447 lines
10 KiB
C
447 lines
10 KiB
C
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/*--------------------------------------------------------------------------
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N76E003.H
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Header file for Nuvoton N76E003
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--------------------------------------------------------------------------*/
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__sfr __at(0x80) P0;
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#define __SFR_P0 0x80
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__sfr __at(0x81) SP;
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#define __SFR_SP 0x81
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__sfr __at(0x82) DPL;
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#define __SFR_DPL 0x82
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__sfr __at(0x83) DPH;
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#define __SFR_DPH 0x83
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__sfr __at(0x84) RCTRIM0;
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#define __SFR_RCTRIM0 0x84
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__sfr __at(0x85) RCTRIM1;
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#define __SFR_RCTRIM1 0x85
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__sfr __at(0x86) RWK;
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#define __SFR_RWK 0x86
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__sfr __at(0x87) PCON;
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#define __SFR_PCON 0x87
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__sfr __at(0x88) TCON;
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#define __SFR_TCON 0x88
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__sfr __at(0x89) TMOD;
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#define __SFR_TMOD 0x89
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__sfr __at(0x8A) TL0;
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#define __SFR_TL0 0x8A
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__sfr __at(0x8B) TL1;
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#define __SFR_TL1 0x8B
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__sfr __at(0x8C) TH0;
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#define __SFR_TH0 0x8C
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__sfr __at(0x8D) TH1;
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#define __SFR_TH1 0x8D
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__sfr __at(0x8E) CKCON;
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#define __SFR_CKCON 0x8E
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__sfr __at(0x8F) WKCON;
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#define __SFR_WKCON 0x8F
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__sfr __at(0x90) P1;
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#define __SFR_P1 0x90
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__sfr __at(0x91) SFRS; //TA Protection
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#define __SFR_SFRS 0x91
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__sfr __at(0x92) CAPCON0;
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#define __SFR_CAPCON0 0x92
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__sfr __at(0x93) CAPCON1;
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#define __SFR_CAPCON1 0x93
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__sfr __at(0x94) CAPCON2;
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#define __SFR_CAPCON2 0x94
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__sfr __at(0x95) CKDIV;
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#define __SFR_CKDIV 0x95
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__sfr __at(0x96) CKSWT; //TA Protection
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#define __SFR_CKSWT 0x96
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__sfr __at(0x97) CKEN; //TA Protection
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#define __SFR_CKEN 0x97
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__sfr __at(0x98) SCON;
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#define __SFR_SCON 0x98
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__sfr __at(0x99) SBUF;
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#define __SFR_SBUF 0x99
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__sfr __at(0x9A) SBUF_1;
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#define __SFR_SBUF_1 0x9A
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__sfr __at(0x9B) EIE;
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#define __SFR_EIE 0x9B
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__sfr __at(0x9C) EIE1;
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#define __SFR_EIE1 0x9C
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__sfr __at(0x9F) CHPCON; //TA Protection
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#define __SFR_CHPCON 0x9F
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__sfr __at(0xA0) P2;
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#define __SFR_P2 0xA0
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__sfr __at(0xA2) AUXR1;
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#define __SFR_AUXR1 0xA2
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__sfr __at(0xA3) BODCON0; //TA Protection
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#define __SFR_BODCON0 0xA3
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__sfr __at(0xA4) IAPTRG; //TA Protection
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#define __SFR_IAPTRG 0xA4
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__sfr __at(0xA5) IAPUEN; //TA Protection
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#define __SFR_IAPUEN 0xA5
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__sfr __at(0xA6) IAPAL;
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#define __SFR_IAPAL 0xA6
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__sfr __at(0xA7) IAPAH;
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#define __SFR_IAPAH 0xA7
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__sfr __at(0xA8) IE;
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#define __SFR_IE 0xA8
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__sfr __at(0xA9) SADDR;
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#define __SFR_SADDR 0xA9
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__sfr __at(0xAA) WDCON; //TA Protection
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#define __SFR_WDCON 0xAA
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__sfr __at(0xAB) BODCON1; //TA Protection
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#define __SFR_BODCON1 0xAB
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__sfr __at(0xAC) P3M1;
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#define __SFR_P3M1 0xAC
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__sfr __at(0xAC) P3S; //Page1
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#define __SFR_P3S 0xAC
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__sfr __at(0xAD) P3M2;
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#define __SFR_P3M2 0xAD
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__sfr __at(0xAD) P3SR; //Page1
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#define __SFR_P3SR 0xAD
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__sfr __at(0xAE) IAPFD;
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#define __SFR_IAPFD 0xAE
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__sfr __at(0xAF) IAPCN;
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#define __SFR_IAPCN 0xAF
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__sfr __at(0xB0) P3;
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#define __SFR_P3 0xB0
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__sfr __at(0xB1) P0M1;
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#define __SFR_P0M1 0xB1
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__sfr __at(0xB1) P0S; //Page1
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#define __SFR_P0S 0xB1
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__sfr __at(0xB2) P0M2;
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#define __SFR_P0M2 0xB2
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__sfr __at(0xB2) P0SR; //Page1
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#define __SFR_P0SR 0xB2
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__sfr __at(0xB3) P1M1;
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#define __SFR_P1M1 0xB3
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__sfr __at(0xB3) P1S; //Page1
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#define __SFR_P1S 0xB3
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__sfr __at(0xB4) P1M2;
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#define __SFR_P1M2 0xB4
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__sfr __at(0xB4) P1SR; //Page1
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#define __SFR_P1SR 0xB4
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__sfr __at(0xB5) P2S;
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#define __SFR_P2S 0xB5
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__sfr __at(0xB7) IPH;
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#define __SFR_IPH 0xB7
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__sfr __at(0xB7) PWMINTC; //Page1
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#define __SFR_PWMINTC 0xB7
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__sfr __at(0xB8) IP;
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#define __SFR_IP 0xB8
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__sfr __at(0xB9) SADEN;
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#define __SFR_SADEN 0xB9
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__sfr __at(0xBA) SADEN_1;
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#define __SFR_SADEN_1 0xBA
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__sfr __at(0xBB) SADDR_1;
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#define __SFR_SADDR_1 0xBB
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__sfr __at(0xBC) I2DAT;
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#define __SFR_I2DAT 0xBC
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__sfr __at(0xBD) I2STAT;
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#define __SFR_I2STAT 0xBD
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__sfr __at(0xBE) I2CLK;
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#define __SFR_I2CLK 0xBE
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__sfr __at(0xBF) I2TOC;
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#define __SFR_I2TOC 0xBF
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__sfr __at(0xC0) I2CON;
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#define __SFR_I2CON 0xC0
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__sfr __at(0xC1) I2ADDR;
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#define __SFR_I2ADDR 0xC1
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__sfr __at(0xC2) ADCRL;
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#define __SFR_ADCRL 0xC2
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__sfr __at(0xC3) ADCRH;
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#define __SFR_ADCRH 0xC3
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__sfr __at(0xC4) T3CON;
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#define __SFR_T3CON 0xC4
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__sfr __at(0xC4) PWM4H; //Page1
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#define __SFR_PWM4H 0xC4
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__sfr __at(0xC5) RL3;
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#define __SFR_RL3 0xC5
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__sfr __at(0xC5) PWM5H; //Page1
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#define __SFR_PWM5H 0xC5
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__sfr __at(0xC6) RH3;
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#define __SFR_RH3 0xC6
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__sfr __at(0xC6) PIOCON1; //Page1
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#define __SFR_PIOCON1 0xC6
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__sfr __at(0xC7) TA;
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#define __SFR_TA 0xC7
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__sfr __at(0xC8) T2CON;
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#define __SFR_T2CON 0xC8
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__sfr __at(0xC9) T2MOD;
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#define __SFR_T2MOD 0xC9
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__sfr __at(0xCA) RCMP2L;
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#define __SFR_RCMP2L 0xCA
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__sfr __at(0xCB) RCMP2H;
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#define __SFR_RCMP2H 0xCB
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__sfr __at(0xCC) TL2;
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#define __SFR_TL2 0xCC
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__sfr __at(0xCC) PWM4L; //Page1
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#define __SFR_PWM4L 0xCC
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__sfr __at(0xCD) TH2;
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#define __SFR_TH2 0xCD
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__sfr __at(0xCD) PWM5L; //Page1
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#define __SFR_PWM5L 0xCD
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__sfr __at(0xCE) ADCMPL;
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#define __SFR_ADCMPL 0xCE
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__sfr __at(0xCF) ADCMPH;
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#define __SFR_ADCMPH 0xCF
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__sfr __at(0xD0) PSW;
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#define __SFR_PSW 0xD0
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__sfr __at(0xD1) PWMPH;
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#define __SFR_PWMPH 0xD1
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__sfr __at(0xD2) PWM0H;
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#define __SFR_PWM0H 0xD2
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__sfr __at(0xD3) PWM1H;
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#define __SFR_PWM1H 0xD3
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__sfr __at(0xD4) PWM2H;
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#define __SFR_PWM2H 0xD4
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__sfr __at(0xD5) PWM3H;
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#define __SFR_PWM3H 0xD5
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__sfr __at(0xD6) PNP;
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#define __SFR_PNP 0xD6
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__sfr __at(0xD7) FBD;
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#define __SFR_FBD 0xD7
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__sfr __at(0xD8) PWMCON0;
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#define __SFR_PWMCON0 0xD8
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__sfr __at(0xD9) PWMPL;
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#define __SFR_PWMPL 0xD9
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__sfr __at(0xDA) PWM0L;
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#define __SFR_PWM0L 0xDA
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__sfr __at(0xDB) PWM1L;
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#define __SFR_PWM1L 0xDB
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__sfr __at(0xDC) PWM2L;
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#define __SFR_PWM2L 0xDC
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__sfr __at(0xDD) PWM3L;
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#define __SFR_PWM3L 0xDD
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__sfr __at(0xDE) PIOCON0;
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#define __SFR_PIOCON0 0xDE
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__sfr __at(0xDF) PWMCON1;
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#define __SFR_PWMCON1 0xDF
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__sfr __at(0xE0) ACC;
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#define __SFR_ACC 0xE0
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__sfr __at(0xE1) ADCCON1;
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#define __SFR_ADCCON1 0xE1
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__sfr __at(0xE2) ADCCON2;
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#define __SFR_ADCCON2 0xE2
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__sfr __at(0xE3) ADCDLY;
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#define __SFR_ADCDLY 0xE3
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__sfr __at(0xE4) C0L;
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#define __SFR_C0L 0xE4
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__sfr __at(0xE5) C0H;
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#define __SFR_C0H 0xE5
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__sfr __at(0xE6) C1L;
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#define __SFR_C1L 0xE6
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__sfr __at(0xE7) C1H;
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#define __SFR_C1H 0xE7
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__sfr __at(0xE8) ADCCON0;
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#define __SFR_ADCCON0 0xE8
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__sfr __at(0xE9) PICON;
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#define __SFR_PICON 0xE9
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__sfr __at(0xEA) PINEN;
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#define __SFR_PINEN 0xEA
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__sfr __at(0xEB) PIPEN;
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#define __SFR_PIPEN 0xEB
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__sfr __at(0xEC) PIF;
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#define __SFR_PIF 0xEC
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__sfr __at(0xED) C2L;
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#define __SFR_C2L 0xED
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__sfr __at(0xEE) C2H;
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#define __SFR_C2H 0xEE
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__sfr __at(0xEF) EIP;
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#define __SFR_EIP 0xEF
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__sfr __at(0xF0) B;
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#define __SFR_B 0xF0
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__sfr __at(0xF1) CAPCON3;
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#define __SFR_CAPCON3 0xF1
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__sfr __at(0xF2) CAPCON4;
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#define __SFR_CAPCON4 0xF2
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__sfr __at(0xF3) SPCR;
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#define __SFR_SPCR 0xF3
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__sfr __at(0xF3) SPCR2; //Page1
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#define __SFR_SPCR2 0xF3
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__sfr __at(0xF4) SPSR;
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#define __SFR_SPSR 0xF4
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__sfr __at(0xF5) SPDR;
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#define __SFR_SPDR 0xF5
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__sfr __at(0xF6) AINDIDS;
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#define __SFR_AINDIDS 0xF6
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__sfr __at(0xF7) EIPH;
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#define __SFR_EIPH 0xF7
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__sfr __at(0xF8) SCON_1;
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#define __SFR_SCON_1 0xF8
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__sfr __at(0xF9) PDTEN; //TA Protection
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#define __SFR_PDTEN 0xF9
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__sfr __at(0xFA) PDTCNT; //TA Protection
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#define __SFR_PDTCNT 0xFA
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__sfr __at(0xFB) PMEN;
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#define __SFR_PMEN 0xFB
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__sfr __at(0xFC) PMD;
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#define __SFR_PMD 0xFC
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__sfr __at(0xFE) EIP1;
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#define __SFR_EIP1 0xFE
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__sfr __at(0xFF) EIPH1;
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#define __SFR_EIPH1 0xFF
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/* BIT Registers */
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/* SCON_1 */
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__sbit __at(__SFR_SCON_1^7) SM0_1;
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__sbit __at(__SFR_SCON_1^7) FE_1;
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__sbit __at(__SFR_SCON_1^6) SM1_1;
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__sbit __at(__SFR_SCON_1^5) SM2_1;
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__sbit __at(__SFR_SCON_1^4) REN_1;
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__sbit __at(__SFR_SCON_1^3) TB8_1;
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__sbit __at(__SFR_SCON_1^2) RB8_1;
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__sbit __at(__SFR_SCON_1^1) TI_1;
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__sbit __at(__SFR_SCON_1^0) RI_1;
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/* ADCCON0 */
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__sbit __at(__SFR_ADCCON0^7) ADCF;
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__sbit __at(__SFR_ADCCON0^6) ADCS;
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__sbit __at(__SFR_ADCCON0^5) ETGSEL1;
|
||
|
|
__sbit __at(__SFR_ADCCON0^4) ETGSEL0;
|
||
|
|
__sbit __at(__SFR_ADCCON0^3) ADCHS3;
|
||
|
|
__sbit __at(__SFR_ADCCON0^2) ADCHS2;
|
||
|
|
__sbit __at(__SFR_ADCCON0^1) ADCHS1;
|
||
|
|
__sbit __at(__SFR_ADCCON0^0) ADCHS0;
|
||
|
|
|
||
|
|
/* PWMCON0 */
|
||
|
|
__sbit __at(__SFR_PWMCON0^7) PWMRUN;
|
||
|
|
__sbit __at(__SFR_PWMCON0^6) LOAD;
|
||
|
|
__sbit __at(__SFR_PWMCON0^5) PWMF;
|
||
|
|
__sbit __at(__SFR_PWMCON0^4) CLRPWM;
|
||
|
|
|
||
|
|
|
||
|
|
/* PSW */
|
||
|
|
__sbit __at(__SFR_PSW^7) CY;
|
||
|
|
__sbit __at(__SFR_PSW^6) AC;
|
||
|
|
__sbit __at(__SFR_PSW^5) F0;
|
||
|
|
__sbit __at(__SFR_PSW^4) RS1;
|
||
|
|
__sbit __at(__SFR_PSW^3) RS0;
|
||
|
|
__sbit __at(__SFR_PSW^2) OV;
|
||
|
|
__sbit __at(__SFR_PSW^0) P;
|
||
|
|
|
||
|
|
/* T2CON */
|
||
|
|
__sbit __at(__SFR_T2CON^7) TF2;
|
||
|
|
__sbit __at(__SFR_T2CON^2) TR2;
|
||
|
|
__sbit __at(__SFR_T2CON^0) CM_RL2;
|
||
|
|
|
||
|
|
/* I2CON */
|
||
|
|
__sbit __at(__SFR_I2CON^6) I2CEN;
|
||
|
|
__sbit __at(__SFR_I2CON^5) STA;
|
||
|
|
__sbit __at(__SFR_I2CON^4) STO;
|
||
|
|
__sbit __at(__SFR_I2CON^3) SI;
|
||
|
|
__sbit __at(__SFR_I2CON^2) AA;
|
||
|
|
__sbit __at(__SFR_I2CON^0) I2CPX;
|
||
|
|
|
||
|
|
/* IP */
|
||
|
|
__sbit __at(__SFR_IP^6) PADC;
|
||
|
|
__sbit __at(__SFR_IP^5) PBOD;
|
||
|
|
__sbit __at(__SFR_IP^4) PS;
|
||
|
|
__sbit __at(__SFR_IP^3) PT1;
|
||
|
|
__sbit __at(__SFR_IP^2) PX1;
|
||
|
|
__sbit __at(__SFR_IP^1) PT0;
|
||
|
|
__sbit __at(__SFR_IP^0) PX0;
|
||
|
|
|
||
|
|
/* P3 */
|
||
|
|
__sbit __at(__SFR_P3^0) P30;
|
||
|
|
|
||
|
|
|
||
|
|
/* IE */
|
||
|
|
__sbit __at(__SFR_IE^7) EA;
|
||
|
|
__sbit __at(__SFR_IE^6) EADC;
|
||
|
|
__sbit __at(__SFR_IE^5) EBOD;
|
||
|
|
__sbit __at(__SFR_IE^4) ES;
|
||
|
|
__sbit __at(__SFR_IE^3) ET1;
|
||
|
|
__sbit __at(__SFR_IE^2) EX1;
|
||
|
|
__sbit __at(__SFR_IE^1) ET0;
|
||
|
|
__sbit __at(__SFR_IE^0) EX0;
|
||
|
|
|
||
|
|
/* P2 */
|
||
|
|
__sbit __at(__SFR_P2^0) P20;
|
||
|
|
|
||
|
|
/* SCON */
|
||
|
|
__sbit __at(__SFR_SCON^7) SM0;
|
||
|
|
__sbit __at(__SFR_SCON^7) FE;
|
||
|
|
__sbit __at(__SFR_SCON^6) SM1;
|
||
|
|
__sbit __at(__SFR_SCON^5) SM2;
|
||
|
|
__sbit __at(__SFR_SCON^4) REN;
|
||
|
|
__sbit __at(__SFR_SCON^3) TB8;
|
||
|
|
__sbit __at(__SFR_SCON^2) RB8;
|
||
|
|
__sbit __at(__SFR_SCON^1) TI;
|
||
|
|
__sbit __at(__SFR_SCON^0) RI;
|
||
|
|
|
||
|
|
/* P1 */
|
||
|
|
__sbit __at(__SFR_P1^7) P17;
|
||
|
|
__sbit __at(__SFR_P1^6) P16;
|
||
|
|
__sbit __at(__SFR_P1^6) TXD_1;
|
||
|
|
__sbit __at(__SFR_P1^5) P15;
|
||
|
|
__sbit __at(__SFR_P1^4) P14;
|
||
|
|
__sbit __at(__SFR_P1^4) SDA;
|
||
|
|
__sbit __at(__SFR_P1^3) P13;
|
||
|
|
__sbit __at(__SFR_P1^3) SCL;
|
||
|
|
__sbit __at(__SFR_P1^2) P12;
|
||
|
|
__sbit __at(__SFR_P1^1) P11;
|
||
|
|
__sbit __at(__SFR_P1^0) P10;
|
||
|
|
|
||
|
|
/* TCON */
|
||
|
|
__sbit __at(__SFR_TCON^7) TF1;
|
||
|
|
__sbit __at(__SFR_TCON^6) TR1;
|
||
|
|
__sbit __at(__SFR_TCON^5) TF0;
|
||
|
|
__sbit __at(__SFR_TCON^4) TR0;
|
||
|
|
__sbit __at(__SFR_TCON^3) IE1;
|
||
|
|
__sbit __at(__SFR_TCON^2) IT1;
|
||
|
|
__sbit __at(__SFR_TCON^1) IE0;
|
||
|
|
__sbit __at(__SFR_TCON^0) IT0;
|
||
|
|
|
||
|
|
/* P0 */
|
||
|
|
|
||
|
|
__sbit __at(__SFR_P0^7) P07;
|
||
|
|
__sbit __at(__SFR_P0^7) RXD;
|
||
|
|
__sbit __at(__SFR_P0^6) P06;
|
||
|
|
__sbit __at(__SFR_P0^6) TXD;
|
||
|
|
__sbit __at(__SFR_P0^5) P05;
|
||
|
|
__sbit __at(__SFR_P0^4) P04;
|
||
|
|
__sbit __at(__SFR_P0^4) STADC;
|
||
|
|
__sbit __at(__SFR_P0^3) P03;
|
||
|
|
__sbit __at(__SFR_P0^2) P02;
|
||
|
|
__sbit __at(__SFR_P0^2) RXD_1;
|
||
|
|
__sbit __at(__SFR_P0^1) P01;
|
||
|
|
__sbit __at(__SFR_P0^1) MISO;
|
||
|
|
__sbit __at(__SFR_P0^0) P00;
|
||
|
|
__sbit __at(__SFR_P0^0) MOSI;
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*--------------------------------------------------------------------------
|
||
|
|
N76E003.H
|
||
|
|
|
||
|
|
Header file for Nuvoton N76E003
|
||
|
|
--------------------------------------------------------------------------*/
|
||
|
|
|