1193 lines
38 KiB
C
1193 lines
38 KiB
C
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/**
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******************************************************************************
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* @file stm32g0xx_hal_dma.c
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* @author MCD Application Team
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* @brief DMA HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Direct Memory Access (DMA) peripheral:
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* + Initialization and de-initialization functions
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* + IO operation functions
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* + Peripheral State and errors functions
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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(#) Enable and configure the peripheral to be connected to the DMA Channel
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(except for internal SRAM / FLASH memories: no initialization is
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necessary). Please refer to the Reference manual for connection between peripherals
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and DMA requests.
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(#) For a given Channel, program the required configuration through the following parameters:
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Channel request, Transfer Direction, Source and Destination data formats,
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Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
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using HAL_DMA_Init() function.
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Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
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thanks to:
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(##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE();
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(##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE();
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(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
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detection.
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(#) Use HAL_DMA_Abort() function to abort the current transfer
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-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
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*** Polling mode IO operation ***
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=================================
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[..]
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(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
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address and destination address and the Length of data to be transferred
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(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
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case a fixed Timeout can be configured by User depending from his application.
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*** Interrupt mode IO operation ***
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===================================
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[..]
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(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
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(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
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(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
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Source address and destination address and the Length of data to be transferred.
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In this case the DMA interrupt is configured
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(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
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(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
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add his own function to register callbacks with HAL_DMA_RegisterCallback().
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*** DMA HAL driver macros list ***
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=============================================
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[..]
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Below the list of macros in DMA HAL driver.
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(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
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(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
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(+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
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(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
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(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
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(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
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(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
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[..]
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(@) You can refer to the DMA HAL driver header file for more useful macros
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32g0xx_hal.h"
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/** @addtogroup STM32G0xx_HAL_Driver
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* @{
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*/
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/** @defgroup DMA DMA
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* @brief DMA HAL module driver
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* @{
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*/
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#ifdef HAL_DMA_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup DMA_Private_Functions DMA Private Functions
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* @{
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*/
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static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
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static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
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/**
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* @}
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*/
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/* Exported functions ---------------------------------------------------------*/
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/** @defgroup DMA_Exported_Functions DMA Exported Functions
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* @{
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*/
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/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and de-initialization functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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This section provides functions allowing to initialize the DMA Channel source
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and destination addresses, incrementation and data sizes, transfer direction,
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circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
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[..]
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The HAL_DMA_Init() function follows the DMA configuration procedures as described in
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reference manual.
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@endverbatim
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* @{
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*/
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/**
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* @brief Initialize the DMA according to the specified
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* parameters in the DMA_InitTypeDef and initialize the associated handle.
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* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Channel.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
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{
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/* Check the DMA handle allocation */
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if (hdma == NULL)
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{
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return HAL_ERROR;
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}
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/* Check the parameters */
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assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
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assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
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assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
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assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
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assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
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assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
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assert_param(IS_DMA_MODE(hdma->Init.Mode));
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assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
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assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
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/* Compute the channel index */
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#if defined(DMA2)
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if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
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{
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/* DMA1 */
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
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hdma->DmaBaseAddress = DMA1;
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}
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else
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{
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/* DMA2 */
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
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hdma->DmaBaseAddress = DMA2;
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}
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#else
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
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#endif
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/* Change DMA peripheral state */
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hdma->State = HAL_DMA_STATE_BUSY;
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/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
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CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
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DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
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DMA_CCR_DIR | DMA_CCR_MEM2MEM));
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/* Set the DMA Channel configuration */
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SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \
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hdma->Init.PeriphInc | hdma->Init.MemInc | \
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hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | \
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hdma->Init.Mode | hdma->Init.Priority));
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/* Initialize parameters for DMAMUX channel :
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DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
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*/
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DMA_CalcDMAMUXChannelBaseAndMask(hdma);
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if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
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{
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/* if memory to memory force the request to 0*/
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hdma->Init.Request = DMA_REQUEST_MEM2MEM;
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}
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/* Set peripheral request to DMAMUX channel */
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hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
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/* Clear the DMAMUX synchro overrun flag */
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hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
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if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
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{
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/* Initialize parameters for DMAMUX request generator :
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DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
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*/
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DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
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/* Reset the DMAMUX request generator register*/
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hdma->DMAmuxRequestGen->RGCR = 0U;
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/* Clear the DMAMUX request generator overrun flag */
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hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
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}
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else
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{
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hdma->DMAmuxRequestGen = 0U;
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hdma->DMAmuxRequestGenStatus = 0U;
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hdma->DMAmuxRequestGenStatusMask = 0U;
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}
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/* Initialize the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Initialize the DMA state*/
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hdma->State = HAL_DMA_STATE_READY;
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/* Release Lock */
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__HAL_UNLOCK(hdma);
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return HAL_OK;
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}
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/**
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* @brief DeInitialize the DMA peripheral.
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* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Channel.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
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{
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/* Check the DMA handle allocation */
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if (NULL == hdma)
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{
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return HAL_ERROR;
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}
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/* Check the parameters */
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assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
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/* Disable the selected DMA Channelx */
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__HAL_DMA_DISABLE(hdma);
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/* Compute the channel index */
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#if defined(DMA2)
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if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
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{
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/* DMA1 */
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
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hdma->DmaBaseAddress = DMA1;
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}
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else
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{
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/* DMA2 */
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
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hdma->DmaBaseAddress = DMA2;
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}
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#else
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
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#endif
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/* Reset DMA Channel control register */
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hdma->Instance->CCR = 0U;
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/* Clear all flags */
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#if defined(DMA2)
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hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
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#else
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__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
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#endif
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/* Initialize parameters for DMAMUX channel :
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DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
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DMA_CalcDMAMUXChannelBaseAndMask(hdma);
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/* Reset the DMAMUX channel that corresponds to the DMA channel */
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hdma->DMAmuxChannel->CCR = 0U;
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/* Clear the DMAMUX synchro overrun flag */
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hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
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/* Reset Request generator parameters if any */
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if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
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{
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/* Initialize parameters for DMAMUX request generator :
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DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
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*/
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DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
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/* Reset the DMAMUX request generator register*/
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hdma->DMAmuxRequestGen->RGCR = 0U;
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/* Clear the DMAMUX request generator overrun flag */
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hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
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}
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hdma->DMAmuxRequestGen = 0U;
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hdma->DMAmuxRequestGenStatus = 0U;
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hdma->DMAmuxRequestGenStatusMask = 0U;
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/* Clean callbacks */
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hdma->XferCpltCallback = NULL;
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hdma->XferHalfCpltCallback = NULL;
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hdma->XferErrorCallback = NULL;
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hdma->XferAbortCallback = NULL;
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/* Initialize the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Initialize the DMA state */
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hdma->State = HAL_DMA_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hdma);
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return HAL_OK;
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}
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/**
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* @}
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*/
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/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
|
||
|
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* @brief Input and Output operation functions
|
||
|
|
*
|
||
|
|
@verbatim
|
||
|
|
===============================================================================
|
||
|
|
##### IO operation functions #####
|
||
|
|
===============================================================================
|
||
|
|
[..] This section provides functions allowing to:
|
||
|
|
(+) Configure the source, destination address and data length and Start DMA transfer
|
||
|
|
(+) Configure the source, destination address and data length and
|
||
|
|
Start DMA transfer with interrupt
|
||
|
|
(+) Abort DMA transfer
|
||
|
|
(+) Poll for transfer complete
|
||
|
|
(+) Handle DMA interrupt request
|
||
|
|
(+) Register and Unregister DMA callbacks
|
||
|
|
|
||
|
|
@endverbatim
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Start the DMA Transfer.
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @param SrcAddress The source memory Buffer address
|
||
|
|
* @param DstAddress The destination memory Buffer address
|
||
|
|
* @param DataLength The length of data to be transferred from source to destination
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||
|
|
{
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||
|
|
|
||
|
|
/* Process locked */
|
||
|
|
__HAL_LOCK(hdma);
|
||
|
|
|
||
|
|
if (hdma->State == HAL_DMA_STATE_READY)
|
||
|
|
{
|
||
|
|
/* Change DMA peripheral state */
|
||
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
||
|
|
|
||
|
|
/* Initialize the error code */
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||
|
|
|
||
|
|
/* Disable the peripheral */
|
||
|
|
__HAL_DMA_DISABLE(hdma);
|
||
|
|
|
||
|
|
/* Configure the source, destination address and the data length & clear flags*/
|
||
|
|
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||
|
|
|
||
|
|
/* Enable the Peripheral */
|
||
|
|
__HAL_DMA_ENABLE(hdma);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Change the error code */
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
/* Return error status */
|
||
|
|
status = HAL_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Start the DMA Transfer with interrupt enabled.
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @param SrcAddress The source memory Buffer address
|
||
|
|
* @param DstAddress The destination memory Buffer address
|
||
|
|
* @param DataLength The length of data to be transferred from source to destination
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||
|
|
{
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||
|
|
|
||
|
|
/* Process locked */
|
||
|
|
__HAL_LOCK(hdma);
|
||
|
|
|
||
|
|
if (hdma->State == HAL_DMA_STATE_READY)
|
||
|
|
{
|
||
|
|
/* Change DMA peripheral state */
|
||
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||
|
|
|
||
|
|
/* Disable the peripheral */
|
||
|
|
__HAL_DMA_DISABLE(hdma);
|
||
|
|
|
||
|
|
/* Configure the source, destination address and the data length & clear flags*/
|
||
|
|
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||
|
|
|
||
|
|
/* Enable the transfer complete interrupt */
|
||
|
|
/* Enable the transfer Error interrupt */
|
||
|
|
if (NULL != hdma->XferHalfCpltCallback)
|
||
|
|
{
|
||
|
|
/* Enable the Half transfer complete interrupt as well */
|
||
|
|
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
||
|
|
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check if DMAMUX Synchronization is enabled*/
|
||
|
|
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
|
||
|
|
{
|
||
|
|
/* Enable DMAMUX sync overrun IT*/
|
||
|
|
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
||
|
|
{
|
||
|
|
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
|
||
|
|
/* enable the request gen overrun IT*/
|
||
|
|
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable the Peripheral */
|
||
|
|
__HAL_DMA_ENABLE(hdma);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Change the error code */
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
/* Return error status */
|
||
|
|
status = HAL_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Abort the DMA Transfer.
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||
|
|
{
|
||
|
|
/* Check the DMA peripheral handle */
|
||
|
|
if (NULL == hdma)
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check the DMA peripheral state */
|
||
|
|
if (hdma->State != HAL_DMA_STATE_BUSY)
|
||
|
|
{
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
return HAL_ERROR;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable DMA IT */
|
||
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||
|
|
|
||
|
|
/* disable the DMAMUX sync overrun IT*/
|
||
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
||
|
|
|
||
|
|
/* Disable the channel */
|
||
|
|
__HAL_DMA_DISABLE(hdma);
|
||
|
|
|
||
|
|
/* Clear all flags */
|
||
|
|
#if defined(DMA2)
|
||
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||
|
|
#else
|
||
|
|
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Clear the DMAMUX synchro overrun flag */
|
||
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||
|
|
|
||
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
||
|
|
{
|
||
|
|
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
||
|
|
/* disable the request gen overrun IT*/
|
||
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
||
|
|
|
||
|
|
/* Clear the DMAMUX request generator overrun flag */
|
||
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Change the DMA state */
|
||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
}
|
||
|
|
|
||
|
|
return HAL_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Aborts the DMA Transfer in Interrupt mode.
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
||
|
|
{
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
|
||
|
|
if (hdma->State != HAL_DMA_STATE_BUSY)
|
||
|
|
{
|
||
|
|
/* no transfer ongoing */
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||
|
|
|
||
|
|
status = HAL_ERROR;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Disable DMA IT */
|
||
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||
|
|
|
||
|
|
/* Disable the channel */
|
||
|
|
__HAL_DMA_DISABLE(hdma);
|
||
|
|
|
||
|
|
/* disable the DMAMUX sync overrun IT*/
|
||
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
||
|
|
|
||
|
|
/* Clear all flags */
|
||
|
|
#if defined(DMA2)
|
||
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||
|
|
#else
|
||
|
|
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Clear the DMAMUX synchro overrun flag */
|
||
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||
|
|
|
||
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
||
|
|
{
|
||
|
|
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
||
|
|
/* disable the request gen overrun IT*/
|
||
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
||
|
|
|
||
|
|
/* Clear the DMAMUX request generator overrun flag */
|
||
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Change the DMA state */
|
||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
/* Call User Abort callback */
|
||
|
|
if (hdma->XferAbortCallback != NULL)
|
||
|
|
{
|
||
|
|
hdma->XferAbortCallback(hdma);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Polling for transfer complete.
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @param CompleteLevel Specifies the DMA level complete.
|
||
|
|
* @param Timeout Timeout duration.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
|
||
|
|
{
|
||
|
|
uint32_t temp;
|
||
|
|
uint32_t tickstart;
|
||
|
|
|
||
|
|
if (hdma->State != HAL_DMA_STATE_BUSY)
|
||
|
|
{
|
||
|
|
/* no transfer ongoing */
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
return HAL_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Polling mode not supported in circular mode */
|
||
|
|
if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
|
||
|
|
{
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||
|
|
return HAL_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Get the level transfer complete flag */
|
||
|
|
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||
|
|
{
|
||
|
|
/* Transfer Complete flag */
|
||
|
|
temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Half Transfer Complete flag */
|
||
|
|
temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Get tick */
|
||
|
|
tickstart = HAL_GetTick();
|
||
|
|
|
||
|
|
#if defined(DMA2)
|
||
|
|
while ((hdma->DmaBaseAddress->ISR & temp) == 0U)
|
||
|
|
{
|
||
|
|
if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U)
|
||
|
|
{
|
||
|
|
/* When a DMA transfer error occurs */
|
||
|
|
/* A hardware clear of its EN bits is performed */
|
||
|
|
/* Clear all flags */
|
||
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||
|
|
|
||
|
|
/* Update error code */
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||
|
|
|
||
|
|
/* Change the DMA state */
|
||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
return HAL_ERROR;
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
while (0U == __HAL_DMA_GET_FLAG(hdma, temp))
|
||
|
|
{
|
||
|
|
if (0U != __HAL_DMA_GET_FLAG(hdma, (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))))
|
||
|
|
{
|
||
|
|
/* When a DMA transfer error occurs */
|
||
|
|
/* A hardware clear of its EN bits is performed */
|
||
|
|
/* Clear all flags */
|
||
|
|
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
|
||
|
|
|
||
|
|
/* Update error code */
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||
|
|
|
||
|
|
/* Change the DMA state */
|
||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
return HAL_ERROR;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
/* Check for the Timeout */
|
||
|
|
if (Timeout != HAL_MAX_DELAY)
|
||
|
|
{
|
||
|
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||
|
|
{
|
||
|
|
/* Update error code */
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
||
|
|
|
||
|
|
/* Change the DMA state */
|
||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
return HAL_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*Check for DMAMUX Request generator (if used) overrun status */
|
||
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
||
|
|
{
|
||
|
|
/* if using DMAMUX request generator Check for DMAMUX request generator overrun */
|
||
|
|
if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
|
||
|
|
{
|
||
|
|
/* Disable the request gen overrun interrupt */
|
||
|
|
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
|
||
|
|
|
||
|
|
/* Clear the DMAMUX request generator overrun flag */
|
||
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
||
|
|
|
||
|
|
/* Update error code */
|
||
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check for DMAMUX Synchronization overrun */
|
||
|
|
if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
|
||
|
|
{
|
||
|
|
/* Clear the DMAMUX synchro overrun flag */
|
||
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||
|
|
|
||
|
|
/* Update error code */
|
||
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||
|
|
{
|
||
|
|
/* Clear the transfer complete flag */
|
||
|
|
#if defined(DMA2)
|
||
|
|
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU));
|
||
|
|
#else
|
||
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Process unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
||
|
|
all transfers are complete) */
|
||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Clear the half transfer complete flag */
|
||
|
|
#if defined(DMA2)
|
||
|
|
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
|
||
|
|
#else
|
||
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
return HAL_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Handle DMA interrupt request.
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||
|
|
{
|
||
|
|
#if defined(DMA2)
|
||
|
|
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
|
||
|
|
#else
|
||
|
|
uint32_t flag_it = DMA1->ISR;
|
||
|
|
#endif
|
||
|
|
uint32_t source_it = hdma->Instance->CCR;
|
||
|
|
|
||
|
|
/* Half Transfer Complete Interrupt management ******************************/
|
||
|
|
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
|
||
|
|
{
|
||
|
|
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
||
|
|
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||
|
|
{
|
||
|
|
/* Disable the half transfer interrupt */
|
||
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
||
|
|
}
|
||
|
|
/* Clear the half transfer complete flag */
|
||
|
|
#if defined(DMA2)
|
||
|
|
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
|
||
|
|
#else
|
||
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* DMA peripheral state is not updated in Half Transfer */
|
||
|
|
/* but in Transfer Complete case */
|
||
|
|
|
||
|
|
if (hdma->XferHalfCpltCallback != NULL)
|
||
|
|
{
|
||
|
|
/* Half transfer callback */
|
||
|
|
hdma->XferHalfCpltCallback(hdma);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Transfer Complete Interrupt management ***********************************/
|
||
|
|
else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC)))
|
||
|
|
{
|
||
|
|
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||
|
|
{
|
||
|
|
/* Disable the transfer complete and error interrupt */
|
||
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
|
||
|
|
|
||
|
|
/* Change the DMA state */
|
||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
||
|
|
}
|
||
|
|
/* Clear the transfer complete flag */
|
||
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
if (hdma->XferCpltCallback != NULL)
|
||
|
|
{
|
||
|
|
/* Transfer complete callback */
|
||
|
|
hdma->XferCpltCallback(hdma);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Transfer Error Interrupt management **************************************/
|
||
|
|
else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
|
||
|
|
{
|
||
|
|
/* When a DMA transfer error occurs */
|
||
|
|
/* A hardware clear of its EN bits is performed */
|
||
|
|
/* Disable ALL DMA IT */
|
||
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||
|
|
|
||
|
|
/* Clear all flags */
|
||
|
|
#if defined(DMA2)
|
||
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||
|
|
#else
|
||
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Update error code */
|
||
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||
|
|
|
||
|
|
/* Change the DMA state */
|
||
|
|
hdma->State = HAL_DMA_STATE_READY;
|
||
|
|
|
||
|
|
/* Process Unlocked */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
if (hdma->XferErrorCallback != NULL)
|
||
|
|
{
|
||
|
|
/* Transfer error callback */
|
||
|
|
hdma->XferErrorCallback(hdma);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Nothing To Do */
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Register callbacks
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @param CallbackID User Callback identifier
|
||
|
|
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||
|
|
* @param pCallback Pointer to private callbacsk function which has pointer to
|
||
|
|
* a DMA_HandleTypeDef structure as parameter.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
|
||
|
|
{
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
|
||
|
|
/* Process locked */
|
||
|
|
__HAL_LOCK(hdma);
|
||
|
|
|
||
|
|
if (hdma->State == HAL_DMA_STATE_READY)
|
||
|
|
{
|
||
|
|
switch (CallbackID)
|
||
|
|
{
|
||
|
|
case HAL_DMA_XFER_CPLT_CB_ID:
|
||
|
|
hdma->XferCpltCallback = pCallback;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||
|
|
hdma->XferHalfCpltCallback = pCallback;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case HAL_DMA_XFER_ERROR_CB_ID:
|
||
|
|
hdma->XferErrorCallback = pCallback;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case HAL_DMA_XFER_ABORT_CB_ID:
|
||
|
|
hdma->XferAbortCallback = pCallback;
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
status = HAL_ERROR;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Release Lock */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief UnRegister callbacks
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @param CallbackID User Callback identifier
|
||
|
|
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
|
||
|
|
{
|
||
|
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
|
||
|
|
/* Process locked */
|
||
|
|
__HAL_LOCK(hdma);
|
||
|
|
|
||
|
|
if (hdma->State == HAL_DMA_STATE_READY)
|
||
|
|
{
|
||
|
|
switch (CallbackID)
|
||
|
|
{
|
||
|
|
case HAL_DMA_XFER_CPLT_CB_ID:
|
||
|
|
hdma->XferCpltCallback = NULL;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||
|
|
hdma->XferHalfCpltCallback = NULL;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case HAL_DMA_XFER_ERROR_CB_ID:
|
||
|
|
hdma->XferErrorCallback = NULL;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case HAL_DMA_XFER_ABORT_CB_ID:
|
||
|
|
hdma->XferAbortCallback = NULL;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case HAL_DMA_XFER_ALL_CB_ID:
|
||
|
|
hdma->XferCpltCallback = NULL;
|
||
|
|
hdma->XferHalfCpltCallback = NULL;
|
||
|
|
hdma->XferErrorCallback = NULL;
|
||
|
|
hdma->XferAbortCallback = NULL;
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
status = HAL_ERROR;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
status = HAL_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Release Lock */
|
||
|
|
__HAL_UNLOCK(hdma);
|
||
|
|
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
|
||
|
|
* @brief Peripheral State and Errors functions
|
||
|
|
*
|
||
|
|
@verbatim
|
||
|
|
===============================================================================
|
||
|
|
##### Peripheral State and Errors functions #####
|
||
|
|
===============================================================================
|
||
|
|
[..]
|
||
|
|
This subsection provides functions allowing to
|
||
|
|
(+) Check the DMA state
|
||
|
|
(+) Get error code
|
||
|
|
|
||
|
|
@endverbatim
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return the DMA handle state.
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @retval HAL state
|
||
|
|
*/
|
||
|
|
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
||
|
|
{
|
||
|
|
/* Return DMA handle state */
|
||
|
|
return hdma->State;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return the DMA error code.
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @retval DMA Error Code
|
||
|
|
*/
|
||
|
|
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
|
||
|
|
{
|
||
|
|
/* Return the DMA error code */
|
||
|
|
return hdma->ErrorCode;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup DMA_Private_Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Sets the DMA Transfer parameter.
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @param SrcAddress The source memory Buffer address
|
||
|
|
* @param DstAddress The destination memory Buffer address
|
||
|
|
* @param DataLength The length of data to be transferred from source to destination
|
||
|
|
* @retval HAL status
|
||
|
|
*/
|
||
|
|
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||
|
|
{
|
||
|
|
/* Clear the DMAMUX synchro overrun flag */
|
||
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||
|
|
|
||
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
||
|
|
{
|
||
|
|
/* Clear the DMAMUX request generator overrun flag */
|
||
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Clear all flags */
|
||
|
|
#if defined(DMA2)
|
||
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||
|
|
#else
|
||
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Configure DMA Channel data length */
|
||
|
|
hdma->Instance->CNDTR = DataLength;
|
||
|
|
|
||
|
|
/* Memory to Peripheral */
|
||
|
|
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||
|
|
{
|
||
|
|
/* Configure DMA Channel destination address */
|
||
|
|
hdma->Instance->CPAR = DstAddress;
|
||
|
|
|
||
|
|
/* Configure DMA Channel source address */
|
||
|
|
hdma->Instance->CMAR = SrcAddress;
|
||
|
|
}
|
||
|
|
/* Peripheral to Memory */
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Configure DMA Channel source address */
|
||
|
|
hdma->Instance->CPAR = SrcAddress;
|
||
|
|
|
||
|
|
/* Configure DMA Channel destination address */
|
||
|
|
hdma->Instance->CMAR = DstAddress;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Updates the DMA handle with the DMAMUX channel and status mask depending on channel number
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
|
||
|
|
{
|
||
|
|
uint32_t channel_number;
|
||
|
|
|
||
|
|
#if defined(DMA2)
|
||
|
|
/* check if instance is not outside the DMA channel range */
|
||
|
|
if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
|
||
|
|
{
|
||
|
|
/* DMA1 */
|
||
|
|
/* Associate a DMA Channel to a DMAMUX channel */
|
||
|
|
hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
|
||
|
|
|
||
|
|
/* Prepare channel_number used for DMAmuxChannelStatusMask computation */
|
||
|
|
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* DMA2 */
|
||
|
|
/* Associate a DMA Channel to a DMAMUX channel */
|
||
|
|
hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));
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||
|
|
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||
|
|
/* Prepare channel_number used for DMAmuxChannelStatusMask computation */
|
||
|
|
channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U);
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
/* Associate a DMA Channel to a DMAMUX channel */
|
||
|
|
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
|
||
|
|
|
||
|
|
/* Prepare channel_number used for DMAmuxChannelStatusMask computation */
|
||
|
|
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */
|
||
|
|
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
|
||
|
|
|
||
|
|
/* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */
|
||
|
|
hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Updates the DMA handle with the DMAMUX request generator params
|
||
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||
|
|
* the configuration information for the specified DMA Channel.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
|
||
|
|
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
|
||
|
|
{
|
||
|
|
uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
|
||
|
|
|
||
|
|
/* DMA Channels are connected to DMAMUX1 request generator blocks*/
|
||
|
|
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
|
||
|
|
|
||
|
|
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
|
||
|
|
|
||
|
|
/* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/
|
||
|
|
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|