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stm32cubeide/test/Debug/test.list

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Initial commit
2021-01-01 14:06:20 +01:00
test.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000011bc 080000c0 080000c0 000100c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000030 0800127c 0800127c 0001127c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080012ac 080012ac 0002000c 2**0
CONTENTS
4 .ARM 00000000 080012ac 080012ac 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 080012ac 080012ac 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080012ac 080012ac 000112ac 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 080012b0 080012b0 000112b0 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 080012b4 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000020 2000000c 080012c0 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000604 2000002c 080012c0 0002002c 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 000026ec 00000000 00000000 00020034 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_abbrev 00000c78 00000000 00000000 00022720 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_aranges 00000348 00000000 00000000 00023398 2**3
CONTENTS, READONLY, DEBUGGING
15 .debug_ranges 000002c0 00000000 00000000 000236e0 2**3
CONTENTS, READONLY, DEBUGGING
16 .debug_macro 0000dd5a 00000000 00000000 000239a0 2**0
CONTENTS, READONLY, DEBUGGING
17 .debug_line 00003b56 00000000 00000000 000316fa 2**0
CONTENTS, READONLY, DEBUGGING
18 .debug_str 00052bb5 00000000 00000000 00035250 2**0
CONTENTS, READONLY, DEBUGGING
19 .comment 0000007b 00000000 00000000 00087e05 2**0
CONTENTS, READONLY
20 .debug_frame 000009dc 00000000 00000000 00087e80 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
080000c0 <__do_global_dtors_aux>:
80000c0: b510 push {r4, lr}
80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
80000c4: 7823 ldrb r3, [r4, #0]
80000c6: 2b00 cmp r3, #0
80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
80000cc: 2b00 cmp r3, #0
80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
80000d4: bf00 nop
80000d6: 2301 movs r3, #1
80000d8: 7023 strb r3, [r4, #0]
80000da: bd10 pop {r4, pc}
80000dc: 2000000c .word 0x2000000c
80000e0: 00000000 .word 0x00000000
80000e4: 08001264 .word 0x08001264
080000e8 <frame_dummy>:
80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
80000ea: b510 push {r4, lr}
80000ec: 2b00 cmp r3, #0
80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
80000f0: 4903 ldr r1, [pc, #12] ; (8000100 <frame_dummy+0x18>)
80000f2: 4804 ldr r0, [pc, #16] ; (8000104 <frame_dummy+0x1c>)
80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
80000f6: bf00 nop
80000f8: bd10 pop {r4, pc}
80000fa: 46c0 nop ; (mov r8, r8)
80000fc: 00000000 .word 0x00000000
8000100: 20000010 .word 0x20000010
8000104: 08001264 .word 0x08001264
08000108 <__udivsi3>:
8000108: 2200 movs r2, #0
800010a: 0843 lsrs r3, r0, #1
800010c: 428b cmp r3, r1
800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
8000110: 0903 lsrs r3, r0, #4
8000112: 428b cmp r3, r1
8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
8000116: 0a03 lsrs r3, r0, #8
8000118: 428b cmp r3, r1
800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
800011c: 0b03 lsrs r3, r0, #12
800011e: 428b cmp r3, r1
8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
8000122: 0c03 lsrs r3, r0, #16
8000124: 428b cmp r3, r1
8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
8000128: 22ff movs r2, #255 ; 0xff
800012a: 0209 lsls r1, r1, #8
800012c: ba12 rev r2, r2
800012e: 0c03 lsrs r3, r0, #16
8000130: 428b cmp r3, r1
8000132: d302 bcc.n 800013a <__udivsi3+0x32>
8000134: 1212 asrs r2, r2, #8
8000136: 0209 lsls r1, r1, #8
8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
800013a: 0b03 lsrs r3, r0, #12
800013c: 428b cmp r3, r1
800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
8000140: e000 b.n 8000144 <__udivsi3+0x3c>
8000142: 0a09 lsrs r1, r1, #8
8000144: 0bc3 lsrs r3, r0, #15
8000146: 428b cmp r3, r1
8000148: d301 bcc.n 800014e <__udivsi3+0x46>
800014a: 03cb lsls r3, r1, #15
800014c: 1ac0 subs r0, r0, r3
800014e: 4152 adcs r2, r2
8000150: 0b83 lsrs r3, r0, #14
8000152: 428b cmp r3, r1
8000154: d301 bcc.n 800015a <__udivsi3+0x52>
8000156: 038b lsls r3, r1, #14
8000158: 1ac0 subs r0, r0, r3
800015a: 4152 adcs r2, r2
800015c: 0b43 lsrs r3, r0, #13
800015e: 428b cmp r3, r1
8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
8000162: 034b lsls r3, r1, #13
8000164: 1ac0 subs r0, r0, r3
8000166: 4152 adcs r2, r2
8000168: 0b03 lsrs r3, r0, #12
800016a: 428b cmp r3, r1
800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
800016e: 030b lsls r3, r1, #12
8000170: 1ac0 subs r0, r0, r3
8000172: 4152 adcs r2, r2
8000174: 0ac3 lsrs r3, r0, #11
8000176: 428b cmp r3, r1
8000178: d301 bcc.n 800017e <__udivsi3+0x76>
800017a: 02cb lsls r3, r1, #11
800017c: 1ac0 subs r0, r0, r3
800017e: 4152 adcs r2, r2
8000180: 0a83 lsrs r3, r0, #10
8000182: 428b cmp r3, r1
8000184: d301 bcc.n 800018a <__udivsi3+0x82>
8000186: 028b lsls r3, r1, #10
8000188: 1ac0 subs r0, r0, r3
800018a: 4152 adcs r2, r2
800018c: 0a43 lsrs r3, r0, #9
800018e: 428b cmp r3, r1
8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
8000192: 024b lsls r3, r1, #9
8000194: 1ac0 subs r0, r0, r3
8000196: 4152 adcs r2, r2
8000198: 0a03 lsrs r3, r0, #8
800019a: 428b cmp r3, r1
800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
800019e: 020b lsls r3, r1, #8
80001a0: 1ac0 subs r0, r0, r3
80001a2: 4152 adcs r2, r2
80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
80001a6: 09c3 lsrs r3, r0, #7
80001a8: 428b cmp r3, r1
80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
80001ac: 01cb lsls r3, r1, #7
80001ae: 1ac0 subs r0, r0, r3
80001b0: 4152 adcs r2, r2
80001b2: 0983 lsrs r3, r0, #6
80001b4: 428b cmp r3, r1
80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
80001b8: 018b lsls r3, r1, #6
80001ba: 1ac0 subs r0, r0, r3
80001bc: 4152 adcs r2, r2
80001be: 0943 lsrs r3, r0, #5
80001c0: 428b cmp r3, r1
80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
80001c4: 014b lsls r3, r1, #5
80001c6: 1ac0 subs r0, r0, r3
80001c8: 4152 adcs r2, r2
80001ca: 0903 lsrs r3, r0, #4
80001cc: 428b cmp r3, r1
80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
80001d0: 010b lsls r3, r1, #4
80001d2: 1ac0 subs r0, r0, r3
80001d4: 4152 adcs r2, r2
80001d6: 08c3 lsrs r3, r0, #3
80001d8: 428b cmp r3, r1
80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
80001dc: 00cb lsls r3, r1, #3
80001de: 1ac0 subs r0, r0, r3
80001e0: 4152 adcs r2, r2
80001e2: 0883 lsrs r3, r0, #2
80001e4: 428b cmp r3, r1
80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
80001e8: 008b lsls r3, r1, #2
80001ea: 1ac0 subs r0, r0, r3
80001ec: 4152 adcs r2, r2
80001ee: 0843 lsrs r3, r0, #1
80001f0: 428b cmp r3, r1
80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
80001f4: 004b lsls r3, r1, #1
80001f6: 1ac0 subs r0, r0, r3
80001f8: 4152 adcs r2, r2
80001fa: 1a41 subs r1, r0, r1
80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
80001fe: 4601 mov r1, r0
8000200: 4152 adcs r2, r2
8000202: 4610 mov r0, r2
8000204: 4770 bx lr
8000206: e7ff b.n 8000208 <__udivsi3+0x100>
8000208: b501 push {r0, lr}
800020a: 2000 movs r0, #0
800020c: f000 f806 bl 800021c <__aeabi_idiv0>
8000210: bd02 pop {r1, pc}
8000212: 46c0 nop ; (mov r8, r8)
08000214 <__aeabi_uidivmod>:
8000214: 2900 cmp r1, #0
8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
8000218: e776 b.n 8000108 <__udivsi3>
800021a: 4770 bx lr
0800021c <__aeabi_idiv0>:
800021c: 4770 bx lr
800021e: 46c0 nop ; (mov r8, r8)
08000220 <main>:
#include "main.h"
void SystemClock_Config(void);
int main(void)
{
8000220: b580 push {r7, lr}
8000222: b086 sub sp, #24
8000224: af00 add r7, sp, #0
HAL_Init();
8000226: f000 f8db bl 80003e0 <HAL_Init>
SystemClock_Config();
800022a: f000 f82c bl 8000286 <SystemClock_Config>
GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_5 | GPIO_PIN_7;
800022e: 1d3b adds r3, r7, #4
8000230: 22a4 movs r2, #164 ; 0xa4
8000232: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000234: 1d3b adds r3, r7, #4
8000236: 2201 movs r2, #1
8000238: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800023a: 1d3b adds r3, r7, #4
800023c: 2200 movs r2, #0
800023e: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
8000240: 1d3b adds r3, r7, #4
8000242: 2200 movs r2, #0
8000244: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000246: 1d3a adds r2, r7, #4
8000248: 2390 movs r3, #144 ; 0x90
800024a: 05db lsls r3, r3, #23
800024c: 0011 movs r1, r2
800024e: 0018 movs r0, r3
8000250: f000 fa00 bl 8000654 <HAL_GPIO_Init>
while (1)
{
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET);
8000254: 2390 movs r3, #144 ; 0x90
8000256: 05db lsls r3, r3, #23
8000258: 2201 movs r2, #1
800025a: 2104 movs r1, #4
800025c: 0018 movs r0, r3
800025e: f000 fb69 bl 8000934 <HAL_GPIO_WritePin>
HAL_Delay(1000);
8000262: 23fa movs r3, #250 ; 0xfa
8000264: 009b lsls r3, r3, #2
8000266: 0018 movs r0, r3
8000268: f000 f91e bl 80004a8 <HAL_Delay>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_RESET);
800026c: 2390 movs r3, #144 ; 0x90
800026e: 05db lsls r3, r3, #23
8000270: 2200 movs r2, #0
8000272: 2104 movs r1, #4
8000274: 0018 movs r0, r3
8000276: f000 fb5d bl 8000934 <HAL_GPIO_WritePin>
HAL_Delay(1000);
800027a: 23fa movs r3, #250 ; 0xfa
800027c: 009b lsls r3, r3, #2
800027e: 0018 movs r0, r3
8000280: f000 f912 bl 80004a8 <HAL_Delay>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET);
8000284: e7e6 b.n 8000254 <main+0x34>
08000286 <SystemClock_Config>:
}
}
void SystemClock_Config(void)
{
8000286: b590 push {r4, r7, lr}
8000288: b091 sub sp, #68 ; 0x44
800028a: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800028c: 2410 movs r4, #16
800028e: 193b adds r3, r7, r4
8000290: 0018 movs r0, r3
8000292: 2330 movs r3, #48 ; 0x30
8000294: 001a movs r2, r3
8000296: 2100 movs r1, #0
8000298: f000 ffdc bl 8001254 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800029c: 003b movs r3, r7
800029e: 0018 movs r0, r3
80002a0: 2310 movs r3, #16
80002a2: 001a movs r2, r3
80002a4: 2100 movs r1, #0
80002a6: f000 ffd5 bl 8001254 <memset>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
80002aa: 0021 movs r1, r4
80002ac: 187b adds r3, r7, r1
80002ae: 2202 movs r2, #2
80002b0: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80002b2: 187b adds r3, r7, r1
80002b4: 2201 movs r2, #1
80002b6: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80002b8: 187b adds r3, r7, r1
80002ba: 2210 movs r2, #16
80002bc: 611a str r2, [r3, #16]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
80002be: 187b adds r3, r7, r1
80002c0: 2200 movs r2, #0
80002c2: 621a str r2, [r3, #32]
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80002c4: 187b adds r3, r7, r1
80002c6: 0018 movs r0, r3
80002c8: f000 fb52 bl 8000970 <HAL_RCC_OscConfig>
80002cc: 1e03 subs r3, r0, #0
80002ce: d001 beq.n 80002d4 <SystemClock_Config+0x4e>
{
Error_Handler();
80002d0: f000 f819 bl 8000306 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80002d4: 003b movs r3, r7
80002d6: 2207 movs r2, #7
80002d8: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
80002da: 003b movs r3, r7
80002dc: 2200 movs r2, #0
80002de: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80002e0: 003b movs r3, r7
80002e2: 2200 movs r2, #0
80002e4: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80002e6: 003b movs r3, r7
80002e8: 2200 movs r2, #0
80002ea: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80002ec: 003b movs r3, r7
80002ee: 2100 movs r1, #0
80002f0: 0018 movs r0, r3
80002f2: f000 fe59 bl 8000fa8 <HAL_RCC_ClockConfig>
80002f6: 1e03 subs r3, r0, #0
80002f8: d001 beq.n 80002fe <SystemClock_Config+0x78>
{
Error_Handler();
80002fa: f000 f804 bl 8000306 <Error_Handler>
}
}
80002fe: 46c0 nop ; (mov r8, r8)
8000300: 46bd mov sp, r7
8000302: b011 add sp, #68 ; 0x44
8000304: bd90 pop {r4, r7, pc}
08000306 <Error_Handler>:
void Error_Handler(void)
{
8000306: b580 push {r7, lr}
8000308: af00 add r7, sp, #0
while (1) { }
800030a: e7fe b.n 800030a <Error_Handler+0x4>
0800030c <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
800030c: b580 push {r7, lr}
800030e: b082 sub sp, #8
8000310: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000312: 4b0f ldr r3, [pc, #60] ; (8000350 <HAL_MspInit+0x44>)
8000314: 699a ldr r2, [r3, #24]
8000316: 4b0e ldr r3, [pc, #56] ; (8000350 <HAL_MspInit+0x44>)
8000318: 2101 movs r1, #1
800031a: 430a orrs r2, r1
800031c: 619a str r2, [r3, #24]
800031e: 4b0c ldr r3, [pc, #48] ; (8000350 <HAL_MspInit+0x44>)
8000320: 699b ldr r3, [r3, #24]
8000322: 2201 movs r2, #1
8000324: 4013 ands r3, r2
8000326: 607b str r3, [r7, #4]
8000328: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800032a: 4b09 ldr r3, [pc, #36] ; (8000350 <HAL_MspInit+0x44>)
800032c: 69da ldr r2, [r3, #28]
800032e: 4b08 ldr r3, [pc, #32] ; (8000350 <HAL_MspInit+0x44>)
8000330: 2180 movs r1, #128 ; 0x80
8000332: 0549 lsls r1, r1, #21
8000334: 430a orrs r2, r1
8000336: 61da str r2, [r3, #28]
8000338: 4b05 ldr r3, [pc, #20] ; (8000350 <HAL_MspInit+0x44>)
800033a: 69da ldr r2, [r3, #28]
800033c: 2380 movs r3, #128 ; 0x80
800033e: 055b lsls r3, r3, #21
8000340: 4013 ands r3, r2
8000342: 603b str r3, [r7, #0]
8000344: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000346: 46c0 nop ; (mov r8, r8)
8000348: 46bd mov sp, r7
800034a: b002 add sp, #8
800034c: bd80 pop {r7, pc}
800034e: 46c0 nop ; (mov r8, r8)
8000350: 40021000 .word 0x40021000
08000354 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000354: b580 push {r7, lr}
8000356: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000358: e7fe b.n 8000358 <NMI_Handler+0x4>
0800035a <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800035a: b580 push {r7, lr}
800035c: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800035e: e7fe b.n 800035e <HardFault_Handler+0x4>
08000360 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000360: b580 push {r7, lr}
8000362: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
8000364: 46c0 nop ; (mov r8, r8)
8000366: 46bd mov sp, r7
8000368: bd80 pop {r7, pc}
0800036a <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
800036a: b580 push {r7, lr}
800036c: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
800036e: 46c0 nop ; (mov r8, r8)
8000370: 46bd mov sp, r7
8000372: bd80 pop {r7, pc}
08000374 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000374: b580 push {r7, lr}
8000376: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000378: f000 f87a bl 8000470 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
800037c: 46c0 nop ; (mov r8, r8)
800037e: 46bd mov sp, r7
8000380: bd80 pop {r7, pc}
08000382 <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
8000382: b580 push {r7, lr}
8000384: af00 add r7, sp, #0
before branch to main program. This call is made inside
the "startup_stm32f0xx.s" file.
User can setups the default system clock (System clock source, PLL Multiplier
and Divider factors, AHB/APBx prescalers and Flash settings).
*/
}
8000386: 46c0 nop ; (mov r8, r8)
8000388: 46bd mov sp, r7
800038a: bd80 pop {r7, pc}
0800038c <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
800038c: 480d ldr r0, [pc, #52] ; (80003c4 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
800038e: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000390: 480d ldr r0, [pc, #52] ; (80003c8 <LoopForever+0x6>)
ldr r1, =_edata
8000392: 490e ldr r1, [pc, #56] ; (80003cc <LoopForever+0xa>)
ldr r2, =_sidata
8000394: 4a0e ldr r2, [pc, #56] ; (80003d0 <LoopForever+0xe>)
movs r3, #0
8000396: 2300 movs r3, #0
b LoopCopyDataInit
8000398: e002 b.n 80003a0 <LoopCopyDataInit>
0800039a <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
800039a: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
800039c: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800039e: 3304 adds r3, #4
080003a0 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80003a0: 18c4 adds r4, r0, r3
cmp r4, r1
80003a2: 428c cmp r4, r1
bcc CopyDataInit
80003a4: d3f9 bcc.n 800039a <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80003a6: 4a0b ldr r2, [pc, #44] ; (80003d4 <LoopForever+0x12>)
ldr r4, =_ebss
80003a8: 4c0b ldr r4, [pc, #44] ; (80003d8 <LoopForever+0x16>)
movs r3, #0
80003aa: 2300 movs r3, #0
b LoopFillZerobss
80003ac: e001 b.n 80003b2 <LoopFillZerobss>
080003ae <FillZerobss>:
FillZerobss:
str r3, [r2]
80003ae: 6013 str r3, [r2, #0]
adds r2, r2, #4
80003b0: 3204 adds r2, #4
080003b2 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80003b2: 42a2 cmp r2, r4
bcc FillZerobss
80003b4: d3fb bcc.n 80003ae <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
80003b6: f7ff ffe4 bl 8000382 <SystemInit>
/* Call static constructors */
bl __libc_init_array
80003ba: f000 ff27 bl 800120c <__libc_init_array>
/* Call the application's entry point.*/
bl main
80003be: f7ff ff2f bl 8000220 <main>
080003c2 <LoopForever>:
LoopForever:
b LoopForever
80003c2: e7fe b.n 80003c2 <LoopForever>
ldr r0, =_estack
80003c4: 20001000 .word 0x20001000
ldr r0, =_sdata
80003c8: 20000000 .word 0x20000000
ldr r1, =_edata
80003cc: 2000000c .word 0x2000000c
ldr r2, =_sidata
80003d0: 080012b4 .word 0x080012b4
ldr r2, =_sbss
80003d4: 2000000c .word 0x2000000c
ldr r4, =_ebss
80003d8: 2000002c .word 0x2000002c
080003dc <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80003dc: e7fe b.n 80003dc <ADC1_IRQHandler>
...
080003e0 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80003e0: b580 push {r7, lr}
80003e2: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80003e4: 4b07 ldr r3, [pc, #28] ; (8000404 <HAL_Init+0x24>)
80003e6: 681a ldr r2, [r3, #0]
80003e8: 4b06 ldr r3, [pc, #24] ; (8000404 <HAL_Init+0x24>)
80003ea: 2110 movs r1, #16
80003ec: 430a orrs r2, r1
80003ee: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80003f0: 2000 movs r0, #0
80003f2: f000 f809 bl 8000408 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80003f6: f7ff ff89 bl 800030c <HAL_MspInit>
/* Return function status */
return HAL_OK;
80003fa: 2300 movs r3, #0
}
80003fc: 0018 movs r0, r3
80003fe: 46bd mov sp, r7
8000400: bd80 pop {r7, pc}
8000402: 46c0 nop ; (mov r8, r8)
8000404: 40022000 .word 0x40022000
08000408 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000408: b590 push {r4, r7, lr}
800040a: b083 sub sp, #12
800040c: af00 add r7, sp, #0
800040e: 6078 str r0, [r7, #4]
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000410: 4b14 ldr r3, [pc, #80] ; (8000464 <HAL_InitTick+0x5c>)
8000412: 681c ldr r4, [r3, #0]
8000414: 4b14 ldr r3, [pc, #80] ; (8000468 <HAL_InitTick+0x60>)
8000416: 781b ldrb r3, [r3, #0]
8000418: 0019 movs r1, r3
800041a: 23fa movs r3, #250 ; 0xfa
800041c: 0098 lsls r0, r3, #2
800041e: f7ff fe73 bl 8000108 <__udivsi3>
8000422: 0003 movs r3, r0
8000424: 0019 movs r1, r3
8000426: 0020 movs r0, r4
8000428: f7ff fe6e bl 8000108 <__udivsi3>
800042c: 0003 movs r3, r0
800042e: 0018 movs r0, r3
8000430: f000 f903 bl 800063a <HAL_SYSTICK_Config>
8000434: 1e03 subs r3, r0, #0
8000436: d001 beq.n 800043c <HAL_InitTick+0x34>
{
return HAL_ERROR;
8000438: 2301 movs r3, #1
800043a: e00f b.n 800045c <HAL_InitTick+0x54>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800043c: 687b ldr r3, [r7, #4]
800043e: 2b03 cmp r3, #3
8000440: d80b bhi.n 800045a <HAL_InitTick+0x52>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000442: 6879 ldr r1, [r7, #4]
8000444: 2301 movs r3, #1
8000446: 425b negs r3, r3
8000448: 2200 movs r2, #0
800044a: 0018 movs r0, r3
800044c: f000 f8e0 bl 8000610 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000450: 4b06 ldr r3, [pc, #24] ; (800046c <HAL_InitTick+0x64>)
8000452: 687a ldr r2, [r7, #4]
8000454: 601a str r2, [r3, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000456: 2300 movs r3, #0
8000458: e000 b.n 800045c <HAL_InitTick+0x54>
return HAL_ERROR;
800045a: 2301 movs r3, #1
}
800045c: 0018 movs r0, r3
800045e: 46bd mov sp, r7
8000460: b003 add sp, #12
8000462: bd90 pop {r4, r7, pc}
8000464: 20000000 .word 0x20000000
8000468: 20000008 .word 0x20000008
800046c: 20000004 .word 0x20000004
08000470 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000470: b580 push {r7, lr}
8000472: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000474: 4b05 ldr r3, [pc, #20] ; (800048c <HAL_IncTick+0x1c>)
8000476: 781b ldrb r3, [r3, #0]
8000478: 001a movs r2, r3
800047a: 4b05 ldr r3, [pc, #20] ; (8000490 <HAL_IncTick+0x20>)
800047c: 681b ldr r3, [r3, #0]
800047e: 18d2 adds r2, r2, r3
8000480: 4b03 ldr r3, [pc, #12] ; (8000490 <HAL_IncTick+0x20>)
8000482: 601a str r2, [r3, #0]
}
8000484: 46c0 nop ; (mov r8, r8)
8000486: 46bd mov sp, r7
8000488: bd80 pop {r7, pc}
800048a: 46c0 nop ; (mov r8, r8)
800048c: 20000008 .word 0x20000008
8000490: 20000028 .word 0x20000028
08000494 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000494: b580 push {r7, lr}
8000496: af00 add r7, sp, #0
return uwTick;
8000498: 4b02 ldr r3, [pc, #8] ; (80004a4 <HAL_GetTick+0x10>)
800049a: 681b ldr r3, [r3, #0]
}
800049c: 0018 movs r0, r3
800049e: 46bd mov sp, r7
80004a0: bd80 pop {r7, pc}
80004a2: 46c0 nop ; (mov r8, r8)
80004a4: 20000028 .word 0x20000028
080004a8 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
80004a8: b580 push {r7, lr}
80004aa: b084 sub sp, #16
80004ac: af00 add r7, sp, #0
80004ae: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
80004b0: f7ff fff0 bl 8000494 <HAL_GetTick>
80004b4: 0003 movs r3, r0
80004b6: 60bb str r3, [r7, #8]
uint32_t wait = Delay;
80004b8: 687b ldr r3, [r7, #4]
80004ba: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
80004bc: 68fb ldr r3, [r7, #12]
80004be: 3301 adds r3, #1
80004c0: d005 beq.n 80004ce <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
80004c2: 4b09 ldr r3, [pc, #36] ; (80004e8 <HAL_Delay+0x40>)
80004c4: 781b ldrb r3, [r3, #0]
80004c6: 001a movs r2, r3
80004c8: 68fb ldr r3, [r7, #12]
80004ca: 189b adds r3, r3, r2
80004cc: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
80004ce: 46c0 nop ; (mov r8, r8)
80004d0: f7ff ffe0 bl 8000494 <HAL_GetTick>
80004d4: 0002 movs r2, r0
80004d6: 68bb ldr r3, [r7, #8]
80004d8: 1ad3 subs r3, r2, r3
80004da: 68fa ldr r2, [r7, #12]
80004dc: 429a cmp r2, r3
80004de: d8f7 bhi.n 80004d0 <HAL_Delay+0x28>
{
}
}
80004e0: 46c0 nop ; (mov r8, r8)
80004e2: 46bd mov sp, r7
80004e4: b004 add sp, #16
80004e6: bd80 pop {r7, pc}
80004e8: 20000008 .word 0x20000008
080004ec <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80004ec: b590 push {r4, r7, lr}
80004ee: b083 sub sp, #12
80004f0: af00 add r7, sp, #0
80004f2: 0002 movs r2, r0
80004f4: 6039 str r1, [r7, #0]
80004f6: 1dfb adds r3, r7, #7
80004f8: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
80004fa: 1dfb adds r3, r7, #7
80004fc: 781b ldrb r3, [r3, #0]
80004fe: 2b7f cmp r3, #127 ; 0x7f
8000500: d828 bhi.n 8000554 <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000502: 4a2f ldr r2, [pc, #188] ; (80005c0 <__NVIC_SetPriority+0xd4>)
8000504: 1dfb adds r3, r7, #7
8000506: 781b ldrb r3, [r3, #0]
8000508: b25b sxtb r3, r3
800050a: 089b lsrs r3, r3, #2
800050c: 33c0 adds r3, #192 ; 0xc0
800050e: 009b lsls r3, r3, #2
8000510: 589b ldr r3, [r3, r2]
8000512: 1dfa adds r2, r7, #7
8000514: 7812 ldrb r2, [r2, #0]
8000516: 0011 movs r1, r2
8000518: 2203 movs r2, #3
800051a: 400a ands r2, r1
800051c: 00d2 lsls r2, r2, #3
800051e: 21ff movs r1, #255 ; 0xff
8000520: 4091 lsls r1, r2
8000522: 000a movs r2, r1
8000524: 43d2 mvns r2, r2
8000526: 401a ands r2, r3
8000528: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
800052a: 683b ldr r3, [r7, #0]
800052c: 019b lsls r3, r3, #6
800052e: 22ff movs r2, #255 ; 0xff
8000530: 401a ands r2, r3
8000532: 1dfb adds r3, r7, #7
8000534: 781b ldrb r3, [r3, #0]
8000536: 0018 movs r0, r3
8000538: 2303 movs r3, #3
800053a: 4003 ands r3, r0
800053c: 00db lsls r3, r3, #3
800053e: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000540: 481f ldr r0, [pc, #124] ; (80005c0 <__NVIC_SetPriority+0xd4>)
8000542: 1dfb adds r3, r7, #7
8000544: 781b ldrb r3, [r3, #0]
8000546: b25b sxtb r3, r3
8000548: 089b lsrs r3, r3, #2
800054a: 430a orrs r2, r1
800054c: 33c0 adds r3, #192 ; 0xc0
800054e: 009b lsls r3, r3, #2
8000550: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
8000552: e031 b.n 80005b8 <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000554: 4a1b ldr r2, [pc, #108] ; (80005c4 <__NVIC_SetPriority+0xd8>)
8000556: 1dfb adds r3, r7, #7
8000558: 781b ldrb r3, [r3, #0]
800055a: 0019 movs r1, r3
800055c: 230f movs r3, #15
800055e: 400b ands r3, r1
8000560: 3b08 subs r3, #8
8000562: 089b lsrs r3, r3, #2
8000564: 3306 adds r3, #6
8000566: 009b lsls r3, r3, #2
8000568: 18d3 adds r3, r2, r3
800056a: 3304 adds r3, #4
800056c: 681b ldr r3, [r3, #0]
800056e: 1dfa adds r2, r7, #7
8000570: 7812 ldrb r2, [r2, #0]
8000572: 0011 movs r1, r2
8000574: 2203 movs r2, #3
8000576: 400a ands r2, r1
8000578: 00d2 lsls r2, r2, #3
800057a: 21ff movs r1, #255 ; 0xff
800057c: 4091 lsls r1, r2
800057e: 000a movs r2, r1
8000580: 43d2 mvns r2, r2
8000582: 401a ands r2, r3
8000584: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8000586: 683b ldr r3, [r7, #0]
8000588: 019b lsls r3, r3, #6
800058a: 22ff movs r2, #255 ; 0xff
800058c: 401a ands r2, r3
800058e: 1dfb adds r3, r7, #7
8000590: 781b ldrb r3, [r3, #0]
8000592: 0018 movs r0, r3
8000594: 2303 movs r3, #3
8000596: 4003 ands r3, r0
8000598: 00db lsls r3, r3, #3
800059a: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
800059c: 4809 ldr r0, [pc, #36] ; (80005c4 <__NVIC_SetPriority+0xd8>)
800059e: 1dfb adds r3, r7, #7
80005a0: 781b ldrb r3, [r3, #0]
80005a2: 001c movs r4, r3
80005a4: 230f movs r3, #15
80005a6: 4023 ands r3, r4
80005a8: 3b08 subs r3, #8
80005aa: 089b lsrs r3, r3, #2
80005ac: 430a orrs r2, r1
80005ae: 3306 adds r3, #6
80005b0: 009b lsls r3, r3, #2
80005b2: 18c3 adds r3, r0, r3
80005b4: 3304 adds r3, #4
80005b6: 601a str r2, [r3, #0]
}
80005b8: 46c0 nop ; (mov r8, r8)
80005ba: 46bd mov sp, r7
80005bc: b003 add sp, #12
80005be: bd90 pop {r4, r7, pc}
80005c0: e000e100 .word 0xe000e100
80005c4: e000ed00 .word 0xe000ed00
080005c8 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80005c8: b580 push {r7, lr}
80005ca: b082 sub sp, #8
80005cc: af00 add r7, sp, #0
80005ce: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80005d0: 687b ldr r3, [r7, #4]
80005d2: 3b01 subs r3, #1
80005d4: 4a0c ldr r2, [pc, #48] ; (8000608 <SysTick_Config+0x40>)
80005d6: 4293 cmp r3, r2
80005d8: d901 bls.n 80005de <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80005da: 2301 movs r3, #1
80005dc: e010 b.n 8000600 <SysTick_Config+0x38>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80005de: 4b0b ldr r3, [pc, #44] ; (800060c <SysTick_Config+0x44>)
80005e0: 687a ldr r2, [r7, #4]
80005e2: 3a01 subs r2, #1
80005e4: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80005e6: 2301 movs r3, #1
80005e8: 425b negs r3, r3
80005ea: 2103 movs r1, #3
80005ec: 0018 movs r0, r3
80005ee: f7ff ff7d bl 80004ec <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80005f2: 4b06 ldr r3, [pc, #24] ; (800060c <SysTick_Config+0x44>)
80005f4: 2200 movs r2, #0
80005f6: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80005f8: 4b04 ldr r3, [pc, #16] ; (800060c <SysTick_Config+0x44>)
80005fa: 2207 movs r2, #7
80005fc: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80005fe: 2300 movs r3, #0
}
8000600: 0018 movs r0, r3
8000602: 46bd mov sp, r7
8000604: b002 add sp, #8
8000606: bd80 pop {r7, pc}
8000608: 00ffffff .word 0x00ffffff
800060c: e000e010 .word 0xe000e010
08000610 <HAL_NVIC_SetPriority>:
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0 based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000610: b580 push {r7, lr}
8000612: b084 sub sp, #16
8000614: af00 add r7, sp, #0
8000616: 60b9 str r1, [r7, #8]
8000618: 607a str r2, [r7, #4]
800061a: 210f movs r1, #15
800061c: 187b adds r3, r7, r1
800061e: 1c02 adds r2, r0, #0
8000620: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn,PreemptPriority);
8000622: 68ba ldr r2, [r7, #8]
8000624: 187b adds r3, r7, r1
8000626: 781b ldrb r3, [r3, #0]
8000628: b25b sxtb r3, r3
800062a: 0011 movs r1, r2
800062c: 0018 movs r0, r3
800062e: f7ff ff5d bl 80004ec <__NVIC_SetPriority>
}
8000632: 46c0 nop ; (mov r8, r8)
8000634: 46bd mov sp, r7
8000636: b004 add sp, #16
8000638: bd80 pop {r7, pc}
0800063a <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800063a: b580 push {r7, lr}
800063c: b082 sub sp, #8
800063e: af00 add r7, sp, #0
8000640: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000642: 687b ldr r3, [r7, #4]
8000644: 0018 movs r0, r3
8000646: f7ff ffbf bl 80005c8 <SysTick_Config>
800064a: 0003 movs r3, r0
}
800064c: 0018 movs r0, r3
800064e: 46bd mov sp, r7
8000650: b002 add sp, #8
8000652: bd80 pop {r7, pc}
08000654 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000654: b580 push {r7, lr}
8000656: b086 sub sp, #24
8000658: af00 add r7, sp, #0
800065a: 6078 str r0, [r7, #4]
800065c: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
800065e: 2300 movs r3, #0
8000660: 617b str r3, [r7, #20]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000662: e14f b.n 8000904 <HAL_GPIO_Init+0x2b0>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8000664: 683b ldr r3, [r7, #0]
8000666: 681b ldr r3, [r3, #0]
8000668: 2101 movs r1, #1
800066a: 697a ldr r2, [r7, #20]
800066c: 4091 lsls r1, r2
800066e: 000a movs r2, r1
8000670: 4013 ands r3, r2
8000672: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8000674: 68fb ldr r3, [r7, #12]
8000676: 2b00 cmp r3, #0
8000678: d100 bne.n 800067c <HAL_GPIO_Init+0x28>
800067a: e140 b.n 80008fe <HAL_GPIO_Init+0x2aa>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
800067c: 683b ldr r3, [r7, #0]
800067e: 685b ldr r3, [r3, #4]
8000680: 2b01 cmp r3, #1
8000682: d00b beq.n 800069c <HAL_GPIO_Init+0x48>
8000684: 683b ldr r3, [r7, #0]
8000686: 685b ldr r3, [r3, #4]
8000688: 2b02 cmp r3, #2
800068a: d007 beq.n 800069c <HAL_GPIO_Init+0x48>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
800068c: 683b ldr r3, [r7, #0]
800068e: 685b ldr r3, [r3, #4]
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
8000690: 2b11 cmp r3, #17
8000692: d003 beq.n 800069c <HAL_GPIO_Init+0x48>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8000694: 683b ldr r3, [r7, #0]
8000696: 685b ldr r3, [r3, #4]
8000698: 2b12 cmp r3, #18
800069a: d130 bne.n 80006fe <HAL_GPIO_Init+0xaa>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
800069c: 687b ldr r3, [r7, #4]
800069e: 689b ldr r3, [r3, #8]
80006a0: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
80006a2: 697b ldr r3, [r7, #20]
80006a4: 005b lsls r3, r3, #1
80006a6: 2203 movs r2, #3
80006a8: 409a lsls r2, r3
80006aa: 0013 movs r3, r2
80006ac: 43da mvns r2, r3
80006ae: 693b ldr r3, [r7, #16]
80006b0: 4013 ands r3, r2
80006b2: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
80006b4: 683b ldr r3, [r7, #0]
80006b6: 68da ldr r2, [r3, #12]
80006b8: 697b ldr r3, [r7, #20]
80006ba: 005b lsls r3, r3, #1
80006bc: 409a lsls r2, r3
80006be: 0013 movs r3, r2
80006c0: 693a ldr r2, [r7, #16]
80006c2: 4313 orrs r3, r2
80006c4: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
80006c6: 687b ldr r3, [r7, #4]
80006c8: 693a ldr r2, [r7, #16]
80006ca: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
80006cc: 687b ldr r3, [r7, #4]
80006ce: 685b ldr r3, [r3, #4]
80006d0: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
80006d2: 2201 movs r2, #1
80006d4: 697b ldr r3, [r7, #20]
80006d6: 409a lsls r2, r3
80006d8: 0013 movs r3, r2
80006da: 43da mvns r2, r3
80006dc: 693b ldr r3, [r7, #16]
80006de: 4013 ands r3, r2
80006e0: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
80006e2: 683b ldr r3, [r7, #0]
80006e4: 685b ldr r3, [r3, #4]
80006e6: 091b lsrs r3, r3, #4
80006e8: 2201 movs r2, #1
80006ea: 401a ands r2, r3
80006ec: 697b ldr r3, [r7, #20]
80006ee: 409a lsls r2, r3
80006f0: 0013 movs r3, r2
80006f2: 693a ldr r2, [r7, #16]
80006f4: 4313 orrs r3, r2
80006f6: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
80006f8: 687b ldr r3, [r7, #4]
80006fa: 693a ldr r2, [r7, #16]
80006fc: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80006fe: 687b ldr r3, [r7, #4]
8000700: 68db ldr r3, [r3, #12]
8000702: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
8000704: 697b ldr r3, [r7, #20]
8000706: 005b lsls r3, r3, #1
8000708: 2203 movs r2, #3
800070a: 409a lsls r2, r3
800070c: 0013 movs r3, r2
800070e: 43da mvns r2, r3
8000710: 693b ldr r3, [r7, #16]
8000712: 4013 ands r3, r2
8000714: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
8000716: 683b ldr r3, [r7, #0]
8000718: 689a ldr r2, [r3, #8]
800071a: 697b ldr r3, [r7, #20]
800071c: 005b lsls r3, r3, #1
800071e: 409a lsls r2, r3
8000720: 0013 movs r3, r2
8000722: 693a ldr r2, [r7, #16]
8000724: 4313 orrs r3, r2
8000726: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8000728: 687b ldr r3, [r7, #4]
800072a: 693a ldr r2, [r7, #16]
800072c: 60da str r2, [r3, #12]
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
800072e: 683b ldr r3, [r7, #0]
8000730: 685b ldr r3, [r3, #4]
8000732: 2b02 cmp r3, #2
8000734: d003 beq.n 800073e <HAL_GPIO_Init+0xea>
8000736: 683b ldr r3, [r7, #0]
8000738: 685b ldr r3, [r3, #4]
800073a: 2b12 cmp r3, #18
800073c: d123 bne.n 8000786 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
800073e: 697b ldr r3, [r7, #20]
8000740: 08da lsrs r2, r3, #3
8000742: 687b ldr r3, [r7, #4]
8000744: 3208 adds r2, #8
8000746: 0092 lsls r2, r2, #2
8000748: 58d3 ldr r3, [r2, r3]
800074a: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
800074c: 697b ldr r3, [r7, #20]
800074e: 2207 movs r2, #7
8000750: 4013 ands r3, r2
8000752: 009b lsls r3, r3, #2
8000754: 220f movs r2, #15
8000756: 409a lsls r2, r3
8000758: 0013 movs r3, r2
800075a: 43da mvns r2, r3
800075c: 693b ldr r3, [r7, #16]
800075e: 4013 ands r3, r2
8000760: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8000762: 683b ldr r3, [r7, #0]
8000764: 691a ldr r2, [r3, #16]
8000766: 697b ldr r3, [r7, #20]
8000768: 2107 movs r1, #7
800076a: 400b ands r3, r1
800076c: 009b lsls r3, r3, #2
800076e: 409a lsls r2, r3
8000770: 0013 movs r3, r2
8000772: 693a ldr r2, [r7, #16]
8000774: 4313 orrs r3, r2
8000776: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8000778: 697b ldr r3, [r7, #20]
800077a: 08da lsrs r2, r3, #3
800077c: 687b ldr r3, [r7, #4]
800077e: 3208 adds r2, #8
8000780: 0092 lsls r2, r2, #2
8000782: 6939 ldr r1, [r7, #16]
8000784: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000786: 687b ldr r3, [r7, #4]
8000788: 681b ldr r3, [r3, #0]
800078a: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
800078c: 697b ldr r3, [r7, #20]
800078e: 005b lsls r3, r3, #1
8000790: 2203 movs r2, #3
8000792: 409a lsls r2, r3
8000794: 0013 movs r3, r2
8000796: 43da mvns r2, r3
8000798: 693b ldr r3, [r7, #16]
800079a: 4013 ands r3, r2
800079c: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
800079e: 683b ldr r3, [r7, #0]
80007a0: 685b ldr r3, [r3, #4]
80007a2: 2203 movs r2, #3
80007a4: 401a ands r2, r3
80007a6: 697b ldr r3, [r7, #20]
80007a8: 005b lsls r3, r3, #1
80007aa: 409a lsls r2, r3
80007ac: 0013 movs r3, r2
80007ae: 693a ldr r2, [r7, #16]
80007b0: 4313 orrs r3, r2
80007b2: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
80007b4: 687b ldr r3, [r7, #4]
80007b6: 693a ldr r2, [r7, #16]
80007b8: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
80007ba: 683b ldr r3, [r7, #0]
80007bc: 685a ldr r2, [r3, #4]
80007be: 2380 movs r3, #128 ; 0x80
80007c0: 055b lsls r3, r3, #21
80007c2: 4013 ands r3, r2
80007c4: d100 bne.n 80007c8 <HAL_GPIO_Init+0x174>
80007c6: e09a b.n 80008fe <HAL_GPIO_Init+0x2aa>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80007c8: 4b54 ldr r3, [pc, #336] ; (800091c <HAL_GPIO_Init+0x2c8>)
80007ca: 699a ldr r2, [r3, #24]
80007cc: 4b53 ldr r3, [pc, #332] ; (800091c <HAL_GPIO_Init+0x2c8>)
80007ce: 2101 movs r1, #1
80007d0: 430a orrs r2, r1
80007d2: 619a str r2, [r3, #24]
80007d4: 4b51 ldr r3, [pc, #324] ; (800091c <HAL_GPIO_Init+0x2c8>)
80007d6: 699b ldr r3, [r3, #24]
80007d8: 2201 movs r2, #1
80007da: 4013 ands r3, r2
80007dc: 60bb str r3, [r7, #8]
80007de: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
80007e0: 4a4f ldr r2, [pc, #316] ; (8000920 <HAL_GPIO_Init+0x2cc>)
80007e2: 697b ldr r3, [r7, #20]
80007e4: 089b lsrs r3, r3, #2
80007e6: 3302 adds r3, #2
80007e8: 009b lsls r3, r3, #2
80007ea: 589b ldr r3, [r3, r2]
80007ec: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
80007ee: 697b ldr r3, [r7, #20]
80007f0: 2203 movs r2, #3
80007f2: 4013 ands r3, r2
80007f4: 009b lsls r3, r3, #2
80007f6: 220f movs r2, #15
80007f8: 409a lsls r2, r3
80007fa: 0013 movs r3, r2
80007fc: 43da mvns r2, r3
80007fe: 693b ldr r3, [r7, #16]
8000800: 4013 ands r3, r2
8000802: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8000804: 687a ldr r2, [r7, #4]
8000806: 2390 movs r3, #144 ; 0x90
8000808: 05db lsls r3, r3, #23
800080a: 429a cmp r2, r3
800080c: d013 beq.n 8000836 <HAL_GPIO_Init+0x1e2>
800080e: 687b ldr r3, [r7, #4]
8000810: 4a44 ldr r2, [pc, #272] ; (8000924 <HAL_GPIO_Init+0x2d0>)
8000812: 4293 cmp r3, r2
8000814: d00d beq.n 8000832 <HAL_GPIO_Init+0x1de>
8000816: 687b ldr r3, [r7, #4]
8000818: 4a43 ldr r2, [pc, #268] ; (8000928 <HAL_GPIO_Init+0x2d4>)
800081a: 4293 cmp r3, r2
800081c: d007 beq.n 800082e <HAL_GPIO_Init+0x1da>
800081e: 687b ldr r3, [r7, #4]
8000820: 4a42 ldr r2, [pc, #264] ; (800092c <HAL_GPIO_Init+0x2d8>)
8000822: 4293 cmp r3, r2
8000824: d101 bne.n 800082a <HAL_GPIO_Init+0x1d6>
8000826: 2303 movs r3, #3
8000828: e006 b.n 8000838 <HAL_GPIO_Init+0x1e4>
800082a: 2305 movs r3, #5
800082c: e004 b.n 8000838 <HAL_GPIO_Init+0x1e4>
800082e: 2302 movs r3, #2
8000830: e002 b.n 8000838 <HAL_GPIO_Init+0x1e4>
8000832: 2301 movs r3, #1
8000834: e000 b.n 8000838 <HAL_GPIO_Init+0x1e4>
8000836: 2300 movs r3, #0
8000838: 697a ldr r2, [r7, #20]
800083a: 2103 movs r1, #3
800083c: 400a ands r2, r1
800083e: 0092 lsls r2, r2, #2
8000840: 4093 lsls r3, r2
8000842: 693a ldr r2, [r7, #16]
8000844: 4313 orrs r3, r2
8000846: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8000848: 4935 ldr r1, [pc, #212] ; (8000920 <HAL_GPIO_Init+0x2cc>)
800084a: 697b ldr r3, [r7, #20]
800084c: 089b lsrs r3, r3, #2
800084e: 3302 adds r3, #2
8000850: 009b lsls r3, r3, #2
8000852: 693a ldr r2, [r7, #16]
8000854: 505a str r2, [r3, r1]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8000856: 4b36 ldr r3, [pc, #216] ; (8000930 <HAL_GPIO_Init+0x2dc>)
8000858: 681b ldr r3, [r3, #0]
800085a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800085c: 68fb ldr r3, [r7, #12]
800085e: 43da mvns r2, r3
8000860: 693b ldr r3, [r7, #16]
8000862: 4013 ands r3, r2
8000864: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8000866: 683b ldr r3, [r7, #0]
8000868: 685a ldr r2, [r3, #4]
800086a: 2380 movs r3, #128 ; 0x80
800086c: 025b lsls r3, r3, #9
800086e: 4013 ands r3, r2
8000870: d003 beq.n 800087a <HAL_GPIO_Init+0x226>
{
temp |= iocurrent;
8000872: 693a ldr r2, [r7, #16]
8000874: 68fb ldr r3, [r7, #12]
8000876: 4313 orrs r3, r2
8000878: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
800087a: 4b2d ldr r3, [pc, #180] ; (8000930 <HAL_GPIO_Init+0x2dc>)
800087c: 693a ldr r2, [r7, #16]
800087e: 601a str r2, [r3, #0]
temp = EXTI->EMR;
8000880: 4b2b ldr r3, [pc, #172] ; (8000930 <HAL_GPIO_Init+0x2dc>)
8000882: 685b ldr r3, [r3, #4]
8000884: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8000886: 68fb ldr r3, [r7, #12]
8000888: 43da mvns r2, r3
800088a: 693b ldr r3, [r7, #16]
800088c: 4013 ands r3, r2
800088e: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8000890: 683b ldr r3, [r7, #0]
8000892: 685a ldr r2, [r3, #4]
8000894: 2380 movs r3, #128 ; 0x80
8000896: 029b lsls r3, r3, #10
8000898: 4013 ands r3, r2
800089a: d003 beq.n 80008a4 <HAL_GPIO_Init+0x250>
{
temp |= iocurrent;
800089c: 693a ldr r2, [r7, #16]
800089e: 68fb ldr r3, [r7, #12]
80008a0: 4313 orrs r3, r2
80008a2: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
80008a4: 4b22 ldr r3, [pc, #136] ; (8000930 <HAL_GPIO_Init+0x2dc>)
80008a6: 693a ldr r2, [r7, #16]
80008a8: 605a str r2, [r3, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
80008aa: 4b21 ldr r3, [pc, #132] ; (8000930 <HAL_GPIO_Init+0x2dc>)
80008ac: 689b ldr r3, [r3, #8]
80008ae: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80008b0: 68fb ldr r3, [r7, #12]
80008b2: 43da mvns r2, r3
80008b4: 693b ldr r3, [r7, #16]
80008b6: 4013 ands r3, r2
80008b8: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
80008ba: 683b ldr r3, [r7, #0]
80008bc: 685a ldr r2, [r3, #4]
80008be: 2380 movs r3, #128 ; 0x80
80008c0: 035b lsls r3, r3, #13
80008c2: 4013 ands r3, r2
80008c4: d003 beq.n 80008ce <HAL_GPIO_Init+0x27a>
{
temp |= iocurrent;
80008c6: 693a ldr r2, [r7, #16]
80008c8: 68fb ldr r3, [r7, #12]
80008ca: 4313 orrs r3, r2
80008cc: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
80008ce: 4b18 ldr r3, [pc, #96] ; (8000930 <HAL_GPIO_Init+0x2dc>)
80008d0: 693a ldr r2, [r7, #16]
80008d2: 609a str r2, [r3, #8]
temp = EXTI->FTSR;
80008d4: 4b16 ldr r3, [pc, #88] ; (8000930 <HAL_GPIO_Init+0x2dc>)
80008d6: 68db ldr r3, [r3, #12]
80008d8: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80008da: 68fb ldr r3, [r7, #12]
80008dc: 43da mvns r2, r3
80008de: 693b ldr r3, [r7, #16]
80008e0: 4013 ands r3, r2
80008e2: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
80008e4: 683b ldr r3, [r7, #0]
80008e6: 685a ldr r2, [r3, #4]
80008e8: 2380 movs r3, #128 ; 0x80
80008ea: 039b lsls r3, r3, #14
80008ec: 4013 ands r3, r2
80008ee: d003 beq.n 80008f8 <HAL_GPIO_Init+0x2a4>
{
temp |= iocurrent;
80008f0: 693a ldr r2, [r7, #16]
80008f2: 68fb ldr r3, [r7, #12]
80008f4: 4313 orrs r3, r2
80008f6: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
80008f8: 4b0d ldr r3, [pc, #52] ; (8000930 <HAL_GPIO_Init+0x2dc>)
80008fa: 693a ldr r2, [r7, #16]
80008fc: 60da str r2, [r3, #12]
}
}
position++;
80008fe: 697b ldr r3, [r7, #20]
8000900: 3301 adds r3, #1
8000902: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000904: 683b ldr r3, [r7, #0]
8000906: 681a ldr r2, [r3, #0]
8000908: 697b ldr r3, [r7, #20]
800090a: 40da lsrs r2, r3
800090c: 1e13 subs r3, r2, #0
800090e: d000 beq.n 8000912 <HAL_GPIO_Init+0x2be>
8000910: e6a8 b.n 8000664 <HAL_GPIO_Init+0x10>
}
}
8000912: 46c0 nop ; (mov r8, r8)
8000914: 46bd mov sp, r7
8000916: b006 add sp, #24
8000918: bd80 pop {r7, pc}
800091a: 46c0 nop ; (mov r8, r8)
800091c: 40021000 .word 0x40021000
8000920: 40010000 .word 0x40010000
8000924: 48000400 .word 0x48000400
8000928: 48000800 .word 0x48000800
800092c: 48000c00 .word 0x48000c00
8000930: 40010400 .word 0x40010400
08000934 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8000934: b580 push {r7, lr}
8000936: b082 sub sp, #8
8000938: af00 add r7, sp, #0
800093a: 6078 str r0, [r7, #4]
800093c: 0008 movs r0, r1
800093e: 0011 movs r1, r2
8000940: 1cbb adds r3, r7, #2
8000942: 1c02 adds r2, r0, #0
8000944: 801a strh r2, [r3, #0]
8000946: 1c7b adds r3, r7, #1
8000948: 1c0a adds r2, r1, #0
800094a: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
800094c: 1c7b adds r3, r7, #1
800094e: 781b ldrb r3, [r3, #0]
8000950: 2b00 cmp r3, #0
8000952: d004 beq.n 800095e <HAL_GPIO_WritePin+0x2a>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8000954: 1cbb adds r3, r7, #2
8000956: 881a ldrh r2, [r3, #0]
8000958: 687b ldr r3, [r7, #4]
800095a: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
800095c: e003 b.n 8000966 <HAL_GPIO_WritePin+0x32>
GPIOx->BRR = (uint32_t)GPIO_Pin;
800095e: 1cbb adds r3, r7, #2
8000960: 881a ldrh r2, [r3, #0]
8000962: 687b ldr r3, [r7, #4]
8000964: 629a str r2, [r3, #40] ; 0x28
}
8000966: 46c0 nop ; (mov r8, r8)
8000968: 46bd mov sp, r7
800096a: b002 add sp, #8
800096c: bd80 pop {r7, pc}
...
08000970 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000970: b580 push {r7, lr}
8000972: b088 sub sp, #32
8000974: af00 add r7, sp, #0
8000976: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
uint32_t pll_config2;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8000978: 687b ldr r3, [r7, #4]
800097a: 2b00 cmp r3, #0
800097c: d101 bne.n 8000982 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800097e: 2301 movs r3, #1
8000980: e303 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000982: 687b ldr r3, [r7, #4]
8000984: 681b ldr r3, [r3, #0]
8000986: 2201 movs r2, #1
8000988: 4013 ands r3, r2
800098a: d100 bne.n 800098e <HAL_RCC_OscConfig+0x1e>
800098c: e08d b.n 8000aaa <HAL_RCC_OscConfig+0x13a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
800098e: 4bc4 ldr r3, [pc, #784] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000990: 685b ldr r3, [r3, #4]
8000992: 220c movs r2, #12
8000994: 4013 ands r3, r2
8000996: 2b04 cmp r3, #4
8000998: d00e beq.n 80009b8 <HAL_RCC_OscConfig+0x48>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
800099a: 4bc1 ldr r3, [pc, #772] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
800099c: 685b ldr r3, [r3, #4]
800099e: 220c movs r2, #12
80009a0: 4013 ands r3, r2
80009a2: 2b08 cmp r3, #8
80009a4: d116 bne.n 80009d4 <HAL_RCC_OscConfig+0x64>
80009a6: 4bbe ldr r3, [pc, #760] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
80009a8: 685a ldr r2, [r3, #4]
80009aa: 2380 movs r3, #128 ; 0x80
80009ac: 025b lsls r3, r3, #9
80009ae: 401a ands r2, r3
80009b0: 2380 movs r3, #128 ; 0x80
80009b2: 025b lsls r3, r3, #9
80009b4: 429a cmp r2, r3
80009b6: d10d bne.n 80009d4 <HAL_RCC_OscConfig+0x64>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80009b8: 4bb9 ldr r3, [pc, #740] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
80009ba: 681a ldr r2, [r3, #0]
80009bc: 2380 movs r3, #128 ; 0x80
80009be: 029b lsls r3, r3, #10
80009c0: 4013 ands r3, r2
80009c2: d100 bne.n 80009c6 <HAL_RCC_OscConfig+0x56>
80009c4: e070 b.n 8000aa8 <HAL_RCC_OscConfig+0x138>
80009c6: 687b ldr r3, [r7, #4]
80009c8: 685b ldr r3, [r3, #4]
80009ca: 2b00 cmp r3, #0
80009cc: d000 beq.n 80009d0 <HAL_RCC_OscConfig+0x60>
80009ce: e06b b.n 8000aa8 <HAL_RCC_OscConfig+0x138>
{
return HAL_ERROR;
80009d0: 2301 movs r3, #1
80009d2: e2da b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80009d4: 687b ldr r3, [r7, #4]
80009d6: 685b ldr r3, [r3, #4]
80009d8: 2b01 cmp r3, #1
80009da: d107 bne.n 80009ec <HAL_RCC_OscConfig+0x7c>
80009dc: 4bb0 ldr r3, [pc, #704] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
80009de: 681a ldr r2, [r3, #0]
80009e0: 4baf ldr r3, [pc, #700] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
80009e2: 2180 movs r1, #128 ; 0x80
80009e4: 0249 lsls r1, r1, #9
80009e6: 430a orrs r2, r1
80009e8: 601a str r2, [r3, #0]
80009ea: e02f b.n 8000a4c <HAL_RCC_OscConfig+0xdc>
80009ec: 687b ldr r3, [r7, #4]
80009ee: 685b ldr r3, [r3, #4]
80009f0: 2b00 cmp r3, #0
80009f2: d10c bne.n 8000a0e <HAL_RCC_OscConfig+0x9e>
80009f4: 4baa ldr r3, [pc, #680] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
80009f6: 681a ldr r2, [r3, #0]
80009f8: 4ba9 ldr r3, [pc, #676] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
80009fa: 49aa ldr r1, [pc, #680] ; (8000ca4 <HAL_RCC_OscConfig+0x334>)
80009fc: 400a ands r2, r1
80009fe: 601a str r2, [r3, #0]
8000a00: 4ba7 ldr r3, [pc, #668] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a02: 681a ldr r2, [r3, #0]
8000a04: 4ba6 ldr r3, [pc, #664] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a06: 49a8 ldr r1, [pc, #672] ; (8000ca8 <HAL_RCC_OscConfig+0x338>)
8000a08: 400a ands r2, r1
8000a0a: 601a str r2, [r3, #0]
8000a0c: e01e b.n 8000a4c <HAL_RCC_OscConfig+0xdc>
8000a0e: 687b ldr r3, [r7, #4]
8000a10: 685b ldr r3, [r3, #4]
8000a12: 2b05 cmp r3, #5
8000a14: d10e bne.n 8000a34 <HAL_RCC_OscConfig+0xc4>
8000a16: 4ba2 ldr r3, [pc, #648] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a18: 681a ldr r2, [r3, #0]
8000a1a: 4ba1 ldr r3, [pc, #644] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a1c: 2180 movs r1, #128 ; 0x80
8000a1e: 02c9 lsls r1, r1, #11
8000a20: 430a orrs r2, r1
8000a22: 601a str r2, [r3, #0]
8000a24: 4b9e ldr r3, [pc, #632] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a26: 681a ldr r2, [r3, #0]
8000a28: 4b9d ldr r3, [pc, #628] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a2a: 2180 movs r1, #128 ; 0x80
8000a2c: 0249 lsls r1, r1, #9
8000a2e: 430a orrs r2, r1
8000a30: 601a str r2, [r3, #0]
8000a32: e00b b.n 8000a4c <HAL_RCC_OscConfig+0xdc>
8000a34: 4b9a ldr r3, [pc, #616] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a36: 681a ldr r2, [r3, #0]
8000a38: 4b99 ldr r3, [pc, #612] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a3a: 499a ldr r1, [pc, #616] ; (8000ca4 <HAL_RCC_OscConfig+0x334>)
8000a3c: 400a ands r2, r1
8000a3e: 601a str r2, [r3, #0]
8000a40: 4b97 ldr r3, [pc, #604] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a42: 681a ldr r2, [r3, #0]
8000a44: 4b96 ldr r3, [pc, #600] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a46: 4998 ldr r1, [pc, #608] ; (8000ca8 <HAL_RCC_OscConfig+0x338>)
8000a48: 400a ands r2, r1
8000a4a: 601a str r2, [r3, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000a4c: 687b ldr r3, [r7, #4]
8000a4e: 685b ldr r3, [r3, #4]
8000a50: 2b00 cmp r3, #0
8000a52: d014 beq.n 8000a7e <HAL_RCC_OscConfig+0x10e>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000a54: f7ff fd1e bl 8000494 <HAL_GetTick>
8000a58: 0003 movs r3, r0
8000a5a: 61bb str r3, [r7, #24]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000a5c: e008 b.n 8000a70 <HAL_RCC_OscConfig+0x100>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000a5e: f7ff fd19 bl 8000494 <HAL_GetTick>
8000a62: 0002 movs r2, r0
8000a64: 69bb ldr r3, [r7, #24]
8000a66: 1ad3 subs r3, r2, r3
8000a68: 2b64 cmp r3, #100 ; 0x64
8000a6a: d901 bls.n 8000a70 <HAL_RCC_OscConfig+0x100>
{
return HAL_TIMEOUT;
8000a6c: 2303 movs r3, #3
8000a6e: e28c b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000a70: 4b8b ldr r3, [pc, #556] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a72: 681a ldr r2, [r3, #0]
8000a74: 2380 movs r3, #128 ; 0x80
8000a76: 029b lsls r3, r3, #10
8000a78: 4013 ands r3, r2
8000a7a: d0f0 beq.n 8000a5e <HAL_RCC_OscConfig+0xee>
8000a7c: e015 b.n 8000aaa <HAL_RCC_OscConfig+0x13a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000a7e: f7ff fd09 bl 8000494 <HAL_GetTick>
8000a82: 0003 movs r3, r0
8000a84: 61bb str r3, [r7, #24]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000a86: e008 b.n 8000a9a <HAL_RCC_OscConfig+0x12a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000a88: f7ff fd04 bl 8000494 <HAL_GetTick>
8000a8c: 0002 movs r2, r0
8000a8e: 69bb ldr r3, [r7, #24]
8000a90: 1ad3 subs r3, r2, r3
8000a92: 2b64 cmp r3, #100 ; 0x64
8000a94: d901 bls.n 8000a9a <HAL_RCC_OscConfig+0x12a>
{
return HAL_TIMEOUT;
8000a96: 2303 movs r3, #3
8000a98: e277 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000a9a: 4b81 ldr r3, [pc, #516] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000a9c: 681a ldr r2, [r3, #0]
8000a9e: 2380 movs r3, #128 ; 0x80
8000aa0: 029b lsls r3, r3, #10
8000aa2: 4013 ands r3, r2
8000aa4: d1f0 bne.n 8000a88 <HAL_RCC_OscConfig+0x118>
8000aa6: e000 b.n 8000aaa <HAL_RCC_OscConfig+0x13a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000aa8: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000aaa: 687b ldr r3, [r7, #4]
8000aac: 681b ldr r3, [r3, #0]
8000aae: 2202 movs r2, #2
8000ab0: 4013 ands r3, r2
8000ab2: d100 bne.n 8000ab6 <HAL_RCC_OscConfig+0x146>
8000ab4: e069 b.n 8000b8a <HAL_RCC_OscConfig+0x21a>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8000ab6: 4b7a ldr r3, [pc, #488] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000ab8: 685b ldr r3, [r3, #4]
8000aba: 220c movs r2, #12
8000abc: 4013 ands r3, r2
8000abe: d00b beq.n 8000ad8 <HAL_RCC_OscConfig+0x168>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8000ac0: 4b77 ldr r3, [pc, #476] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000ac2: 685b ldr r3, [r3, #4]
8000ac4: 220c movs r2, #12
8000ac6: 4013 ands r3, r2
8000ac8: 2b08 cmp r3, #8
8000aca: d11c bne.n 8000b06 <HAL_RCC_OscConfig+0x196>
8000acc: 4b74 ldr r3, [pc, #464] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000ace: 685a ldr r2, [r3, #4]
8000ad0: 2380 movs r3, #128 ; 0x80
8000ad2: 025b lsls r3, r3, #9
8000ad4: 4013 ands r3, r2
8000ad6: d116 bne.n 8000b06 <HAL_RCC_OscConfig+0x196>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000ad8: 4b71 ldr r3, [pc, #452] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000ada: 681b ldr r3, [r3, #0]
8000adc: 2202 movs r2, #2
8000ade: 4013 ands r3, r2
8000ae0: d005 beq.n 8000aee <HAL_RCC_OscConfig+0x17e>
8000ae2: 687b ldr r3, [r7, #4]
8000ae4: 68db ldr r3, [r3, #12]
8000ae6: 2b01 cmp r3, #1
8000ae8: d001 beq.n 8000aee <HAL_RCC_OscConfig+0x17e>
{
return HAL_ERROR;
8000aea: 2301 movs r3, #1
8000aec: e24d b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000aee: 4b6c ldr r3, [pc, #432] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000af0: 681b ldr r3, [r3, #0]
8000af2: 22f8 movs r2, #248 ; 0xf8
8000af4: 4393 bics r3, r2
8000af6: 0019 movs r1, r3
8000af8: 687b ldr r3, [r7, #4]
8000afa: 691b ldr r3, [r3, #16]
8000afc: 00da lsls r2, r3, #3
8000afe: 4b68 ldr r3, [pc, #416] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000b00: 430a orrs r2, r1
8000b02: 601a str r2, [r3, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000b04: e041 b.n 8000b8a <HAL_RCC_OscConfig+0x21a>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000b06: 687b ldr r3, [r7, #4]
8000b08: 68db ldr r3, [r3, #12]
8000b0a: 2b00 cmp r3, #0
8000b0c: d024 beq.n 8000b58 <HAL_RCC_OscConfig+0x1e8>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8000b0e: 4b64 ldr r3, [pc, #400] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000b10: 681a ldr r2, [r3, #0]
8000b12: 4b63 ldr r3, [pc, #396] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000b14: 2101 movs r1, #1
8000b16: 430a orrs r2, r1
8000b18: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000b1a: f7ff fcbb bl 8000494 <HAL_GetTick>
8000b1e: 0003 movs r3, r0
8000b20: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000b22: e008 b.n 8000b36 <HAL_RCC_OscConfig+0x1c6>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8000b24: f7ff fcb6 bl 8000494 <HAL_GetTick>
8000b28: 0002 movs r2, r0
8000b2a: 69bb ldr r3, [r7, #24]
8000b2c: 1ad3 subs r3, r2, r3
8000b2e: 2b02 cmp r3, #2
8000b30: d901 bls.n 8000b36 <HAL_RCC_OscConfig+0x1c6>
{
return HAL_TIMEOUT;
8000b32: 2303 movs r3, #3
8000b34: e229 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000b36: 4b5a ldr r3, [pc, #360] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000b38: 681b ldr r3, [r3, #0]
8000b3a: 2202 movs r2, #2
8000b3c: 4013 ands r3, r2
8000b3e: d0f1 beq.n 8000b24 <HAL_RCC_OscConfig+0x1b4>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000b40: 4b57 ldr r3, [pc, #348] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000b42: 681b ldr r3, [r3, #0]
8000b44: 22f8 movs r2, #248 ; 0xf8
8000b46: 4393 bics r3, r2
8000b48: 0019 movs r1, r3
8000b4a: 687b ldr r3, [r7, #4]
8000b4c: 691b ldr r3, [r3, #16]
8000b4e: 00da lsls r2, r3, #3
8000b50: 4b53 ldr r3, [pc, #332] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000b52: 430a orrs r2, r1
8000b54: 601a str r2, [r3, #0]
8000b56: e018 b.n 8000b8a <HAL_RCC_OscConfig+0x21a>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8000b58: 4b51 ldr r3, [pc, #324] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000b5a: 681a ldr r2, [r3, #0]
8000b5c: 4b50 ldr r3, [pc, #320] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000b5e: 2101 movs r1, #1
8000b60: 438a bics r2, r1
8000b62: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000b64: f7ff fc96 bl 8000494 <HAL_GetTick>
8000b68: 0003 movs r3, r0
8000b6a: 61bb str r3, [r7, #24]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000b6c: e008 b.n 8000b80 <HAL_RCC_OscConfig+0x210>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8000b6e: f7ff fc91 bl 8000494 <HAL_GetTick>
8000b72: 0002 movs r2, r0
8000b74: 69bb ldr r3, [r7, #24]
8000b76: 1ad3 subs r3, r2, r3
8000b78: 2b02 cmp r3, #2
8000b7a: d901 bls.n 8000b80 <HAL_RCC_OscConfig+0x210>
{
return HAL_TIMEOUT;
8000b7c: 2303 movs r3, #3
8000b7e: e204 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000b80: 4b47 ldr r3, [pc, #284] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000b82: 681b ldr r3, [r3, #0]
8000b84: 2202 movs r2, #2
8000b86: 4013 ands r3, r2
8000b88: d1f1 bne.n 8000b6e <HAL_RCC_OscConfig+0x1fe>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8000b8a: 687b ldr r3, [r7, #4]
8000b8c: 681b ldr r3, [r3, #0]
8000b8e: 2208 movs r2, #8
8000b90: 4013 ands r3, r2
8000b92: d036 beq.n 8000c02 <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8000b94: 687b ldr r3, [r7, #4]
8000b96: 69db ldr r3, [r3, #28]
8000b98: 2b00 cmp r3, #0
8000b9a: d019 beq.n 8000bd0 <HAL_RCC_OscConfig+0x260>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8000b9c: 4b40 ldr r3, [pc, #256] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000b9e: 6a5a ldr r2, [r3, #36] ; 0x24
8000ba0: 4b3f ldr r3, [pc, #252] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000ba2: 2101 movs r1, #1
8000ba4: 430a orrs r2, r1
8000ba6: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8000ba8: f7ff fc74 bl 8000494 <HAL_GetTick>
8000bac: 0003 movs r3, r0
8000bae: 61bb str r3, [r7, #24]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000bb0: e008 b.n 8000bc4 <HAL_RCC_OscConfig+0x254>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8000bb2: f7ff fc6f bl 8000494 <HAL_GetTick>
8000bb6: 0002 movs r2, r0
8000bb8: 69bb ldr r3, [r7, #24]
8000bba: 1ad3 subs r3, r2, r3
8000bbc: 2b02 cmp r3, #2
8000bbe: d901 bls.n 8000bc4 <HAL_RCC_OscConfig+0x254>
{
return HAL_TIMEOUT;
8000bc0: 2303 movs r3, #3
8000bc2: e1e2 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000bc4: 4b36 ldr r3, [pc, #216] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000bc6: 6a5b ldr r3, [r3, #36] ; 0x24
8000bc8: 2202 movs r2, #2
8000bca: 4013 ands r3, r2
8000bcc: d0f1 beq.n 8000bb2 <HAL_RCC_OscConfig+0x242>
8000bce: e018 b.n 8000c02 <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8000bd0: 4b33 ldr r3, [pc, #204] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000bd2: 6a5a ldr r2, [r3, #36] ; 0x24
8000bd4: 4b32 ldr r3, [pc, #200] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000bd6: 2101 movs r1, #1
8000bd8: 438a bics r2, r1
8000bda: 625a str r2, [r3, #36] ; 0x24
/* Get Start Tick */
tickstart = HAL_GetTick();
8000bdc: f7ff fc5a bl 8000494 <HAL_GetTick>
8000be0: 0003 movs r3, r0
8000be2: 61bb str r3, [r7, #24]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000be4: e008 b.n 8000bf8 <HAL_RCC_OscConfig+0x288>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8000be6: f7ff fc55 bl 8000494 <HAL_GetTick>
8000bea: 0002 movs r2, r0
8000bec: 69bb ldr r3, [r7, #24]
8000bee: 1ad3 subs r3, r2, r3
8000bf0: 2b02 cmp r3, #2
8000bf2: d901 bls.n 8000bf8 <HAL_RCC_OscConfig+0x288>
{
return HAL_TIMEOUT;
8000bf4: 2303 movs r3, #3
8000bf6: e1c8 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000bf8: 4b29 ldr r3, [pc, #164] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000bfa: 6a5b ldr r3, [r3, #36] ; 0x24
8000bfc: 2202 movs r2, #2
8000bfe: 4013 ands r3, r2
8000c00: d1f1 bne.n 8000be6 <HAL_RCC_OscConfig+0x276>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8000c02: 687b ldr r3, [r7, #4]
8000c04: 681b ldr r3, [r3, #0]
8000c06: 2204 movs r2, #4
8000c08: 4013 ands r3, r2
8000c0a: d100 bne.n 8000c0e <HAL_RCC_OscConfig+0x29e>
8000c0c: e0b6 b.n 8000d7c <HAL_RCC_OscConfig+0x40c>
{
FlagStatus pwrclkchanged = RESET;
8000c0e: 231f movs r3, #31
8000c10: 18fb adds r3, r7, r3
8000c12: 2200 movs r2, #0
8000c14: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8000c16: 4b22 ldr r3, [pc, #136] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000c18: 69da ldr r2, [r3, #28]
8000c1a: 2380 movs r3, #128 ; 0x80
8000c1c: 055b lsls r3, r3, #21
8000c1e: 4013 ands r3, r2
8000c20: d111 bne.n 8000c46 <HAL_RCC_OscConfig+0x2d6>
{
__HAL_RCC_PWR_CLK_ENABLE();
8000c22: 4b1f ldr r3, [pc, #124] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000c24: 69da ldr r2, [r3, #28]
8000c26: 4b1e ldr r3, [pc, #120] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000c28: 2180 movs r1, #128 ; 0x80
8000c2a: 0549 lsls r1, r1, #21
8000c2c: 430a orrs r2, r1
8000c2e: 61da str r2, [r3, #28]
8000c30: 4b1b ldr r3, [pc, #108] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000c32: 69da ldr r2, [r3, #28]
8000c34: 2380 movs r3, #128 ; 0x80
8000c36: 055b lsls r3, r3, #21
8000c38: 4013 ands r3, r2
8000c3a: 60fb str r3, [r7, #12]
8000c3c: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8000c3e: 231f movs r3, #31
8000c40: 18fb adds r3, r7, r3
8000c42: 2201 movs r2, #1
8000c44: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000c46: 4b19 ldr r3, [pc, #100] ; (8000cac <HAL_RCC_OscConfig+0x33c>)
8000c48: 681a ldr r2, [r3, #0]
8000c4a: 2380 movs r3, #128 ; 0x80
8000c4c: 005b lsls r3, r3, #1
8000c4e: 4013 ands r3, r2
8000c50: d11a bne.n 8000c88 <HAL_RCC_OscConfig+0x318>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8000c52: 4b16 ldr r3, [pc, #88] ; (8000cac <HAL_RCC_OscConfig+0x33c>)
8000c54: 681a ldr r2, [r3, #0]
8000c56: 4b15 ldr r3, [pc, #84] ; (8000cac <HAL_RCC_OscConfig+0x33c>)
8000c58: 2180 movs r1, #128 ; 0x80
8000c5a: 0049 lsls r1, r1, #1
8000c5c: 430a orrs r2, r1
8000c5e: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8000c60: f7ff fc18 bl 8000494 <HAL_GetTick>
8000c64: 0003 movs r3, r0
8000c66: 61bb str r3, [r7, #24]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000c68: e008 b.n 8000c7c <HAL_RCC_OscConfig+0x30c>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8000c6a: f7ff fc13 bl 8000494 <HAL_GetTick>
8000c6e: 0002 movs r2, r0
8000c70: 69bb ldr r3, [r7, #24]
8000c72: 1ad3 subs r3, r2, r3
8000c74: 2b64 cmp r3, #100 ; 0x64
8000c76: d901 bls.n 8000c7c <HAL_RCC_OscConfig+0x30c>
{
return HAL_TIMEOUT;
8000c78: 2303 movs r3, #3
8000c7a: e186 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000c7c: 4b0b ldr r3, [pc, #44] ; (8000cac <HAL_RCC_OscConfig+0x33c>)
8000c7e: 681a ldr r2, [r3, #0]
8000c80: 2380 movs r3, #128 ; 0x80
8000c82: 005b lsls r3, r3, #1
8000c84: 4013 ands r3, r2
8000c86: d0f0 beq.n 8000c6a <HAL_RCC_OscConfig+0x2fa>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8000c88: 687b ldr r3, [r7, #4]
8000c8a: 689b ldr r3, [r3, #8]
8000c8c: 2b01 cmp r3, #1
8000c8e: d10f bne.n 8000cb0 <HAL_RCC_OscConfig+0x340>
8000c90: 4b03 ldr r3, [pc, #12] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000c92: 6a1a ldr r2, [r3, #32]
8000c94: 4b02 ldr r3, [pc, #8] ; (8000ca0 <HAL_RCC_OscConfig+0x330>)
8000c96: 2101 movs r1, #1
8000c98: 430a orrs r2, r1
8000c9a: 621a str r2, [r3, #32]
8000c9c: e036 b.n 8000d0c <HAL_RCC_OscConfig+0x39c>
8000c9e: 46c0 nop ; (mov r8, r8)
8000ca0: 40021000 .word 0x40021000
8000ca4: fffeffff .word 0xfffeffff
8000ca8: fffbffff .word 0xfffbffff
8000cac: 40007000 .word 0x40007000
8000cb0: 687b ldr r3, [r7, #4]
8000cb2: 689b ldr r3, [r3, #8]
8000cb4: 2b00 cmp r3, #0
8000cb6: d10c bne.n 8000cd2 <HAL_RCC_OscConfig+0x362>
8000cb8: 4bb6 ldr r3, [pc, #728] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000cba: 6a1a ldr r2, [r3, #32]
8000cbc: 4bb5 ldr r3, [pc, #724] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000cbe: 2101 movs r1, #1
8000cc0: 438a bics r2, r1
8000cc2: 621a str r2, [r3, #32]
8000cc4: 4bb3 ldr r3, [pc, #716] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000cc6: 6a1a ldr r2, [r3, #32]
8000cc8: 4bb2 ldr r3, [pc, #712] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000cca: 2104 movs r1, #4
8000ccc: 438a bics r2, r1
8000cce: 621a str r2, [r3, #32]
8000cd0: e01c b.n 8000d0c <HAL_RCC_OscConfig+0x39c>
8000cd2: 687b ldr r3, [r7, #4]
8000cd4: 689b ldr r3, [r3, #8]
8000cd6: 2b05 cmp r3, #5
8000cd8: d10c bne.n 8000cf4 <HAL_RCC_OscConfig+0x384>
8000cda: 4bae ldr r3, [pc, #696] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000cdc: 6a1a ldr r2, [r3, #32]
8000cde: 4bad ldr r3, [pc, #692] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000ce0: 2104 movs r1, #4
8000ce2: 430a orrs r2, r1
8000ce4: 621a str r2, [r3, #32]
8000ce6: 4bab ldr r3, [pc, #684] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000ce8: 6a1a ldr r2, [r3, #32]
8000cea: 4baa ldr r3, [pc, #680] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000cec: 2101 movs r1, #1
8000cee: 430a orrs r2, r1
8000cf0: 621a str r2, [r3, #32]
8000cf2: e00b b.n 8000d0c <HAL_RCC_OscConfig+0x39c>
8000cf4: 4ba7 ldr r3, [pc, #668] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000cf6: 6a1a ldr r2, [r3, #32]
8000cf8: 4ba6 ldr r3, [pc, #664] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000cfa: 2101 movs r1, #1
8000cfc: 438a bics r2, r1
8000cfe: 621a str r2, [r3, #32]
8000d00: 4ba4 ldr r3, [pc, #656] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000d02: 6a1a ldr r2, [r3, #32]
8000d04: 4ba3 ldr r3, [pc, #652] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000d06: 2104 movs r1, #4
8000d08: 438a bics r2, r1
8000d0a: 621a str r2, [r3, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8000d0c: 687b ldr r3, [r7, #4]
8000d0e: 689b ldr r3, [r3, #8]
8000d10: 2b00 cmp r3, #0
8000d12: d014 beq.n 8000d3e <HAL_RCC_OscConfig+0x3ce>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d14: f7ff fbbe bl 8000494 <HAL_GetTick>
8000d18: 0003 movs r3, r0
8000d1a: 61bb str r3, [r7, #24]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000d1c: e009 b.n 8000d32 <HAL_RCC_OscConfig+0x3c2>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8000d1e: f7ff fbb9 bl 8000494 <HAL_GetTick>
8000d22: 0002 movs r2, r0
8000d24: 69bb ldr r3, [r7, #24]
8000d26: 1ad3 subs r3, r2, r3
8000d28: 4a9b ldr r2, [pc, #620] ; (8000f98 <HAL_RCC_OscConfig+0x628>)
8000d2a: 4293 cmp r3, r2
8000d2c: d901 bls.n 8000d32 <HAL_RCC_OscConfig+0x3c2>
{
return HAL_TIMEOUT;
8000d2e: 2303 movs r3, #3
8000d30: e12b b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000d32: 4b98 ldr r3, [pc, #608] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000d34: 6a1b ldr r3, [r3, #32]
8000d36: 2202 movs r2, #2
8000d38: 4013 ands r3, r2
8000d3a: d0f0 beq.n 8000d1e <HAL_RCC_OscConfig+0x3ae>
8000d3c: e013 b.n 8000d66 <HAL_RCC_OscConfig+0x3f6>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d3e: f7ff fba9 bl 8000494 <HAL_GetTick>
8000d42: 0003 movs r3, r0
8000d44: 61bb str r3, [r7, #24]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000d46: e009 b.n 8000d5c <HAL_RCC_OscConfig+0x3ec>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8000d48: f7ff fba4 bl 8000494 <HAL_GetTick>
8000d4c: 0002 movs r2, r0
8000d4e: 69bb ldr r3, [r7, #24]
8000d50: 1ad3 subs r3, r2, r3
8000d52: 4a91 ldr r2, [pc, #580] ; (8000f98 <HAL_RCC_OscConfig+0x628>)
8000d54: 4293 cmp r3, r2
8000d56: d901 bls.n 8000d5c <HAL_RCC_OscConfig+0x3ec>
{
return HAL_TIMEOUT;
8000d58: 2303 movs r3, #3
8000d5a: e116 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000d5c: 4b8d ldr r3, [pc, #564] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000d5e: 6a1b ldr r3, [r3, #32]
8000d60: 2202 movs r2, #2
8000d62: 4013 ands r3, r2
8000d64: d1f0 bne.n 8000d48 <HAL_RCC_OscConfig+0x3d8>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8000d66: 231f movs r3, #31
8000d68: 18fb adds r3, r7, r3
8000d6a: 781b ldrb r3, [r3, #0]
8000d6c: 2b01 cmp r3, #1
8000d6e: d105 bne.n 8000d7c <HAL_RCC_OscConfig+0x40c>
{
__HAL_RCC_PWR_CLK_DISABLE();
8000d70: 4b88 ldr r3, [pc, #544] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000d72: 69da ldr r2, [r3, #28]
8000d74: 4b87 ldr r3, [pc, #540] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000d76: 4989 ldr r1, [pc, #548] ; (8000f9c <HAL_RCC_OscConfig+0x62c>)
8000d78: 400a ands r2, r1
8000d7a: 61da str r2, [r3, #28]
}
}
/*----------------------------- HSI14 Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
8000d7c: 687b ldr r3, [r7, #4]
8000d7e: 681b ldr r3, [r3, #0]
8000d80: 2210 movs r2, #16
8000d82: 4013 ands r3, r2
8000d84: d063 beq.n 8000e4e <HAL_RCC_OscConfig+0x4de>
/* Check the parameters */
assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
/* Check the HSI14 State */
if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
8000d86: 687b ldr r3, [r7, #4]
8000d88: 695b ldr r3, [r3, #20]
8000d8a: 2b01 cmp r3, #1
8000d8c: d12a bne.n 8000de4 <HAL_RCC_OscConfig+0x474>
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8000d8e: 4b81 ldr r3, [pc, #516] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000d90: 6b5a ldr r2, [r3, #52] ; 0x34
8000d92: 4b80 ldr r3, [pc, #512] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000d94: 2104 movs r1, #4
8000d96: 430a orrs r2, r1
8000d98: 635a str r2, [r3, #52] ; 0x34
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_ENABLE();
8000d9a: 4b7e ldr r3, [pc, #504] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000d9c: 6b5a ldr r2, [r3, #52] ; 0x34
8000d9e: 4b7d ldr r3, [pc, #500] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000da0: 2101 movs r1, #1
8000da2: 430a orrs r2, r1
8000da4: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8000da6: f7ff fb75 bl 8000494 <HAL_GetTick>
8000daa: 0003 movs r3, r0
8000dac: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8000dae: e008 b.n 8000dc2 <HAL_RCC_OscConfig+0x452>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8000db0: f7ff fb70 bl 8000494 <HAL_GetTick>
8000db4: 0002 movs r2, r0
8000db6: 69bb ldr r3, [r7, #24]
8000db8: 1ad3 subs r3, r2, r3
8000dba: 2b02 cmp r3, #2
8000dbc: d901 bls.n 8000dc2 <HAL_RCC_OscConfig+0x452>
{
return HAL_TIMEOUT;
8000dbe: 2303 movs r3, #3
8000dc0: e0e3 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
8000dc2: 4b74 ldr r3, [pc, #464] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000dc4: 6b5b ldr r3, [r3, #52] ; 0x34
8000dc6: 2202 movs r2, #2
8000dc8: 4013 ands r3, r2
8000dca: d0f1 beq.n 8000db0 <HAL_RCC_OscConfig+0x440>
}
}
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8000dcc: 4b71 ldr r3, [pc, #452] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000dce: 6b5b ldr r3, [r3, #52] ; 0x34
8000dd0: 22f8 movs r2, #248 ; 0xf8
8000dd2: 4393 bics r3, r2
8000dd4: 0019 movs r1, r3
8000dd6: 687b ldr r3, [r7, #4]
8000dd8: 699b ldr r3, [r3, #24]
8000dda: 00da lsls r2, r3, #3
8000ddc: 4b6d ldr r3, [pc, #436] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000dde: 430a orrs r2, r1
8000de0: 635a str r2, [r3, #52] ; 0x34
8000de2: e034 b.n 8000e4e <HAL_RCC_OscConfig+0x4de>
}
else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
8000de4: 687b ldr r3, [r7, #4]
8000de6: 695b ldr r3, [r3, #20]
8000de8: 3305 adds r3, #5
8000dea: d111 bne.n 8000e10 <HAL_RCC_OscConfig+0x4a0>
{
/* Enable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_ENABLE();
8000dec: 4b69 ldr r3, [pc, #420] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000dee: 6b5a ldr r2, [r3, #52] ; 0x34
8000df0: 4b68 ldr r3, [pc, #416] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000df2: 2104 movs r1, #4
8000df4: 438a bics r2, r1
8000df6: 635a str r2, [r3, #52] ; 0x34
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
8000df8: 4b66 ldr r3, [pc, #408] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000dfa: 6b5b ldr r3, [r3, #52] ; 0x34
8000dfc: 22f8 movs r2, #248 ; 0xf8
8000dfe: 4393 bics r3, r2
8000e00: 0019 movs r1, r3
8000e02: 687b ldr r3, [r7, #4]
8000e04: 699b ldr r3, [r3, #24]
8000e06: 00da lsls r2, r3, #3
8000e08: 4b62 ldr r3, [pc, #392] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000e0a: 430a orrs r2, r1
8000e0c: 635a str r2, [r3, #52] ; 0x34
8000e0e: e01e b.n 8000e4e <HAL_RCC_OscConfig+0x4de>
}
else
{
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
__HAL_RCC_HSI14ADC_DISABLE();
8000e10: 4b60 ldr r3, [pc, #384] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000e12: 6b5a ldr r2, [r3, #52] ; 0x34
8000e14: 4b5f ldr r3, [pc, #380] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000e16: 2104 movs r1, #4
8000e18: 430a orrs r2, r1
8000e1a: 635a str r2, [r3, #52] ; 0x34
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI14_DISABLE();
8000e1c: 4b5d ldr r3, [pc, #372] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000e1e: 6b5a ldr r2, [r3, #52] ; 0x34
8000e20: 4b5c ldr r3, [pc, #368] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000e22: 2101 movs r1, #1
8000e24: 438a bics r2, r1
8000e26: 635a str r2, [r3, #52] ; 0x34
/* Get Start Tick */
tickstart = HAL_GetTick();
8000e28: f7ff fb34 bl 8000494 <HAL_GetTick>
8000e2c: 0003 movs r3, r0
8000e2e: 61bb str r3, [r7, #24]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8000e30: e008 b.n 8000e44 <HAL_RCC_OscConfig+0x4d4>
{
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
8000e32: f7ff fb2f bl 8000494 <HAL_GetTick>
8000e36: 0002 movs r2, r0
8000e38: 69bb ldr r3, [r7, #24]
8000e3a: 1ad3 subs r3, r2, r3
8000e3c: 2b02 cmp r3, #2
8000e3e: d901 bls.n 8000e44 <HAL_RCC_OscConfig+0x4d4>
{
return HAL_TIMEOUT;
8000e40: 2303 movs r3, #3
8000e42: e0a2 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
8000e44: 4b53 ldr r3, [pc, #332] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000e46: 6b5b ldr r3, [r3, #52] ; 0x34
8000e48: 2202 movs r2, #2
8000e4a: 4013 ands r3, r2
8000e4c: d1f1 bne.n 8000e32 <HAL_RCC_OscConfig+0x4c2>
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8000e4e: 687b ldr r3, [r7, #4]
8000e50: 6a1b ldr r3, [r3, #32]
8000e52: 2b00 cmp r3, #0
8000e54: d100 bne.n 8000e58 <HAL_RCC_OscConfig+0x4e8>
8000e56: e097 b.n 8000f88 <HAL_RCC_OscConfig+0x618>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8000e58: 4b4e ldr r3, [pc, #312] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000e5a: 685b ldr r3, [r3, #4]
8000e5c: 220c movs r2, #12
8000e5e: 4013 ands r3, r2
8000e60: 2b08 cmp r3, #8
8000e62: d100 bne.n 8000e66 <HAL_RCC_OscConfig+0x4f6>
8000e64: e06b b.n 8000f3e <HAL_RCC_OscConfig+0x5ce>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8000e66: 687b ldr r3, [r7, #4]
8000e68: 6a1b ldr r3, [r3, #32]
8000e6a: 2b02 cmp r3, #2
8000e6c: d14c bne.n 8000f08 <HAL_RCC_OscConfig+0x598>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000e6e: 4b49 ldr r3, [pc, #292] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000e70: 681a ldr r2, [r3, #0]
8000e72: 4b48 ldr r3, [pc, #288] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000e74: 494a ldr r1, [pc, #296] ; (8000fa0 <HAL_RCC_OscConfig+0x630>)
8000e76: 400a ands r2, r1
8000e78: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000e7a: f7ff fb0b bl 8000494 <HAL_GetTick>
8000e7e: 0003 movs r3, r0
8000e80: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000e82: e008 b.n 8000e96 <HAL_RCC_OscConfig+0x526>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8000e84: f7ff fb06 bl 8000494 <HAL_GetTick>
8000e88: 0002 movs r2, r0
8000e8a: 69bb ldr r3, [r7, #24]
8000e8c: 1ad3 subs r3, r2, r3
8000e8e: 2b02 cmp r3, #2
8000e90: d901 bls.n 8000e96 <HAL_RCC_OscConfig+0x526>
{
return HAL_TIMEOUT;
8000e92: 2303 movs r3, #3
8000e94: e079 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000e96: 4b3f ldr r3, [pc, #252] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000e98: 681a ldr r2, [r3, #0]
8000e9a: 2380 movs r3, #128 ; 0x80
8000e9c: 049b lsls r3, r3, #18
8000e9e: 4013 ands r3, r2
8000ea0: d1f0 bne.n 8000e84 <HAL_RCC_OscConfig+0x514>
}
}
/* Configure the main PLL clock source, predivider and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8000ea2: 4b3c ldr r3, [pc, #240] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000ea4: 6adb ldr r3, [r3, #44] ; 0x2c
8000ea6: 220f movs r2, #15
8000ea8: 4393 bics r3, r2
8000eaa: 0019 movs r1, r3
8000eac: 687b ldr r3, [r7, #4]
8000eae: 6ada ldr r2, [r3, #44] ; 0x2c
8000eb0: 4b38 ldr r3, [pc, #224] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000eb2: 430a orrs r2, r1
8000eb4: 62da str r2, [r3, #44] ; 0x2c
8000eb6: 4b37 ldr r3, [pc, #220] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000eb8: 685b ldr r3, [r3, #4]
8000eba: 4a3a ldr r2, [pc, #232] ; (8000fa4 <HAL_RCC_OscConfig+0x634>)
8000ebc: 4013 ands r3, r2
8000ebe: 0019 movs r1, r3
8000ec0: 687b ldr r3, [r7, #4]
8000ec2: 6a9a ldr r2, [r3, #40] ; 0x28
8000ec4: 687b ldr r3, [r7, #4]
8000ec6: 6a5b ldr r3, [r3, #36] ; 0x24
8000ec8: 431a orrs r2, r3
8000eca: 4b32 ldr r3, [pc, #200] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000ecc: 430a orrs r2, r1
8000ece: 605a str r2, [r3, #4]
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8000ed0: 4b30 ldr r3, [pc, #192] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000ed2: 681a ldr r2, [r3, #0]
8000ed4: 4b2f ldr r3, [pc, #188] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000ed6: 2180 movs r1, #128 ; 0x80
8000ed8: 0449 lsls r1, r1, #17
8000eda: 430a orrs r2, r1
8000edc: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000ede: f7ff fad9 bl 8000494 <HAL_GetTick>
8000ee2: 0003 movs r3, r0
8000ee4: 61bb str r3, [r7, #24]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000ee6: e008 b.n 8000efa <HAL_RCC_OscConfig+0x58a>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8000ee8: f7ff fad4 bl 8000494 <HAL_GetTick>
8000eec: 0002 movs r2, r0
8000eee: 69bb ldr r3, [r7, #24]
8000ef0: 1ad3 subs r3, r2, r3
8000ef2: 2b02 cmp r3, #2
8000ef4: d901 bls.n 8000efa <HAL_RCC_OscConfig+0x58a>
{
return HAL_TIMEOUT;
8000ef6: 2303 movs r3, #3
8000ef8: e047 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000efa: 4b26 ldr r3, [pc, #152] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000efc: 681a ldr r2, [r3, #0]
8000efe: 2380 movs r3, #128 ; 0x80
8000f00: 049b lsls r3, r3, #18
8000f02: 4013 ands r3, r2
8000f04: d0f0 beq.n 8000ee8 <HAL_RCC_OscConfig+0x578>
8000f06: e03f b.n 8000f88 <HAL_RCC_OscConfig+0x618>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000f08: 4b22 ldr r3, [pc, #136] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000f0a: 681a ldr r2, [r3, #0]
8000f0c: 4b21 ldr r3, [pc, #132] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000f0e: 4924 ldr r1, [pc, #144] ; (8000fa0 <HAL_RCC_OscConfig+0x630>)
8000f10: 400a ands r2, r1
8000f12: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f14: f7ff fabe bl 8000494 <HAL_GetTick>
8000f18: 0003 movs r3, r0
8000f1a: 61bb str r3, [r7, #24]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000f1c: e008 b.n 8000f30 <HAL_RCC_OscConfig+0x5c0>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8000f1e: f7ff fab9 bl 8000494 <HAL_GetTick>
8000f22: 0002 movs r2, r0
8000f24: 69bb ldr r3, [r7, #24]
8000f26: 1ad3 subs r3, r2, r3
8000f28: 2b02 cmp r3, #2
8000f2a: d901 bls.n 8000f30 <HAL_RCC_OscConfig+0x5c0>
{
return HAL_TIMEOUT;
8000f2c: 2303 movs r3, #3
8000f2e: e02c b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000f30: 4b18 ldr r3, [pc, #96] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000f32: 681a ldr r2, [r3, #0]
8000f34: 2380 movs r3, #128 ; 0x80
8000f36: 049b lsls r3, r3, #18
8000f38: 4013 ands r3, r2
8000f3a: d1f0 bne.n 8000f1e <HAL_RCC_OscConfig+0x5ae>
8000f3c: e024 b.n 8000f88 <HAL_RCC_OscConfig+0x618>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8000f3e: 687b ldr r3, [r7, #4]
8000f40: 6a1b ldr r3, [r3, #32]
8000f42: 2b01 cmp r3, #1
8000f44: d101 bne.n 8000f4a <HAL_RCC_OscConfig+0x5da>
{
return HAL_ERROR;
8000f46: 2301 movs r3, #1
8000f48: e01f b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8000f4a: 4b12 ldr r3, [pc, #72] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000f4c: 685b ldr r3, [r3, #4]
8000f4e: 617b str r3, [r7, #20]
pll_config2 = RCC->CFGR2;
8000f50: 4b10 ldr r3, [pc, #64] ; (8000f94 <HAL_RCC_OscConfig+0x624>)
8000f52: 6adb ldr r3, [r3, #44] ; 0x2c
8000f54: 613b str r3, [r7, #16]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8000f56: 697a ldr r2, [r7, #20]
8000f58: 2380 movs r3, #128 ; 0x80
8000f5a: 025b lsls r3, r3, #9
8000f5c: 401a ands r2, r3
8000f5e: 687b ldr r3, [r7, #4]
8000f60: 6a5b ldr r3, [r3, #36] ; 0x24
8000f62: 429a cmp r2, r3
8000f64: d10e bne.n 8000f84 <HAL_RCC_OscConfig+0x614>
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8000f66: 693b ldr r3, [r7, #16]
8000f68: 220f movs r2, #15
8000f6a: 401a ands r2, r3
8000f6c: 687b ldr r3, [r7, #4]
8000f6e: 6adb ldr r3, [r3, #44] ; 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8000f70: 429a cmp r2, r3
8000f72: d107 bne.n 8000f84 <HAL_RCC_OscConfig+0x614>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8000f74: 697a ldr r2, [r7, #20]
8000f76: 23f0 movs r3, #240 ; 0xf0
8000f78: 039b lsls r3, r3, #14
8000f7a: 401a ands r2, r3
8000f7c: 687b ldr r3, [r7, #4]
8000f7e: 6a9b ldr r3, [r3, #40] ; 0x28
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
8000f80: 429a cmp r2, r3
8000f82: d001 beq.n 8000f88 <HAL_RCC_OscConfig+0x618>
{
return HAL_ERROR;
8000f84: 2301 movs r3, #1
8000f86: e000 b.n 8000f8a <HAL_RCC_OscConfig+0x61a>
}
}
}
}
return HAL_OK;
8000f88: 2300 movs r3, #0
}
8000f8a: 0018 movs r0, r3
8000f8c: 46bd mov sp, r7
8000f8e: b008 add sp, #32
8000f90: bd80 pop {r7, pc}
8000f92: 46c0 nop ; (mov r8, r8)
8000f94: 40021000 .word 0x40021000
8000f98: 00001388 .word 0x00001388
8000f9c: efffffff .word 0xefffffff
8000fa0: feffffff .word 0xfeffffff
8000fa4: ffc2ffff .word 0xffc2ffff
08000fa8 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8000fa8: b580 push {r7, lr}
8000faa: b084 sub sp, #16
8000fac: af00 add r7, sp, #0
8000fae: 6078 str r0, [r7, #4]
8000fb0: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8000fb2: 687b ldr r3, [r7, #4]
8000fb4: 2b00 cmp r3, #0
8000fb6: d101 bne.n 8000fbc <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8000fb8: 2301 movs r3, #1
8000fba: e0b3 b.n 8001124 <HAL_RCC_ClockConfig+0x17c>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8000fbc: 4b5b ldr r3, [pc, #364] ; (800112c <HAL_RCC_ClockConfig+0x184>)
8000fbe: 681b ldr r3, [r3, #0]
8000fc0: 2201 movs r2, #1
8000fc2: 4013 ands r3, r2
8000fc4: 683a ldr r2, [r7, #0]
8000fc6: 429a cmp r2, r3
8000fc8: d911 bls.n 8000fee <HAL_RCC_ClockConfig+0x46>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8000fca: 4b58 ldr r3, [pc, #352] ; (800112c <HAL_RCC_ClockConfig+0x184>)
8000fcc: 681b ldr r3, [r3, #0]
8000fce: 2201 movs r2, #1
8000fd0: 4393 bics r3, r2
8000fd2: 0019 movs r1, r3
8000fd4: 4b55 ldr r3, [pc, #340] ; (800112c <HAL_RCC_ClockConfig+0x184>)
8000fd6: 683a ldr r2, [r7, #0]
8000fd8: 430a orrs r2, r1
8000fda: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8000fdc: 4b53 ldr r3, [pc, #332] ; (800112c <HAL_RCC_ClockConfig+0x184>)
8000fde: 681b ldr r3, [r3, #0]
8000fe0: 2201 movs r2, #1
8000fe2: 4013 ands r3, r2
8000fe4: 683a ldr r2, [r7, #0]
8000fe6: 429a cmp r2, r3
8000fe8: d001 beq.n 8000fee <HAL_RCC_ClockConfig+0x46>
{
return HAL_ERROR;
8000fea: 2301 movs r3, #1
8000fec: e09a b.n 8001124 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8000fee: 687b ldr r3, [r7, #4]
8000ff0: 681b ldr r3, [r3, #0]
8000ff2: 2202 movs r2, #2
8000ff4: 4013 ands r3, r2
8000ff6: d015 beq.n 8001024 <HAL_RCC_ClockConfig+0x7c>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8000ff8: 687b ldr r3, [r7, #4]
8000ffa: 681b ldr r3, [r3, #0]
8000ffc: 2204 movs r2, #4
8000ffe: 4013 ands r3, r2
8001000: d006 beq.n 8001010 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
8001002: 4b4b ldr r3, [pc, #300] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
8001004: 685a ldr r2, [r3, #4]
8001006: 4b4a ldr r3, [pc, #296] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
8001008: 21e0 movs r1, #224 ; 0xe0
800100a: 00c9 lsls r1, r1, #3
800100c: 430a orrs r2, r1
800100e: 605a str r2, [r3, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001010: 4b47 ldr r3, [pc, #284] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
8001012: 685b ldr r3, [r3, #4]
8001014: 22f0 movs r2, #240 ; 0xf0
8001016: 4393 bics r3, r2
8001018: 0019 movs r1, r3
800101a: 687b ldr r3, [r7, #4]
800101c: 689a ldr r2, [r3, #8]
800101e: 4b44 ldr r3, [pc, #272] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
8001020: 430a orrs r2, r1
8001022: 605a str r2, [r3, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001024: 687b ldr r3, [r7, #4]
8001026: 681b ldr r3, [r3, #0]
8001028: 2201 movs r2, #1
800102a: 4013 ands r3, r2
800102c: d040 beq.n 80010b0 <HAL_RCC_ClockConfig+0x108>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800102e: 687b ldr r3, [r7, #4]
8001030: 685b ldr r3, [r3, #4]
8001032: 2b01 cmp r3, #1
8001034: d107 bne.n 8001046 <HAL_RCC_ClockConfig+0x9e>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001036: 4b3e ldr r3, [pc, #248] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
8001038: 681a ldr r2, [r3, #0]
800103a: 2380 movs r3, #128 ; 0x80
800103c: 029b lsls r3, r3, #10
800103e: 4013 ands r3, r2
8001040: d114 bne.n 800106c <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001042: 2301 movs r3, #1
8001044: e06e b.n 8001124 <HAL_RCC_ClockConfig+0x17c>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001046: 687b ldr r3, [r7, #4]
8001048: 685b ldr r3, [r3, #4]
800104a: 2b02 cmp r3, #2
800104c: d107 bne.n 800105e <HAL_RCC_ClockConfig+0xb6>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800104e: 4b38 ldr r3, [pc, #224] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
8001050: 681a ldr r2, [r3, #0]
8001052: 2380 movs r3, #128 ; 0x80
8001054: 049b lsls r3, r3, #18
8001056: 4013 ands r3, r2
8001058: d108 bne.n 800106c <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
800105a: 2301 movs r3, #1
800105c: e062 b.n 8001124 <HAL_RCC_ClockConfig+0x17c>
#endif /* RCC_CFGR_SWS_HSI48 */
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800105e: 4b34 ldr r3, [pc, #208] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
8001060: 681b ldr r3, [r3, #0]
8001062: 2202 movs r2, #2
8001064: 4013 ands r3, r2
8001066: d101 bne.n 800106c <HAL_RCC_ClockConfig+0xc4>
{
return HAL_ERROR;
8001068: 2301 movs r3, #1
800106a: e05b b.n 8001124 <HAL_RCC_ClockConfig+0x17c>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800106c: 4b30 ldr r3, [pc, #192] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
800106e: 685b ldr r3, [r3, #4]
8001070: 2203 movs r2, #3
8001072: 4393 bics r3, r2
8001074: 0019 movs r1, r3
8001076: 687b ldr r3, [r7, #4]
8001078: 685a ldr r2, [r3, #4]
800107a: 4b2d ldr r3, [pc, #180] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
800107c: 430a orrs r2, r1
800107e: 605a str r2, [r3, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001080: f7ff fa08 bl 8000494 <HAL_GetTick>
8001084: 0003 movs r3, r0
8001086: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001088: e009 b.n 800109e <HAL_RCC_ClockConfig+0xf6>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
800108a: f7ff fa03 bl 8000494 <HAL_GetTick>
800108e: 0002 movs r2, r0
8001090: 68fb ldr r3, [r7, #12]
8001092: 1ad3 subs r3, r2, r3
8001094: 4a27 ldr r2, [pc, #156] ; (8001134 <HAL_RCC_ClockConfig+0x18c>)
8001096: 4293 cmp r3, r2
8001098: d901 bls.n 800109e <HAL_RCC_ClockConfig+0xf6>
{
return HAL_TIMEOUT;
800109a: 2303 movs r3, #3
800109c: e042 b.n 8001124 <HAL_RCC_ClockConfig+0x17c>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800109e: 4b24 ldr r3, [pc, #144] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
80010a0: 685b ldr r3, [r3, #4]
80010a2: 220c movs r2, #12
80010a4: 401a ands r2, r3
80010a6: 687b ldr r3, [r7, #4]
80010a8: 685b ldr r3, [r3, #4]
80010aa: 009b lsls r3, r3, #2
80010ac: 429a cmp r2, r3
80010ae: d1ec bne.n 800108a <HAL_RCC_ClockConfig+0xe2>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
80010b0: 4b1e ldr r3, [pc, #120] ; (800112c <HAL_RCC_ClockConfig+0x184>)
80010b2: 681b ldr r3, [r3, #0]
80010b4: 2201 movs r2, #1
80010b6: 4013 ands r3, r2
80010b8: 683a ldr r2, [r7, #0]
80010ba: 429a cmp r2, r3
80010bc: d211 bcs.n 80010e2 <HAL_RCC_ClockConfig+0x13a>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80010be: 4b1b ldr r3, [pc, #108] ; (800112c <HAL_RCC_ClockConfig+0x184>)
80010c0: 681b ldr r3, [r3, #0]
80010c2: 2201 movs r2, #1
80010c4: 4393 bics r3, r2
80010c6: 0019 movs r1, r3
80010c8: 4b18 ldr r3, [pc, #96] ; (800112c <HAL_RCC_ClockConfig+0x184>)
80010ca: 683a ldr r2, [r7, #0]
80010cc: 430a orrs r2, r1
80010ce: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80010d0: 4b16 ldr r3, [pc, #88] ; (800112c <HAL_RCC_ClockConfig+0x184>)
80010d2: 681b ldr r3, [r3, #0]
80010d4: 2201 movs r2, #1
80010d6: 4013 ands r3, r2
80010d8: 683a ldr r2, [r7, #0]
80010da: 429a cmp r2, r3
80010dc: d001 beq.n 80010e2 <HAL_RCC_ClockConfig+0x13a>
{
return HAL_ERROR;
80010de: 2301 movs r3, #1
80010e0: e020 b.n 8001124 <HAL_RCC_ClockConfig+0x17c>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80010e2: 687b ldr r3, [r7, #4]
80010e4: 681b ldr r3, [r3, #0]
80010e6: 2204 movs r2, #4
80010e8: 4013 ands r3, r2
80010ea: d009 beq.n 8001100 <HAL_RCC_ClockConfig+0x158>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
80010ec: 4b10 ldr r3, [pc, #64] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
80010ee: 685b ldr r3, [r3, #4]
80010f0: 4a11 ldr r2, [pc, #68] ; (8001138 <HAL_RCC_ClockConfig+0x190>)
80010f2: 4013 ands r3, r2
80010f4: 0019 movs r1, r3
80010f6: 687b ldr r3, [r7, #4]
80010f8: 68da ldr r2, [r3, #12]
80010fa: 4b0d ldr r3, [pc, #52] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
80010fc: 430a orrs r2, r1
80010fe: 605a str r2, [r3, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8001100: f000 f820 bl 8001144 <HAL_RCC_GetSysClockFreq>
8001104: 0001 movs r1, r0
8001106: 4b0a ldr r3, [pc, #40] ; (8001130 <HAL_RCC_ClockConfig+0x188>)
8001108: 685b ldr r3, [r3, #4]
800110a: 091b lsrs r3, r3, #4
800110c: 220f movs r2, #15
800110e: 4013 ands r3, r2
8001110: 4a0a ldr r2, [pc, #40] ; (800113c <HAL_RCC_ClockConfig+0x194>)
8001112: 5cd3 ldrb r3, [r2, r3]
8001114: 000a movs r2, r1
8001116: 40da lsrs r2, r3
8001118: 4b09 ldr r3, [pc, #36] ; (8001140 <HAL_RCC_ClockConfig+0x198>)
800111a: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
800111c: 2000 movs r0, #0
800111e: f7ff f973 bl 8000408 <HAL_InitTick>
return HAL_OK;
8001122: 2300 movs r3, #0
}
8001124: 0018 movs r0, r3
8001126: 46bd mov sp, r7
8001128: b004 add sp, #16
800112a: bd80 pop {r7, pc}
800112c: 40022000 .word 0x40022000
8001130: 40021000 .word 0x40021000
8001134: 00001388 .word 0x00001388
8001138: fffff8ff .word 0xfffff8ff
800113c: 0800129c .word 0x0800129c
8001140: 20000000 .word 0x20000000
08001144 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001144: b590 push {r4, r7, lr}
8001146: b08f sub sp, #60 ; 0x3c
8001148: af00 add r7, sp, #0
const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
800114a: 2314 movs r3, #20
800114c: 18fb adds r3, r7, r3
800114e: 4a2b ldr r2, [pc, #172] ; (80011fc <HAL_RCC_GetSysClockFreq+0xb8>)
8001150: ca13 ldmia r2!, {r0, r1, r4}
8001152: c313 stmia r3!, {r0, r1, r4}
8001154: 6812 ldr r2, [r2, #0]
8001156: 601a str r2, [r3, #0]
10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
8001158: 1d3b adds r3, r7, #4
800115a: 4a29 ldr r2, [pc, #164] ; (8001200 <HAL_RCC_GetSysClockFreq+0xbc>)
800115c: ca13 ldmia r2!, {r0, r1, r4}
800115e: c313 stmia r3!, {r0, r1, r4}
8001160: 6812 ldr r2, [r2, #0]
8001162: 601a str r2, [r3, #0]
9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8001164: 2300 movs r3, #0
8001166: 62fb str r3, [r7, #44] ; 0x2c
8001168: 2300 movs r3, #0
800116a: 62bb str r3, [r7, #40] ; 0x28
800116c: 2300 movs r3, #0
800116e: 637b str r3, [r7, #52] ; 0x34
8001170: 2300 movs r3, #0
8001172: 627b str r3, [r7, #36] ; 0x24
uint32_t sysclockfreq = 0U;
8001174: 2300 movs r3, #0
8001176: 633b str r3, [r7, #48] ; 0x30
tmpreg = RCC->CFGR;
8001178: 4b22 ldr r3, [pc, #136] ; (8001204 <HAL_RCC_GetSysClockFreq+0xc0>)
800117a: 685b ldr r3, [r3, #4]
800117c: 62fb str r3, [r7, #44] ; 0x2c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
800117e: 6afb ldr r3, [r7, #44] ; 0x2c
8001180: 220c movs r2, #12
8001182: 4013 ands r3, r2
8001184: 2b04 cmp r3, #4
8001186: d002 beq.n 800118e <HAL_RCC_GetSysClockFreq+0x4a>
8001188: 2b08 cmp r3, #8
800118a: d003 beq.n 8001194 <HAL_RCC_GetSysClockFreq+0x50>
800118c: e02d b.n 80011ea <HAL_RCC_GetSysClockFreq+0xa6>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
800118e: 4b1e ldr r3, [pc, #120] ; (8001208 <HAL_RCC_GetSysClockFreq+0xc4>)
8001190: 633b str r3, [r7, #48] ; 0x30
break;
8001192: e02d b.n 80011f0 <HAL_RCC_GetSysClockFreq+0xac>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
8001194: 6afb ldr r3, [r7, #44] ; 0x2c
8001196: 0c9b lsrs r3, r3, #18
8001198: 220f movs r2, #15
800119a: 4013 ands r3, r2
800119c: 2214 movs r2, #20
800119e: 18ba adds r2, r7, r2
80011a0: 5cd3 ldrb r3, [r2, r3]
80011a2: 627b str r3, [r7, #36] ; 0x24
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
80011a4: 4b17 ldr r3, [pc, #92] ; (8001204 <HAL_RCC_GetSysClockFreq+0xc0>)
80011a6: 6adb ldr r3, [r3, #44] ; 0x2c
80011a8: 220f movs r2, #15
80011aa: 4013 ands r3, r2
80011ac: 1d3a adds r2, r7, #4
80011ae: 5cd3 ldrb r3, [r2, r3]
80011b0: 62bb str r3, [r7, #40] ; 0x28
if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
80011b2: 6afa ldr r2, [r7, #44] ; 0x2c
80011b4: 2380 movs r3, #128 ; 0x80
80011b6: 025b lsls r3, r3, #9
80011b8: 4013 ands r3, r2
80011ba: d009 beq.n 80011d0 <HAL_RCC_GetSysClockFreq+0x8c>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
80011bc: 6ab9 ldr r1, [r7, #40] ; 0x28
80011be: 4812 ldr r0, [pc, #72] ; (8001208 <HAL_RCC_GetSysClockFreq+0xc4>)
80011c0: f7fe ffa2 bl 8000108 <__udivsi3>
80011c4: 0003 movs r3, r0
80011c6: 001a movs r2, r3
80011c8: 6a7b ldr r3, [r7, #36] ; 0x24
80011ca: 4353 muls r3, r2
80011cc: 637b str r3, [r7, #52] ; 0x34
80011ce: e009 b.n 80011e4 <HAL_RCC_GetSysClockFreq+0xa0>
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
#else
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
80011d0: 6a79 ldr r1, [r7, #36] ; 0x24
80011d2: 000a movs r2, r1
80011d4: 0152 lsls r2, r2, #5
80011d6: 1a52 subs r2, r2, r1
80011d8: 0193 lsls r3, r2, #6
80011da: 1a9b subs r3, r3, r2
80011dc: 00db lsls r3, r3, #3
80011de: 185b adds r3, r3, r1
80011e0: 021b lsls r3, r3, #8
80011e2: 637b str r3, [r7, #52] ; 0x34
#endif
}
sysclockfreq = pllclk;
80011e4: 6b7b ldr r3, [r7, #52] ; 0x34
80011e6: 633b str r3, [r7, #48] ; 0x30
break;
80011e8: e002 b.n 80011f0 <HAL_RCC_GetSysClockFreq+0xac>
}
#endif /* RCC_CFGR_SWS_HSI48 */
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
80011ea: 4b07 ldr r3, [pc, #28] ; (8001208 <HAL_RCC_GetSysClockFreq+0xc4>)
80011ec: 633b str r3, [r7, #48] ; 0x30
break;
80011ee: 46c0 nop ; (mov r8, r8)
}
}
return sysclockfreq;
80011f0: 6b3b ldr r3, [r7, #48] ; 0x30
}
80011f2: 0018 movs r0, r3
80011f4: 46bd mov sp, r7
80011f6: b00f add sp, #60 ; 0x3c
80011f8: bd90 pop {r4, r7, pc}
80011fa: 46c0 nop ; (mov r8, r8)
80011fc: 0800127c .word 0x0800127c
8001200: 0800128c .word 0x0800128c
8001204: 40021000 .word 0x40021000
8001208: 007a1200 .word 0x007a1200
0800120c <__libc_init_array>:
800120c: b570 push {r4, r5, r6, lr}
800120e: 2600 movs r6, #0
8001210: 4d0c ldr r5, [pc, #48] ; (8001244 <__libc_init_array+0x38>)
8001212: 4c0d ldr r4, [pc, #52] ; (8001248 <__libc_init_array+0x3c>)
8001214: 1b64 subs r4, r4, r5
8001216: 10a4 asrs r4, r4, #2
8001218: 42a6 cmp r6, r4
800121a: d109 bne.n 8001230 <__libc_init_array+0x24>
800121c: 2600 movs r6, #0
800121e: f000 f821 bl 8001264 <_init>
8001222: 4d0a ldr r5, [pc, #40] ; (800124c <__libc_init_array+0x40>)
8001224: 4c0a ldr r4, [pc, #40] ; (8001250 <__libc_init_array+0x44>)
8001226: 1b64 subs r4, r4, r5
8001228: 10a4 asrs r4, r4, #2
800122a: 42a6 cmp r6, r4
800122c: d105 bne.n 800123a <__libc_init_array+0x2e>
800122e: bd70 pop {r4, r5, r6, pc}
8001230: 00b3 lsls r3, r6, #2
8001232: 58eb ldr r3, [r5, r3]
8001234: 4798 blx r3
8001236: 3601 adds r6, #1
8001238: e7ee b.n 8001218 <__libc_init_array+0xc>
800123a: 00b3 lsls r3, r6, #2
800123c: 58eb ldr r3, [r5, r3]
800123e: 4798 blx r3
8001240: 3601 adds r6, #1
8001242: e7f2 b.n 800122a <__libc_init_array+0x1e>
8001244: 080012ac .word 0x080012ac
8001248: 080012ac .word 0x080012ac
800124c: 080012ac .word 0x080012ac
8001250: 080012b0 .word 0x080012b0
08001254 <memset>:
8001254: 0003 movs r3, r0
8001256: 1812 adds r2, r2, r0
8001258: 4293 cmp r3, r2
800125a: d100 bne.n 800125e <memset+0xa>
800125c: 4770 bx lr
800125e: 7019 strb r1, [r3, #0]
8001260: 3301 adds r3, #1
8001262: e7f9 b.n 8001258 <memset+0x4>
08001264 <_init>:
8001264: b5f8 push {r3, r4, r5, r6, r7, lr}
8001266: 46c0 nop ; (mov r8, r8)
8001268: bcf8 pop {r3, r4, r5, r6, r7}
800126a: bc08 pop {r3}
800126c: 469e mov lr, r3
800126e: 4770 bx lr
08001270 <_fini>:
8001270: b5f8 push {r3, r4, r5, r6, r7, lr}
8001272: 46c0 nop ; (mov r8, r8)
8001274: bcf8 pop {r3, r4, r5, r6, r7}
8001276: bc08 pop {r3}
8001278: 469e mov lr, r3
800127a: 4770 bx lr
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