LED.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000012fc 080000c0 080000c0 000100c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000030 080013bc 080013bc 000113bc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080013ec 080013ec 0002000c 2**0 CONTENTS 4 .ARM 00000000 080013ec 080013ec 0002000c 2**0 CONTENTS 5 .preinit_array 00000000 080013ec 080013ec 0002000c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080013ec 080013ec 000113ec 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 080013f0 080013f0 000113f0 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000000c 20000000 080013f4 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000020 2000000c 08001400 0002000c 2**2 ALLOC 10 ._user_heap_stack 00000604 2000002c 08001400 0002002c 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0 CONTENTS, READONLY 12 .debug_info 00002838 00000000 00000000 00020034 2**0 CONTENTS, READONLY, DEBUGGING 13 .debug_abbrev 00000ce0 00000000 00000000 0002286c 2**0 CONTENTS, READONLY, DEBUGGING 14 .debug_aranges 00000350 00000000 00000000 00023550 2**3 CONTENTS, READONLY, DEBUGGING 15 .debug_ranges 000002c8 00000000 00000000 000238a0 2**3 CONTENTS, READONLY, DEBUGGING 16 .debug_macro 0000ddc1 00000000 00000000 00023b68 2**0 CONTENTS, READONLY, DEBUGGING 17 .debug_line 00003b83 00000000 00000000 00031929 2**0 CONTENTS, READONLY, DEBUGGING 18 .debug_str 00052cf2 00000000 00000000 000354ac 2**0 CONTENTS, READONLY, DEBUGGING 19 .comment 0000007b 00000000 00000000 0008819e 2**0 CONTENTS, READONLY 20 .debug_frame 000009f8 00000000 00000000 0008821c 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 080000c0 <__do_global_dtors_aux>: 80000c0: b510 push {r4, lr} 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) 80000c4: 7823 ldrb r3, [r4, #0] 80000c6: 2b00 cmp r3, #0 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) 80000cc: 2b00 cmp r3, #0 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> 80000d4: bf00 nop 80000d6: 2301 movs r3, #1 80000d8: 7023 strb r3, [r4, #0] 80000da: bd10 pop {r4, pc} 80000dc: 2000000c .word 0x2000000c 80000e0: 00000000 .word 0x00000000 80000e4: 080013a4 .word 0x080013a4 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) 80000ea: b510 push {r4, lr} 80000ec: 2b00 cmp r3, #0 80000ee: d003 beq.n 80000f8 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) 80000f4: e000 b.n 80000f8 80000f6: bf00 nop 80000f8: bd10 pop {r4, pc} 80000fa: 46c0 nop ; (mov r8, r8) 80000fc: 00000000 .word 0x00000000 8000100: 20000010 .word 0x20000010 8000104: 080013a4 .word 0x080013a4 08000108 <__udivsi3>: 8000108: 2200 movs r2, #0 800010a: 0843 lsrs r3, r0, #1 800010c: 428b cmp r3, r1 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> 8000110: 0903 lsrs r3, r0, #4 8000112: 428b cmp r3, r1 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> 8000116: 0a03 lsrs r3, r0, #8 8000118: 428b cmp r3, r1 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> 800011c: 0b03 lsrs r3, r0, #12 800011e: 428b cmp r3, r1 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> 8000122: 0c03 lsrs r3, r0, #16 8000124: 428b cmp r3, r1 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> 8000128: 22ff movs r2, #255 ; 0xff 800012a: 0209 lsls r1, r1, #8 800012c: ba12 rev r2, r2 800012e: 0c03 lsrs r3, r0, #16 8000130: 428b cmp r3, r1 8000132: d302 bcc.n 800013a <__udivsi3+0x32> 8000134: 1212 asrs r2, r2, #8 8000136: 0209 lsls r1, r1, #8 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> 800013a: 0b03 lsrs r3, r0, #12 800013c: 428b cmp r3, r1 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> 8000140: e000 b.n 8000144 <__udivsi3+0x3c> 8000142: 0a09 lsrs r1, r1, #8 8000144: 0bc3 lsrs r3, r0, #15 8000146: 428b cmp r3, r1 8000148: d301 bcc.n 800014e <__udivsi3+0x46> 800014a: 03cb lsls r3, r1, #15 800014c: 1ac0 subs r0, r0, r3 800014e: 4152 adcs r2, r2 8000150: 0b83 lsrs r3, r0, #14 8000152: 428b cmp r3, r1 8000154: d301 bcc.n 800015a <__udivsi3+0x52> 8000156: 038b lsls r3, r1, #14 8000158: 1ac0 subs r0, r0, r3 800015a: 4152 adcs r2, r2 800015c: 0b43 lsrs r3, r0, #13 800015e: 428b cmp r3, r1 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> 8000162: 034b lsls r3, r1, #13 8000164: 1ac0 subs r0, r0, r3 8000166: 4152 adcs r2, r2 8000168: 0b03 lsrs r3, r0, #12 800016a: 428b cmp r3, r1 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> 800016e: 030b lsls r3, r1, #12 8000170: 1ac0 subs r0, r0, r3 8000172: 4152 adcs r2, r2 8000174: 0ac3 lsrs r3, r0, #11 8000176: 428b cmp r3, r1 8000178: d301 bcc.n 800017e <__udivsi3+0x76> 800017a: 02cb lsls r3, r1, #11 800017c: 1ac0 subs r0, r0, r3 800017e: 4152 adcs r2, r2 8000180: 0a83 lsrs r3, r0, #10 8000182: 428b cmp r3, r1 8000184: d301 bcc.n 800018a <__udivsi3+0x82> 8000186: 028b lsls r3, r1, #10 8000188: 1ac0 subs r0, r0, r3 800018a: 4152 adcs r2, r2 800018c: 0a43 lsrs r3, r0, #9 800018e: 428b cmp r3, r1 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> 8000192: 024b lsls r3, r1, #9 8000194: 1ac0 subs r0, r0, r3 8000196: 4152 adcs r2, r2 8000198: 0a03 lsrs r3, r0, #8 800019a: 428b cmp r3, r1 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> 800019e: 020b lsls r3, r1, #8 80001a0: 1ac0 subs r0, r0, r3 80001a2: 4152 adcs r2, r2 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> 80001a6: 09c3 lsrs r3, r0, #7 80001a8: 428b cmp r3, r1 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> 80001ac: 01cb lsls r3, r1, #7 80001ae: 1ac0 subs r0, r0, r3 80001b0: 4152 adcs r2, r2 80001b2: 0983 lsrs r3, r0, #6 80001b4: 428b cmp r3, r1 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> 80001b8: 018b lsls r3, r1, #6 80001ba: 1ac0 subs r0, r0, r3 80001bc: 4152 adcs r2, r2 80001be: 0943 lsrs r3, r0, #5 80001c0: 428b cmp r3, r1 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> 80001c4: 014b lsls r3, r1, #5 80001c6: 1ac0 subs r0, r0, r3 80001c8: 4152 adcs r2, r2 80001ca: 0903 lsrs r3, r0, #4 80001cc: 428b cmp r3, r1 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> 80001d0: 010b lsls r3, r1, #4 80001d2: 1ac0 subs r0, r0, r3 80001d4: 4152 adcs r2, r2 80001d6: 08c3 lsrs r3, r0, #3 80001d8: 428b cmp r3, r1 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> 80001dc: 00cb lsls r3, r1, #3 80001de: 1ac0 subs r0, r0, r3 80001e0: 4152 adcs r2, r2 80001e2: 0883 lsrs r3, r0, #2 80001e4: 428b cmp r3, r1 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> 80001e8: 008b lsls r3, r1, #2 80001ea: 1ac0 subs r0, r0, r3 80001ec: 4152 adcs r2, r2 80001ee: 0843 lsrs r3, r0, #1 80001f0: 428b cmp r3, r1 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> 80001f4: 004b lsls r3, r1, #1 80001f6: 1ac0 subs r0, r0, r3 80001f8: 4152 adcs r2, r2 80001fa: 1a41 subs r1, r0, r1 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> 80001fe: 4601 mov r1, r0 8000200: 4152 adcs r2, r2 8000202: 4610 mov r0, r2 8000204: 4770 bx lr 8000206: e7ff b.n 8000208 <__udivsi3+0x100> 8000208: b501 push {r0, lr} 800020a: 2000 movs r0, #0 800020c: f000 f806 bl 800021c <__aeabi_idiv0> 8000210: bd02 pop {r1, pc} 8000212: 46c0 nop ; (mov r8, r8) 08000214 <__aeabi_uidivmod>: 8000214: 2900 cmp r1, #0 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> 8000218: e776 b.n 8000108 <__udivsi3> 800021a: 4770 bx lr 0800021c <__aeabi_idiv0>: 800021c: 4770 bx lr 800021e: 46c0 nop ; (mov r8, r8) 08000220
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000220: b580 push {r7, lr} 8000222: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000224: f000 f960 bl 80004e8 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000228: f000 f816 bl 8000258 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800022c: f000 f854 bl 80002d8 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6)); 8000230: 2390 movs r3, #144 ; 0x90 8000232: 05db lsls r3, r3, #23 8000234: 2140 movs r1, #64 ; 0x40 8000236: 0018 movs r0, r3 8000238: f000 fc00 bl 8000a3c 800023c: 0003 movs r3, r0 800023e: 001a movs r2, r3 8000240: 2390 movs r3, #144 ; 0x90 8000242: 05db lsls r3, r3, #23 8000244: 2104 movs r1, #4 8000246: 0018 movs r0, r3 8000248: f000 fc15 bl 8000a76 HAL_Delay(1000); 800024c: 23fa movs r3, #250 ; 0xfa 800024e: 009b lsls r3, r3, #2 8000250: 0018 movs r0, r3 8000252: f000 f9ad bl 80005b0 HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_6)); 8000256: e7eb b.n 8000230 08000258 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000258: b590 push {r4, r7, lr} 800025a: b091 sub sp, #68 ; 0x44 800025c: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800025e: 2410 movs r4, #16 8000260: 193b adds r3, r7, r4 8000262: 0018 movs r0, r3 8000264: 2330 movs r3, #48 ; 0x30 8000266: 001a movs r2, r3 8000268: 2100 movs r1, #0 800026a: f001 f893 bl 8001394 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800026e: 003b movs r3, r7 8000270: 0018 movs r0, r3 8000272: 2310 movs r3, #16 8000274: 001a movs r2, r3 8000276: 2100 movs r1, #0 8000278: f001 f88c bl 8001394 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 800027c: 0021 movs r1, r4 800027e: 187b adds r3, r7, r1 8000280: 2202 movs r2, #2 8000282: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000284: 187b adds r3, r7, r1 8000286: 2201 movs r2, #1 8000288: 60da str r2, [r3, #12] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 800028a: 187b adds r3, r7, r1 800028c: 2210 movs r2, #16 800028e: 611a str r2, [r3, #16] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8000290: 187b adds r3, r7, r1 8000292: 2200 movs r2, #0 8000294: 621a str r2, [r3, #32] if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000296: 187b adds r3, r7, r1 8000298: 0018 movs r0, r3 800029a: f000 fc09 bl 8000ab0 800029e: 1e03 subs r3, r0, #0 80002a0: d001 beq.n 80002a6 { Error_Handler(); 80002a2: f000 f8b3 bl 800040c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80002a6: 003b movs r3, r7 80002a8: 2207 movs r2, #7 80002aa: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 80002ac: 003b movs r3, r7 80002ae: 2200 movs r2, #0 80002b0: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80002b2: 003b movs r3, r7 80002b4: 2200 movs r2, #0 80002b6: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80002b8: 003b movs r3, r7 80002ba: 2200 movs r2, #0 80002bc: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 80002be: 003b movs r3, r7 80002c0: 2100 movs r1, #0 80002c2: 0018 movs r0, r3 80002c4: f000 ff10 bl 80010e8 80002c8: 1e03 subs r3, r0, #0 80002ca: d001 beq.n 80002d0 { Error_Handler(); 80002cc: f000 f89e bl 800040c } } 80002d0: 46c0 nop ; (mov r8, r8) 80002d2: 46bd mov sp, r7 80002d4: b011 add sp, #68 ; 0x44 80002d6: bd90 pop {r4, r7, pc} 080002d8 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80002d8: b590 push {r4, r7, lr} 80002da: b089 sub sp, #36 ; 0x24 80002dc: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80002de: 240c movs r4, #12 80002e0: 193b adds r3, r7, r4 80002e2: 0018 movs r0, r3 80002e4: 2314 movs r3, #20 80002e6: 001a movs r2, r3 80002e8: 2100 movs r1, #0 80002ea: f001 f853 bl 8001394 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 80002ee: 4b45 ldr r3, [pc, #276] ; (8000404 ) 80002f0: 695a ldr r2, [r3, #20] 80002f2: 4b44 ldr r3, [pc, #272] ; (8000404 ) 80002f4: 2180 movs r1, #128 ; 0x80 80002f6: 03c9 lsls r1, r1, #15 80002f8: 430a orrs r2, r1 80002fa: 615a str r2, [r3, #20] 80002fc: 4b41 ldr r3, [pc, #260] ; (8000404 ) 80002fe: 695a ldr r2, [r3, #20] 8000300: 2380 movs r3, #128 ; 0x80 8000302: 03db lsls r3, r3, #15 8000304: 4013 ands r3, r2 8000306: 60bb str r3, [r7, #8] 8000308: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 800030a: 4b3e ldr r3, [pc, #248] ; (8000404 ) 800030c: 695a ldr r2, [r3, #20] 800030e: 4b3d ldr r3, [pc, #244] ; (8000404 ) 8000310: 2180 movs r1, #128 ; 0x80 8000312: 0289 lsls r1, r1, #10 8000314: 430a orrs r2, r1 8000316: 615a str r2, [r3, #20] 8000318: 4b3a ldr r3, [pc, #232] ; (8000404 ) 800031a: 695a ldr r2, [r3, #20] 800031c: 2380 movs r3, #128 ; 0x80 800031e: 029b lsls r3, r3, #10 8000320: 4013 ands r3, r2 8000322: 607b str r3, [r7, #4] 8000324: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000326: 4b37 ldr r3, [pc, #220] ; (8000404 ) 8000328: 695a ldr r2, [r3, #20] 800032a: 4b36 ldr r3, [pc, #216] ; (8000404 ) 800032c: 2180 movs r1, #128 ; 0x80 800032e: 02c9 lsls r1, r1, #11 8000330: 430a orrs r2, r1 8000332: 615a str r2, [r3, #20] 8000334: 4b33 ldr r3, [pc, #204] ; (8000404 ) 8000336: 695a ldr r2, [r3, #20] 8000338: 2380 movs r3, #128 ; 0x80 800033a: 02db lsls r3, r3, #11 800033c: 4013 ands r3, r2 800033e: 603b str r3, [r7, #0] 8000340: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, LED_Pin|TEN_Pin|Relay1_Pin, GPIO_PIN_RESET); 8000342: 2390 movs r3, #144 ; 0x90 8000344: 05db lsls r3, r3, #23 8000346: 2200 movs r2, #0 8000348: 21a4 movs r1, #164 ; 0xa4 800034a: 0018 movs r0, r3 800034c: f000 fb93 bl 8000a76 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(Relay2_GPIO_Port, Relay2_Pin, GPIO_PIN_RESET); 8000350: 4b2d ldr r3, [pc, #180] ; (8000408 ) 8000352: 2200 movs r2, #0 8000354: 2102 movs r1, #2 8000356: 0018 movs r0, r3 8000358: f000 fb8d bl 8000a76 /*Configure GPIO pins : IN1_Pin IN2_Pin Button_Pin */ GPIO_InitStruct.Pin = IN1_Pin|IN2_Pin|Button_Pin; 800035c: 193b adds r3, r7, r4 800035e: 2243 movs r2, #67 ; 0x43 8000360: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000362: 193b adds r3, r7, r4 8000364: 2200 movs r2, #0 8000366: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 8000368: 193b adds r3, r7, r4 800036a: 2201 movs r2, #1 800036c: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800036e: 193a adds r2, r7, r4 8000370: 2390 movs r3, #144 ; 0x90 8000372: 05db lsls r3, r3, #23 8000374: 0011 movs r1, r2 8000376: 0018 movs r0, r3 8000378: f000 f9f0 bl 800075c /*Configure GPIO pins : LED_Pin TEN_Pin Relay1_Pin */ GPIO_InitStruct.Pin = LED_Pin|TEN_Pin|Relay1_Pin; 800037c: 193b adds r3, r7, r4 800037e: 22a4 movs r2, #164 ; 0xa4 8000380: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000382: 193b adds r3, r7, r4 8000384: 2201 movs r2, #1 8000386: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000388: 193b adds r3, r7, r4 800038a: 2200 movs r2, #0 800038c: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800038e: 193b adds r3, r7, r4 8000390: 2203 movs r2, #3 8000392: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000394: 193a adds r2, r7, r4 8000396: 2390 movs r3, #144 ; 0x90 8000398: 05db lsls r3, r3, #23 800039a: 0011 movs r1, r2 800039c: 0018 movs r0, r3 800039e: f000 f9dd bl 800075c /*Configure GPIO pin : Relay2_Pin */ GPIO_InitStruct.Pin = Relay2_Pin; 80003a2: 0021 movs r1, r4 80003a4: 187b adds r3, r7, r1 80003a6: 2202 movs r2, #2 80003a8: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80003aa: 187b adds r3, r7, r1 80003ac: 2201 movs r2, #1 80003ae: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80003b0: 187b adds r3, r7, r1 80003b2: 2200 movs r2, #0 80003b4: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80003b6: 187b adds r3, r7, r1 80003b8: 2203 movs r2, #3 80003ba: 60da str r2, [r3, #12] HAL_GPIO_Init(Relay2_GPIO_Port, &GPIO_InitStruct); 80003bc: 000c movs r4, r1 80003be: 187b adds r3, r7, r1 80003c0: 4a11 ldr r2, [pc, #68] ; (8000408 ) 80003c2: 0019 movs r1, r3 80003c4: 0010 movs r0, r2 80003c6: f000 f9c9 bl 800075c /*Configure GPIO pins : PA9 PA10 */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 80003ca: 0021 movs r1, r4 80003cc: 187b adds r3, r7, r1 80003ce: 22c0 movs r2, #192 ; 0xc0 80003d0: 00d2 lsls r2, r2, #3 80003d2: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80003d4: 187b adds r3, r7, r1 80003d6: 2202 movs r2, #2 80003d8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80003da: 187b adds r3, r7, r1 80003dc: 2200 movs r2, #0 80003de: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80003e0: 187b adds r3, r7, r1 80003e2: 2203 movs r2, #3 80003e4: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_USART1; 80003e6: 187b adds r3, r7, r1 80003e8: 2201 movs r2, #1 80003ea: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80003ec: 187a adds r2, r7, r1 80003ee: 2390 movs r3, #144 ; 0x90 80003f0: 05db lsls r3, r3, #23 80003f2: 0011 movs r1, r2 80003f4: 0018 movs r0, r3 80003f6: f000 f9b1 bl 800075c } 80003fa: 46c0 nop ; (mov r8, r8) 80003fc: 46bd mov sp, r7 80003fe: b009 add sp, #36 ; 0x24 8000400: bd90 pop {r4, r7, pc} 8000402: 46c0 nop ; (mov r8, r8) 8000404: 40021000 .word 0x40021000 8000408: 48000400 .word 0x48000400 0800040c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800040c: b580 push {r7, lr} 800040e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000410: b672 cpsid i /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000412: e7fe b.n 8000412 08000414 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000414: b580 push {r7, lr} 8000416: b082 sub sp, #8 8000418: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800041a: 4b0f ldr r3, [pc, #60] ; (8000458 ) 800041c: 699a ldr r2, [r3, #24] 800041e: 4b0e ldr r3, [pc, #56] ; (8000458 ) 8000420: 2101 movs r1, #1 8000422: 430a orrs r2, r1 8000424: 619a str r2, [r3, #24] 8000426: 4b0c ldr r3, [pc, #48] ; (8000458 ) 8000428: 699b ldr r3, [r3, #24] 800042a: 2201 movs r2, #1 800042c: 4013 ands r3, r2 800042e: 607b str r3, [r7, #4] 8000430: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000432: 4b09 ldr r3, [pc, #36] ; (8000458 ) 8000434: 69da ldr r2, [r3, #28] 8000436: 4b08 ldr r3, [pc, #32] ; (8000458 ) 8000438: 2180 movs r1, #128 ; 0x80 800043a: 0549 lsls r1, r1, #21 800043c: 430a orrs r2, r1 800043e: 61da str r2, [r3, #28] 8000440: 4b05 ldr r3, [pc, #20] ; (8000458 ) 8000442: 69da ldr r2, [r3, #28] 8000444: 2380 movs r3, #128 ; 0x80 8000446: 055b lsls r3, r3, #21 8000448: 4013 ands r3, r2 800044a: 603b str r3, [r7, #0] 800044c: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800044e: 46c0 nop ; (mov r8, r8) 8000450: 46bd mov sp, r7 8000452: b002 add sp, #8 8000454: bd80 pop {r7, pc} 8000456: 46c0 nop ; (mov r8, r8) 8000458: 40021000 .word 0x40021000 0800045c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800045c: b580 push {r7, lr} 800045e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000460: e7fe b.n 8000460 08000462 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000462: b580 push {r7, lr} 8000464: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000466: e7fe b.n 8000466 08000468 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000468: b580 push {r7, lr} 800046a: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 800046c: 46c0 nop ; (mov r8, r8) 800046e: 46bd mov sp, r7 8000470: bd80 pop {r7, pc} 08000472 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000472: b580 push {r7, lr} 8000474: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000476: 46c0 nop ; (mov r8, r8) 8000478: 46bd mov sp, r7 800047a: bd80 pop {r7, pc} 0800047c : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800047c: b580 push {r7, lr} 800047e: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000480: f000 f87a bl 8000578 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000484: 46c0 nop ; (mov r8, r8) 8000486: 46bd mov sp, r7 8000488: bd80 pop {r7, pc} 0800048a : * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { 800048a: b580 push {r7, lr} 800048c: af00 add r7, sp, #0 before branch to main program. This call is made inside the "startup_stm32f0xx.s" file. User can setups the default system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings). */ } 800048e: 46c0 nop ; (mov r8, r8) 8000490: 46bd mov sp, r7 8000492: bd80 pop {r7, pc} 08000494 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8000494: 480d ldr r0, [pc, #52] ; (80004cc ) mov sp, r0 /* set stack pointer */ 8000496: 4685 mov sp, r0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000498: 480d ldr r0, [pc, #52] ; (80004d0 ) ldr r1, =_edata 800049a: 490e ldr r1, [pc, #56] ; (80004d4 ) ldr r2, =_sidata 800049c: 4a0e ldr r2, [pc, #56] ; (80004d8 ) movs r3, #0 800049e: 2300 movs r3, #0 b LoopCopyDataInit 80004a0: e002 b.n 80004a8 080004a2 : CopyDataInit: ldr r4, [r2, r3] 80004a2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80004a4: 50c4 str r4, [r0, r3] adds r3, r3, #4 80004a6: 3304 adds r3, #4 080004a8 : LoopCopyDataInit: adds r4, r0, r3 80004a8: 18c4 adds r4, r0, r3 cmp r4, r1 80004aa: 428c cmp r4, r1 bcc CopyDataInit 80004ac: d3f9 bcc.n 80004a2 /* Zero fill the bss segment. */ ldr r2, =_sbss 80004ae: 4a0b ldr r2, [pc, #44] ; (80004dc ) ldr r4, =_ebss 80004b0: 4c0b ldr r4, [pc, #44] ; (80004e0 ) movs r3, #0 80004b2: 2300 movs r3, #0 b LoopFillZerobss 80004b4: e001 b.n 80004ba 080004b6 : FillZerobss: str r3, [r2] 80004b6: 6013 str r3, [r2, #0] adds r2, r2, #4 80004b8: 3204 adds r2, #4 080004ba : LoopFillZerobss: cmp r2, r4 80004ba: 42a2 cmp r2, r4 bcc FillZerobss 80004bc: d3fb bcc.n 80004b6 /* Call the clock system intitialization function.*/ bl SystemInit 80004be: f7ff ffe4 bl 800048a /* Call static constructors */ bl __libc_init_array 80004c2: f000 ff43 bl 800134c <__libc_init_array> /* Call the application's entry point.*/ bl main 80004c6: f7ff feab bl 8000220
080004ca : LoopForever: b LoopForever 80004ca: e7fe b.n 80004ca ldr r0, =_estack 80004cc: 20001000 .word 0x20001000 ldr r0, =_sdata 80004d0: 20000000 .word 0x20000000 ldr r1, =_edata 80004d4: 2000000c .word 0x2000000c ldr r2, =_sidata 80004d8: 080013f4 .word 0x080013f4 ldr r2, =_sbss 80004dc: 2000000c .word 0x2000000c ldr r4, =_ebss 80004e0: 2000002c .word 0x2000002c 080004e4 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80004e4: e7fe b.n 80004e4 ... 080004e8 : * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80004e8: b580 push {r7, lr} 80004ea: af00 add r7, sp, #0 /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80004ec: 4b07 ldr r3, [pc, #28] ; (800050c ) 80004ee: 681a ldr r2, [r3, #0] 80004f0: 4b06 ldr r3, [pc, #24] ; (800050c ) 80004f2: 2110 movs r1, #16 80004f4: 430a orrs r2, r1 80004f6: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80004f8: 2000 movs r0, #0 80004fa: f000 f809 bl 8000510 /* Init the low level hardware */ HAL_MspInit(); 80004fe: f7ff ff89 bl 8000414 /* Return function status */ return HAL_OK; 8000502: 2300 movs r3, #0 } 8000504: 0018 movs r0, r3 8000506: 46bd mov sp, r7 8000508: bd80 pop {r7, pc} 800050a: 46c0 nop ; (mov r8, r8) 800050c: 40022000 .word 0x40022000 08000510 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000510: b590 push {r4, r7, lr} 8000512: b083 sub sp, #12 8000514: af00 add r7, sp, #0 8000516: 6078 str r0, [r7, #4] /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000518: 4b14 ldr r3, [pc, #80] ; (800056c ) 800051a: 681c ldr r4, [r3, #0] 800051c: 4b14 ldr r3, [pc, #80] ; (8000570 ) 800051e: 781b ldrb r3, [r3, #0] 8000520: 0019 movs r1, r3 8000522: 23fa movs r3, #250 ; 0xfa 8000524: 0098 lsls r0, r3, #2 8000526: f7ff fdef bl 8000108 <__udivsi3> 800052a: 0003 movs r3, r0 800052c: 0019 movs r1, r3 800052e: 0020 movs r0, r4 8000530: f7ff fdea bl 8000108 <__udivsi3> 8000534: 0003 movs r3, r0 8000536: 0018 movs r0, r3 8000538: f000 f903 bl 8000742 800053c: 1e03 subs r3, r0, #0 800053e: d001 beq.n 8000544 { return HAL_ERROR; 8000540: 2301 movs r3, #1 8000542: e00f b.n 8000564 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000544: 687b ldr r3, [r7, #4] 8000546: 2b03 cmp r3, #3 8000548: d80b bhi.n 8000562 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800054a: 6879 ldr r1, [r7, #4] 800054c: 2301 movs r3, #1 800054e: 425b negs r3, r3 8000550: 2200 movs r2, #0 8000552: 0018 movs r0, r3 8000554: f000 f8e0 bl 8000718 uwTickPrio = TickPriority; 8000558: 4b06 ldr r3, [pc, #24] ; (8000574 ) 800055a: 687a ldr r2, [r7, #4] 800055c: 601a str r2, [r3, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800055e: 2300 movs r3, #0 8000560: e000 b.n 8000564 return HAL_ERROR; 8000562: 2301 movs r3, #1 } 8000564: 0018 movs r0, r3 8000566: 46bd mov sp, r7 8000568: b003 add sp, #12 800056a: bd90 pop {r4, r7, pc} 800056c: 20000000 .word 0x20000000 8000570: 20000008 .word 0x20000008 8000574: 20000004 .word 0x20000004 08000578 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000578: b580 push {r7, lr} 800057a: af00 add r7, sp, #0 uwTick += uwTickFreq; 800057c: 4b05 ldr r3, [pc, #20] ; (8000594 ) 800057e: 781b ldrb r3, [r3, #0] 8000580: 001a movs r2, r3 8000582: 4b05 ldr r3, [pc, #20] ; (8000598 ) 8000584: 681b ldr r3, [r3, #0] 8000586: 18d2 adds r2, r2, r3 8000588: 4b03 ldr r3, [pc, #12] ; (8000598 ) 800058a: 601a str r2, [r3, #0] } 800058c: 46c0 nop ; (mov r8, r8) 800058e: 46bd mov sp, r7 8000590: bd80 pop {r7, pc} 8000592: 46c0 nop ; (mov r8, r8) 8000594: 20000008 .word 0x20000008 8000598: 20000028 .word 0x20000028 0800059c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800059c: b580 push {r7, lr} 800059e: af00 add r7, sp, #0 return uwTick; 80005a0: 4b02 ldr r3, [pc, #8] ; (80005ac ) 80005a2: 681b ldr r3, [r3, #0] } 80005a4: 0018 movs r0, r3 80005a6: 46bd mov sp, r7 80005a8: bd80 pop {r7, pc} 80005aa: 46c0 nop ; (mov r8, r8) 80005ac: 20000028 .word 0x20000028 080005b0 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80005b0: b580 push {r7, lr} 80005b2: b084 sub sp, #16 80005b4: af00 add r7, sp, #0 80005b6: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80005b8: f7ff fff0 bl 800059c 80005bc: 0003 movs r3, r0 80005be: 60bb str r3, [r7, #8] uint32_t wait = Delay; 80005c0: 687b ldr r3, [r7, #4] 80005c2: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80005c4: 68fb ldr r3, [r7, #12] 80005c6: 3301 adds r3, #1 80005c8: d005 beq.n 80005d6 { wait += (uint32_t)(uwTickFreq); 80005ca: 4b09 ldr r3, [pc, #36] ; (80005f0 ) 80005cc: 781b ldrb r3, [r3, #0] 80005ce: 001a movs r2, r3 80005d0: 68fb ldr r3, [r7, #12] 80005d2: 189b adds r3, r3, r2 80005d4: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 80005d6: 46c0 nop ; (mov r8, r8) 80005d8: f7ff ffe0 bl 800059c 80005dc: 0002 movs r2, r0 80005de: 68bb ldr r3, [r7, #8] 80005e0: 1ad3 subs r3, r2, r3 80005e2: 68fa ldr r2, [r7, #12] 80005e4: 429a cmp r2, r3 80005e6: d8f7 bhi.n 80005d8 { } } 80005e8: 46c0 nop ; (mov r8, r8) 80005ea: 46bd mov sp, r7 80005ec: b004 add sp, #16 80005ee: bd80 pop {r7, pc} 80005f0: 20000008 .word 0x20000008 080005f4 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80005f4: b590 push {r4, r7, lr} 80005f6: b083 sub sp, #12 80005f8: af00 add r7, sp, #0 80005fa: 0002 movs r2, r0 80005fc: 6039 str r1, [r7, #0] 80005fe: 1dfb adds r3, r7, #7 8000600: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 8000602: 1dfb adds r3, r7, #7 8000604: 781b ldrb r3, [r3, #0] 8000606: 2b7f cmp r3, #127 ; 0x7f 8000608: d828 bhi.n 800065c <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 800060a: 4a2f ldr r2, [pc, #188] ; (80006c8 <__NVIC_SetPriority+0xd4>) 800060c: 1dfb adds r3, r7, #7 800060e: 781b ldrb r3, [r3, #0] 8000610: b25b sxtb r3, r3 8000612: 089b lsrs r3, r3, #2 8000614: 33c0 adds r3, #192 ; 0xc0 8000616: 009b lsls r3, r3, #2 8000618: 589b ldr r3, [r3, r2] 800061a: 1dfa adds r2, r7, #7 800061c: 7812 ldrb r2, [r2, #0] 800061e: 0011 movs r1, r2 8000620: 2203 movs r2, #3 8000622: 400a ands r2, r1 8000624: 00d2 lsls r2, r2, #3 8000626: 21ff movs r1, #255 ; 0xff 8000628: 4091 lsls r1, r2 800062a: 000a movs r2, r1 800062c: 43d2 mvns r2, r2 800062e: 401a ands r2, r3 8000630: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8000632: 683b ldr r3, [r7, #0] 8000634: 019b lsls r3, r3, #6 8000636: 22ff movs r2, #255 ; 0xff 8000638: 401a ands r2, r3 800063a: 1dfb adds r3, r7, #7 800063c: 781b ldrb r3, [r3, #0] 800063e: 0018 movs r0, r3 8000640: 2303 movs r3, #3 8000642: 4003 ands r3, r0 8000644: 00db lsls r3, r3, #3 8000646: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8000648: 481f ldr r0, [pc, #124] ; (80006c8 <__NVIC_SetPriority+0xd4>) 800064a: 1dfb adds r3, r7, #7 800064c: 781b ldrb r3, [r3, #0] 800064e: b25b sxtb r3, r3 8000650: 089b lsrs r3, r3, #2 8000652: 430a orrs r2, r1 8000654: 33c0 adds r3, #192 ; 0xc0 8000656: 009b lsls r3, r3, #2 8000658: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 800065a: e031 b.n 80006c0 <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 800065c: 4a1b ldr r2, [pc, #108] ; (80006cc <__NVIC_SetPriority+0xd8>) 800065e: 1dfb adds r3, r7, #7 8000660: 781b ldrb r3, [r3, #0] 8000662: 0019 movs r1, r3 8000664: 230f movs r3, #15 8000666: 400b ands r3, r1 8000668: 3b08 subs r3, #8 800066a: 089b lsrs r3, r3, #2 800066c: 3306 adds r3, #6 800066e: 009b lsls r3, r3, #2 8000670: 18d3 adds r3, r2, r3 8000672: 3304 adds r3, #4 8000674: 681b ldr r3, [r3, #0] 8000676: 1dfa adds r2, r7, #7 8000678: 7812 ldrb r2, [r2, #0] 800067a: 0011 movs r1, r2 800067c: 2203 movs r2, #3 800067e: 400a ands r2, r1 8000680: 00d2 lsls r2, r2, #3 8000682: 21ff movs r1, #255 ; 0xff 8000684: 4091 lsls r1, r2 8000686: 000a movs r2, r1 8000688: 43d2 mvns r2, r2 800068a: 401a ands r2, r3 800068c: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 800068e: 683b ldr r3, [r7, #0] 8000690: 019b lsls r3, r3, #6 8000692: 22ff movs r2, #255 ; 0xff 8000694: 401a ands r2, r3 8000696: 1dfb adds r3, r7, #7 8000698: 781b ldrb r3, [r3, #0] 800069a: 0018 movs r0, r3 800069c: 2303 movs r3, #3 800069e: 4003 ands r3, r0 80006a0: 00db lsls r3, r3, #3 80006a2: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80006a4: 4809 ldr r0, [pc, #36] ; (80006cc <__NVIC_SetPriority+0xd8>) 80006a6: 1dfb adds r3, r7, #7 80006a8: 781b ldrb r3, [r3, #0] 80006aa: 001c movs r4, r3 80006ac: 230f movs r3, #15 80006ae: 4023 ands r3, r4 80006b0: 3b08 subs r3, #8 80006b2: 089b lsrs r3, r3, #2 80006b4: 430a orrs r2, r1 80006b6: 3306 adds r3, #6 80006b8: 009b lsls r3, r3, #2 80006ba: 18c3 adds r3, r0, r3 80006bc: 3304 adds r3, #4 80006be: 601a str r2, [r3, #0] } 80006c0: 46c0 nop ; (mov r8, r8) 80006c2: 46bd mov sp, r7 80006c4: b003 add sp, #12 80006c6: bd90 pop {r4, r7, pc} 80006c8: e000e100 .word 0xe000e100 80006cc: e000ed00 .word 0xe000ed00 080006d0 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80006d0: b580 push {r7, lr} 80006d2: b082 sub sp, #8 80006d4: af00 add r7, sp, #0 80006d6: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80006d8: 687b ldr r3, [r7, #4] 80006da: 3b01 subs r3, #1 80006dc: 4a0c ldr r2, [pc, #48] ; (8000710 ) 80006de: 4293 cmp r3, r2 80006e0: d901 bls.n 80006e6 { return (1UL); /* Reload value impossible */ 80006e2: 2301 movs r3, #1 80006e4: e010 b.n 8000708 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80006e6: 4b0b ldr r3, [pc, #44] ; (8000714 ) 80006e8: 687a ldr r2, [r7, #4] 80006ea: 3a01 subs r2, #1 80006ec: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80006ee: 2301 movs r3, #1 80006f0: 425b negs r3, r3 80006f2: 2103 movs r1, #3 80006f4: 0018 movs r0, r3 80006f6: f7ff ff7d bl 80005f4 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80006fa: 4b06 ldr r3, [pc, #24] ; (8000714 ) 80006fc: 2200 movs r2, #0 80006fe: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000700: 4b04 ldr r3, [pc, #16] ; (8000714 ) 8000702: 2207 movs r2, #7 8000704: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000706: 2300 movs r3, #0 } 8000708: 0018 movs r0, r3 800070a: 46bd mov sp, r7 800070c: b002 add sp, #8 800070e: bd80 pop {r7, pc} 8000710: 00ffffff .word 0x00ffffff 8000714: e000e010 .word 0xe000e010 08000718 : * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000718: b580 push {r7, lr} 800071a: b084 sub sp, #16 800071c: af00 add r7, sp, #0 800071e: 60b9 str r1, [r7, #8] 8000720: 607a str r2, [r7, #4] 8000722: 210f movs r1, #15 8000724: 187b adds r3, r7, r1 8000726: 1c02 adds r2, r0, #0 8000728: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn,PreemptPriority); 800072a: 68ba ldr r2, [r7, #8] 800072c: 187b adds r3, r7, r1 800072e: 781b ldrb r3, [r3, #0] 8000730: b25b sxtb r3, r3 8000732: 0011 movs r1, r2 8000734: 0018 movs r0, r3 8000736: f7ff ff5d bl 80005f4 <__NVIC_SetPriority> } 800073a: 46c0 nop ; (mov r8, r8) 800073c: 46bd mov sp, r7 800073e: b004 add sp, #16 8000740: bd80 pop {r7, pc} 08000742 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8000742: b580 push {r7, lr} 8000744: b082 sub sp, #8 8000746: af00 add r7, sp, #0 8000748: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800074a: 687b ldr r3, [r7, #4] 800074c: 0018 movs r0, r3 800074e: f7ff ffbf bl 80006d0 8000752: 0003 movs r3, r0 } 8000754: 0018 movs r0, r3 8000756: 46bd mov sp, r7 8000758: b002 add sp, #8 800075a: bd80 pop {r7, pc} 0800075c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800075c: b580 push {r7, lr} 800075e: b086 sub sp, #24 8000760: af00 add r7, sp, #0 8000762: 6078 str r0, [r7, #4] 8000764: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8000766: 2300 movs r3, #0 8000768: 617b str r3, [r7, #20] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800076a: e14f b.n 8000a0c { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 800076c: 683b ldr r3, [r7, #0] 800076e: 681b ldr r3, [r3, #0] 8000770: 2101 movs r1, #1 8000772: 697a ldr r2, [r7, #20] 8000774: 4091 lsls r1, r2 8000776: 000a movs r2, r1 8000778: 4013 ands r3, r2 800077a: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 800077c: 68fb ldr r3, [r7, #12] 800077e: 2b00 cmp r3, #0 8000780: d100 bne.n 8000784 8000782: e140 b.n 8000a06 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 8000784: 683b ldr r3, [r7, #0] 8000786: 685b ldr r3, [r3, #4] 8000788: 2b01 cmp r3, #1 800078a: d00b beq.n 80007a4 800078c: 683b ldr r3, [r7, #0] 800078e: 685b ldr r3, [r3, #4] 8000790: 2b02 cmp r3, #2 8000792: d007 beq.n 80007a4 (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 8000794: 683b ldr r3, [r7, #0] 8000796: 685b ldr r3, [r3, #4] if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 8000798: 2b11 cmp r3, #17 800079a: d003 beq.n 80007a4 (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 800079c: 683b ldr r3, [r7, #0] 800079e: 685b ldr r3, [r3, #4] 80007a0: 2b12 cmp r3, #18 80007a2: d130 bne.n 8000806 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 80007a4: 687b ldr r3, [r7, #4] 80007a6: 689b ldr r3, [r3, #8] 80007a8: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); 80007aa: 697b ldr r3, [r7, #20] 80007ac: 005b lsls r3, r3, #1 80007ae: 2203 movs r2, #3 80007b0: 409a lsls r2, r3 80007b2: 0013 movs r3, r2 80007b4: 43da mvns r2, r3 80007b6: 693b ldr r3, [r7, #16] 80007b8: 4013 ands r3, r2 80007ba: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 80007bc: 683b ldr r3, [r7, #0] 80007be: 68da ldr r2, [r3, #12] 80007c0: 697b ldr r3, [r7, #20] 80007c2: 005b lsls r3, r3, #1 80007c4: 409a lsls r2, r3 80007c6: 0013 movs r3, r2 80007c8: 693a ldr r2, [r7, #16] 80007ca: 4313 orrs r3, r2 80007cc: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 80007ce: 687b ldr r3, [r7, #4] 80007d0: 693a ldr r2, [r7, #16] 80007d2: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 80007d4: 687b ldr r3, [r7, #4] 80007d6: 685b ldr r3, [r3, #4] 80007d8: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 80007da: 2201 movs r2, #1 80007dc: 697b ldr r3, [r7, #20] 80007de: 409a lsls r2, r3 80007e0: 0013 movs r3, r2 80007e2: 43da mvns r2, r3 80007e4: 693b ldr r3, [r7, #16] 80007e6: 4013 ands r3, r2 80007e8: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position); 80007ea: 683b ldr r3, [r7, #0] 80007ec: 685b ldr r3, [r3, #4] 80007ee: 091b lsrs r3, r3, #4 80007f0: 2201 movs r2, #1 80007f2: 401a ands r2, r3 80007f4: 697b ldr r3, [r7, #20] 80007f6: 409a lsls r2, r3 80007f8: 0013 movs r3, r2 80007fa: 693a ldr r2, [r7, #16] 80007fc: 4313 orrs r3, r2 80007fe: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8000800: 687b ldr r3, [r7, #4] 8000802: 693a ldr r2, [r7, #16] 8000804: 605a str r2, [r3, #4] } /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8000806: 687b ldr r3, [r7, #4] 8000808: 68db ldr r3, [r3, #12] 800080a: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); 800080c: 697b ldr r3, [r7, #20] 800080e: 005b lsls r3, r3, #1 8000810: 2203 movs r2, #3 8000812: 409a lsls r2, r3 8000814: 0013 movs r3, r2 8000816: 43da mvns r2, r3 8000818: 693b ldr r3, [r7, #16] 800081a: 4013 ands r3, r2 800081c: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 800081e: 683b ldr r3, [r7, #0] 8000820: 689a ldr r2, [r3, #8] 8000822: 697b ldr r3, [r7, #20] 8000824: 005b lsls r3, r3, #1 8000826: 409a lsls r2, r3 8000828: 0013 movs r3, r2 800082a: 693a ldr r2, [r7, #16] 800082c: 4313 orrs r3, r2 800082e: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8000830: 687b ldr r3, [r7, #4] 8000832: 693a ldr r2, [r7, #16] 8000834: 60da str r2, [r3, #12] /* In case of Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 8000836: 683b ldr r3, [r7, #0] 8000838: 685b ldr r3, [r3, #4] 800083a: 2b02 cmp r3, #2 800083c: d003 beq.n 8000846 800083e: 683b ldr r3, [r7, #0] 8000840: 685b ldr r3, [r3, #4] 8000842: 2b12 cmp r3, #18 8000844: d123 bne.n 800088e /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8000846: 697b ldr r3, [r7, #20] 8000848: 08da lsrs r2, r3, #3 800084a: 687b ldr r3, [r7, #4] 800084c: 3208 adds r2, #8 800084e: 0092 lsls r2, r2, #2 8000850: 58d3 ldr r3, [r2, r3] 8000852: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8000854: 697b ldr r3, [r7, #20] 8000856: 2207 movs r2, #7 8000858: 4013 ands r3, r2 800085a: 009b lsls r3, r3, #2 800085c: 220f movs r2, #15 800085e: 409a lsls r2, r3 8000860: 0013 movs r3, r2 8000862: 43da mvns r2, r3 8000864: 693b ldr r3, [r7, #16] 8000866: 4013 ands r3, r2 8000868: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 800086a: 683b ldr r3, [r7, #0] 800086c: 691a ldr r2, [r3, #16] 800086e: 697b ldr r3, [r7, #20] 8000870: 2107 movs r1, #7 8000872: 400b ands r3, r1 8000874: 009b lsls r3, r3, #2 8000876: 409a lsls r2, r3 8000878: 0013 movs r3, r2 800087a: 693a ldr r2, [r7, #16] 800087c: 4313 orrs r3, r2 800087e: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8000880: 697b ldr r3, [r7, #20] 8000882: 08da lsrs r2, r3, #3 8000884: 687b ldr r3, [r7, #4] 8000886: 3208 adds r2, #8 8000888: 0092 lsls r2, r2, #2 800088a: 6939 ldr r1, [r7, #16] 800088c: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800088e: 687b ldr r3, [r7, #4] 8000890: 681b ldr r3, [r3, #0] 8000892: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8000894: 697b ldr r3, [r7, #20] 8000896: 005b lsls r3, r3, #1 8000898: 2203 movs r2, #3 800089a: 409a lsls r2, r3 800089c: 0013 movs r3, r2 800089e: 43da mvns r2, r3 80008a0: 693b ldr r3, [r7, #16] 80008a2: 4013 ands r3, r2 80008a4: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 80008a6: 683b ldr r3, [r7, #0] 80008a8: 685b ldr r3, [r3, #4] 80008aa: 2203 movs r2, #3 80008ac: 401a ands r2, r3 80008ae: 697b ldr r3, [r7, #20] 80008b0: 005b lsls r3, r3, #1 80008b2: 409a lsls r2, r3 80008b4: 0013 movs r3, r2 80008b6: 693a ldr r2, [r7, #16] 80008b8: 4313 orrs r3, r2 80008ba: 613b str r3, [r7, #16] GPIOx->MODER = temp; 80008bc: 687b ldr r3, [r7, #4] 80008be: 693a ldr r2, [r7, #16] 80008c0: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 80008c2: 683b ldr r3, [r7, #0] 80008c4: 685a ldr r2, [r3, #4] 80008c6: 2380 movs r3, #128 ; 0x80 80008c8: 055b lsls r3, r3, #21 80008ca: 4013 ands r3, r2 80008cc: d100 bne.n 80008d0 80008ce: e09a b.n 8000a06 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80008d0: 4b54 ldr r3, [pc, #336] ; (8000a24 ) 80008d2: 699a ldr r2, [r3, #24] 80008d4: 4b53 ldr r3, [pc, #332] ; (8000a24 ) 80008d6: 2101 movs r1, #1 80008d8: 430a orrs r2, r1 80008da: 619a str r2, [r3, #24] 80008dc: 4b51 ldr r3, [pc, #324] ; (8000a24 ) 80008de: 699b ldr r3, [r3, #24] 80008e0: 2201 movs r2, #1 80008e2: 4013 ands r3, r2 80008e4: 60bb str r3, [r7, #8] 80008e6: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; 80008e8: 4a4f ldr r2, [pc, #316] ; (8000a28 ) 80008ea: 697b ldr r3, [r7, #20] 80008ec: 089b lsrs r3, r3, #2 80008ee: 3302 adds r3, #2 80008f0: 009b lsls r3, r3, #2 80008f2: 589b ldr r3, [r3, r2] 80008f4: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 80008f6: 697b ldr r3, [r7, #20] 80008f8: 2203 movs r2, #3 80008fa: 4013 ands r3, r2 80008fc: 009b lsls r3, r3, #2 80008fe: 220f movs r2, #15 8000900: 409a lsls r2, r3 8000902: 0013 movs r3, r2 8000904: 43da mvns r2, r3 8000906: 693b ldr r3, [r7, #16] 8000908: 4013 ands r3, r2 800090a: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 800090c: 687a ldr r2, [r7, #4] 800090e: 2390 movs r3, #144 ; 0x90 8000910: 05db lsls r3, r3, #23 8000912: 429a cmp r2, r3 8000914: d013 beq.n 800093e 8000916: 687b ldr r3, [r7, #4] 8000918: 4a44 ldr r2, [pc, #272] ; (8000a2c ) 800091a: 4293 cmp r3, r2 800091c: d00d beq.n 800093a 800091e: 687b ldr r3, [r7, #4] 8000920: 4a43 ldr r2, [pc, #268] ; (8000a30 ) 8000922: 4293 cmp r3, r2 8000924: d007 beq.n 8000936 8000926: 687b ldr r3, [r7, #4] 8000928: 4a42 ldr r2, [pc, #264] ; (8000a34 ) 800092a: 4293 cmp r3, r2 800092c: d101 bne.n 8000932 800092e: 2303 movs r3, #3 8000930: e006 b.n 8000940 8000932: 2305 movs r3, #5 8000934: e004 b.n 8000940 8000936: 2302 movs r3, #2 8000938: e002 b.n 8000940 800093a: 2301 movs r3, #1 800093c: e000 b.n 8000940 800093e: 2300 movs r3, #0 8000940: 697a ldr r2, [r7, #20] 8000942: 2103 movs r1, #3 8000944: 400a ands r2, r1 8000946: 0092 lsls r2, r2, #2 8000948: 4093 lsls r3, r2 800094a: 693a ldr r2, [r7, #16] 800094c: 4313 orrs r3, r2 800094e: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 8000950: 4935 ldr r1, [pc, #212] ; (8000a28 ) 8000952: 697b ldr r3, [r7, #20] 8000954: 089b lsrs r3, r3, #2 8000956: 3302 adds r3, #2 8000958: 009b lsls r3, r3, #2 800095a: 693a ldr r2, [r7, #16] 800095c: 505a str r2, [r3, r1] /* Clear EXTI line configuration */ temp = EXTI->IMR; 800095e: 4b36 ldr r3, [pc, #216] ; (8000a38 ) 8000960: 681b ldr r3, [r3, #0] 8000962: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8000964: 68fb ldr r3, [r7, #12] 8000966: 43da mvns r2, r3 8000968: 693b ldr r3, [r7, #16] 800096a: 4013 ands r3, r2 800096c: 613b str r3, [r7, #16] if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 800096e: 683b ldr r3, [r7, #0] 8000970: 685a ldr r2, [r3, #4] 8000972: 2380 movs r3, #128 ; 0x80 8000974: 025b lsls r3, r3, #9 8000976: 4013 ands r3, r2 8000978: d003 beq.n 8000982 { temp |= iocurrent; 800097a: 693a ldr r2, [r7, #16] 800097c: 68fb ldr r3, [r7, #12] 800097e: 4313 orrs r3, r2 8000980: 613b str r3, [r7, #16] } EXTI->IMR = temp; 8000982: 4b2d ldr r3, [pc, #180] ; (8000a38 ) 8000984: 693a ldr r2, [r7, #16] 8000986: 601a str r2, [r3, #0] temp = EXTI->EMR; 8000988: 4b2b ldr r3, [pc, #172] ; (8000a38 ) 800098a: 685b ldr r3, [r3, #4] 800098c: 613b str r3, [r7, #16] temp &= ~(iocurrent); 800098e: 68fb ldr r3, [r7, #12] 8000990: 43da mvns r2, r3 8000992: 693b ldr r3, [r7, #16] 8000994: 4013 ands r3, r2 8000996: 613b str r3, [r7, #16] if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8000998: 683b ldr r3, [r7, #0] 800099a: 685a ldr r2, [r3, #4] 800099c: 2380 movs r3, #128 ; 0x80 800099e: 029b lsls r3, r3, #10 80009a0: 4013 ands r3, r2 80009a2: d003 beq.n 80009ac { temp |= iocurrent; 80009a4: 693a ldr r2, [r7, #16] 80009a6: 68fb ldr r3, [r7, #12] 80009a8: 4313 orrs r3, r2 80009aa: 613b str r3, [r7, #16] } EXTI->EMR = temp; 80009ac: 4b22 ldr r3, [pc, #136] ; (8000a38 ) 80009ae: 693a ldr r2, [r7, #16] 80009b0: 605a str r2, [r3, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 80009b2: 4b21 ldr r3, [pc, #132] ; (8000a38 ) 80009b4: 689b ldr r3, [r3, #8] 80009b6: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80009b8: 68fb ldr r3, [r7, #12] 80009ba: 43da mvns r2, r3 80009bc: 693b ldr r3, [r7, #16] 80009be: 4013 ands r3, r2 80009c0: 613b str r3, [r7, #16] if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 80009c2: 683b ldr r3, [r7, #0] 80009c4: 685a ldr r2, [r3, #4] 80009c6: 2380 movs r3, #128 ; 0x80 80009c8: 035b lsls r3, r3, #13 80009ca: 4013 ands r3, r2 80009cc: d003 beq.n 80009d6 { temp |= iocurrent; 80009ce: 693a ldr r2, [r7, #16] 80009d0: 68fb ldr r3, [r7, #12] 80009d2: 4313 orrs r3, r2 80009d4: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 80009d6: 4b18 ldr r3, [pc, #96] ; (8000a38 ) 80009d8: 693a ldr r2, [r7, #16] 80009da: 609a str r2, [r3, #8] temp = EXTI->FTSR; 80009dc: 4b16 ldr r3, [pc, #88] ; (8000a38 ) 80009de: 68db ldr r3, [r3, #12] 80009e0: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80009e2: 68fb ldr r3, [r7, #12] 80009e4: 43da mvns r2, r3 80009e6: 693b ldr r3, [r7, #16] 80009e8: 4013 ands r3, r2 80009ea: 613b str r3, [r7, #16] if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 80009ec: 683b ldr r3, [r7, #0] 80009ee: 685a ldr r2, [r3, #4] 80009f0: 2380 movs r3, #128 ; 0x80 80009f2: 039b lsls r3, r3, #14 80009f4: 4013 ands r3, r2 80009f6: d003 beq.n 8000a00 { temp |= iocurrent; 80009f8: 693a ldr r2, [r7, #16] 80009fa: 68fb ldr r3, [r7, #12] 80009fc: 4313 orrs r3, r2 80009fe: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 8000a00: 4b0d ldr r3, [pc, #52] ; (8000a38 ) 8000a02: 693a ldr r2, [r7, #16] 8000a04: 60da str r2, [r3, #12] } } position++; 8000a06: 697b ldr r3, [r7, #20] 8000a08: 3301 adds r3, #1 8000a0a: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 8000a0c: 683b ldr r3, [r7, #0] 8000a0e: 681a ldr r2, [r3, #0] 8000a10: 697b ldr r3, [r7, #20] 8000a12: 40da lsrs r2, r3 8000a14: 1e13 subs r3, r2, #0 8000a16: d000 beq.n 8000a1a 8000a18: e6a8 b.n 800076c } } 8000a1a: 46c0 nop ; (mov r8, r8) 8000a1c: 46bd mov sp, r7 8000a1e: b006 add sp, #24 8000a20: bd80 pop {r7, pc} 8000a22: 46c0 nop ; (mov r8, r8) 8000a24: 40021000 .word 0x40021000 8000a28: 40010000 .word 0x40010000 8000a2c: 48000400 .word 0x48000400 8000a30: 48000800 .word 0x48000800 8000a34: 48000c00 .word 0x48000c00 8000a38: 40010400 .word 0x40010400 08000a3c : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8000a3c: b580 push {r7, lr} 8000a3e: b084 sub sp, #16 8000a40: af00 add r7, sp, #0 8000a42: 6078 str r0, [r7, #4] 8000a44: 000a movs r2, r1 8000a46: 1cbb adds r3, r7, #2 8000a48: 801a strh r2, [r3, #0] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8000a4a: 687b ldr r3, [r7, #4] 8000a4c: 691b ldr r3, [r3, #16] 8000a4e: 1cba adds r2, r7, #2 8000a50: 8812 ldrh r2, [r2, #0] 8000a52: 4013 ands r3, r2 8000a54: d004 beq.n 8000a60 { bitstatus = GPIO_PIN_SET; 8000a56: 230f movs r3, #15 8000a58: 18fb adds r3, r7, r3 8000a5a: 2201 movs r2, #1 8000a5c: 701a strb r2, [r3, #0] 8000a5e: e003 b.n 8000a68 } else { bitstatus = GPIO_PIN_RESET; 8000a60: 230f movs r3, #15 8000a62: 18fb adds r3, r7, r3 8000a64: 2200 movs r2, #0 8000a66: 701a strb r2, [r3, #0] } return bitstatus; 8000a68: 230f movs r3, #15 8000a6a: 18fb adds r3, r7, r3 8000a6c: 781b ldrb r3, [r3, #0] } 8000a6e: 0018 movs r0, r3 8000a70: 46bd mov sp, r7 8000a72: b004 add sp, #16 8000a74: bd80 pop {r7, pc} 08000a76 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8000a76: b580 push {r7, lr} 8000a78: b082 sub sp, #8 8000a7a: af00 add r7, sp, #0 8000a7c: 6078 str r0, [r7, #4] 8000a7e: 0008 movs r0, r1 8000a80: 0011 movs r1, r2 8000a82: 1cbb adds r3, r7, #2 8000a84: 1c02 adds r2, r0, #0 8000a86: 801a strh r2, [r3, #0] 8000a88: 1c7b adds r3, r7, #1 8000a8a: 1c0a adds r2, r1, #0 8000a8c: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8000a8e: 1c7b adds r3, r7, #1 8000a90: 781b ldrb r3, [r3, #0] 8000a92: 2b00 cmp r3, #0 8000a94: d004 beq.n 8000aa0 { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8000a96: 1cbb adds r3, r7, #2 8000a98: 881a ldrh r2, [r3, #0] 8000a9a: 687b ldr r3, [r7, #4] 8000a9c: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 8000a9e: e003 b.n 8000aa8 GPIOx->BRR = (uint32_t)GPIO_Pin; 8000aa0: 1cbb adds r3, r7, #2 8000aa2: 881a ldrh r2, [r3, #0] 8000aa4: 687b ldr r3, [r7, #4] 8000aa6: 629a str r2, [r3, #40] ; 0x28 } 8000aa8: 46c0 nop ; (mov r8, r8) 8000aaa: 46bd mov sp, r7 8000aac: b002 add sp, #8 8000aae: bd80 pop {r7, pc} 08000ab0 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000ab0: b580 push {r7, lr} 8000ab2: b088 sub sp, #32 8000ab4: af00 add r7, sp, #0 8000ab6: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; uint32_t pll_config2; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8000ab8: 687b ldr r3, [r7, #4] 8000aba: 2b00 cmp r3, #0 8000abc: d101 bne.n 8000ac2 { return HAL_ERROR; 8000abe: 2301 movs r3, #1 8000ac0: e303 b.n 80010ca /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000ac2: 687b ldr r3, [r7, #4] 8000ac4: 681b ldr r3, [r3, #0] 8000ac6: 2201 movs r2, #1 8000ac8: 4013 ands r3, r2 8000aca: d100 bne.n 8000ace 8000acc: e08d b.n 8000bea { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8000ace: 4bc4 ldr r3, [pc, #784] ; (8000de0 ) 8000ad0: 685b ldr r3, [r3, #4] 8000ad2: 220c movs r2, #12 8000ad4: 4013 ands r3, r2 8000ad6: 2b04 cmp r3, #4 8000ad8: d00e beq.n 8000af8 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8000ada: 4bc1 ldr r3, [pc, #772] ; (8000de0 ) 8000adc: 685b ldr r3, [r3, #4] 8000ade: 220c movs r2, #12 8000ae0: 4013 ands r3, r2 8000ae2: 2b08 cmp r3, #8 8000ae4: d116 bne.n 8000b14 8000ae6: 4bbe ldr r3, [pc, #760] ; (8000de0 ) 8000ae8: 685a ldr r2, [r3, #4] 8000aea: 2380 movs r3, #128 ; 0x80 8000aec: 025b lsls r3, r3, #9 8000aee: 401a ands r2, r3 8000af0: 2380 movs r3, #128 ; 0x80 8000af2: 025b lsls r3, r3, #9 8000af4: 429a cmp r2, r3 8000af6: d10d bne.n 8000b14 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000af8: 4bb9 ldr r3, [pc, #740] ; (8000de0 ) 8000afa: 681a ldr r2, [r3, #0] 8000afc: 2380 movs r3, #128 ; 0x80 8000afe: 029b lsls r3, r3, #10 8000b00: 4013 ands r3, r2 8000b02: d100 bne.n 8000b06 8000b04: e070 b.n 8000be8 8000b06: 687b ldr r3, [r7, #4] 8000b08: 685b ldr r3, [r3, #4] 8000b0a: 2b00 cmp r3, #0 8000b0c: d000 beq.n 8000b10 8000b0e: e06b b.n 8000be8 { return HAL_ERROR; 8000b10: 2301 movs r3, #1 8000b12: e2da b.n 80010ca } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000b14: 687b ldr r3, [r7, #4] 8000b16: 685b ldr r3, [r3, #4] 8000b18: 2b01 cmp r3, #1 8000b1a: d107 bne.n 8000b2c 8000b1c: 4bb0 ldr r3, [pc, #704] ; (8000de0 ) 8000b1e: 681a ldr r2, [r3, #0] 8000b20: 4baf ldr r3, [pc, #700] ; (8000de0 ) 8000b22: 2180 movs r1, #128 ; 0x80 8000b24: 0249 lsls r1, r1, #9 8000b26: 430a orrs r2, r1 8000b28: 601a str r2, [r3, #0] 8000b2a: e02f b.n 8000b8c 8000b2c: 687b ldr r3, [r7, #4] 8000b2e: 685b ldr r3, [r3, #4] 8000b30: 2b00 cmp r3, #0 8000b32: d10c bne.n 8000b4e 8000b34: 4baa ldr r3, [pc, #680] ; (8000de0 ) 8000b36: 681a ldr r2, [r3, #0] 8000b38: 4ba9 ldr r3, [pc, #676] ; (8000de0 ) 8000b3a: 49aa ldr r1, [pc, #680] ; (8000de4 ) 8000b3c: 400a ands r2, r1 8000b3e: 601a str r2, [r3, #0] 8000b40: 4ba7 ldr r3, [pc, #668] ; (8000de0 ) 8000b42: 681a ldr r2, [r3, #0] 8000b44: 4ba6 ldr r3, [pc, #664] ; (8000de0 ) 8000b46: 49a8 ldr r1, [pc, #672] ; (8000de8 ) 8000b48: 400a ands r2, r1 8000b4a: 601a str r2, [r3, #0] 8000b4c: e01e b.n 8000b8c 8000b4e: 687b ldr r3, [r7, #4] 8000b50: 685b ldr r3, [r3, #4] 8000b52: 2b05 cmp r3, #5 8000b54: d10e bne.n 8000b74 8000b56: 4ba2 ldr r3, [pc, #648] ; (8000de0 ) 8000b58: 681a ldr r2, [r3, #0] 8000b5a: 4ba1 ldr r3, [pc, #644] ; (8000de0 ) 8000b5c: 2180 movs r1, #128 ; 0x80 8000b5e: 02c9 lsls r1, r1, #11 8000b60: 430a orrs r2, r1 8000b62: 601a str r2, [r3, #0] 8000b64: 4b9e ldr r3, [pc, #632] ; (8000de0 ) 8000b66: 681a ldr r2, [r3, #0] 8000b68: 4b9d ldr r3, [pc, #628] ; (8000de0 ) 8000b6a: 2180 movs r1, #128 ; 0x80 8000b6c: 0249 lsls r1, r1, #9 8000b6e: 430a orrs r2, r1 8000b70: 601a str r2, [r3, #0] 8000b72: e00b b.n 8000b8c 8000b74: 4b9a ldr r3, [pc, #616] ; (8000de0 ) 8000b76: 681a ldr r2, [r3, #0] 8000b78: 4b99 ldr r3, [pc, #612] ; (8000de0 ) 8000b7a: 499a ldr r1, [pc, #616] ; (8000de4 ) 8000b7c: 400a ands r2, r1 8000b7e: 601a str r2, [r3, #0] 8000b80: 4b97 ldr r3, [pc, #604] ; (8000de0 ) 8000b82: 681a ldr r2, [r3, #0] 8000b84: 4b96 ldr r3, [pc, #600] ; (8000de0 ) 8000b86: 4998 ldr r1, [pc, #608] ; (8000de8 ) 8000b88: 400a ands r2, r1 8000b8a: 601a str r2, [r3, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8000b8c: 687b ldr r3, [r7, #4] 8000b8e: 685b ldr r3, [r3, #4] 8000b90: 2b00 cmp r3, #0 8000b92: d014 beq.n 8000bbe { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000b94: f7ff fd02 bl 800059c 8000b98: 0003 movs r3, r0 8000b9a: 61bb str r3, [r7, #24] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000b9c: e008 b.n 8000bb0 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8000b9e: f7ff fcfd bl 800059c 8000ba2: 0002 movs r2, r0 8000ba4: 69bb ldr r3, [r7, #24] 8000ba6: 1ad3 subs r3, r2, r3 8000ba8: 2b64 cmp r3, #100 ; 0x64 8000baa: d901 bls.n 8000bb0 { return HAL_TIMEOUT; 8000bac: 2303 movs r3, #3 8000bae: e28c b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000bb0: 4b8b ldr r3, [pc, #556] ; (8000de0 ) 8000bb2: 681a ldr r2, [r3, #0] 8000bb4: 2380 movs r3, #128 ; 0x80 8000bb6: 029b lsls r3, r3, #10 8000bb8: 4013 ands r3, r2 8000bba: d0f0 beq.n 8000b9e 8000bbc: e015 b.n 8000bea } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000bbe: f7ff fced bl 800059c 8000bc2: 0003 movs r3, r0 8000bc4: 61bb str r3, [r7, #24] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000bc6: e008 b.n 8000bda { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8000bc8: f7ff fce8 bl 800059c 8000bcc: 0002 movs r2, r0 8000bce: 69bb ldr r3, [r7, #24] 8000bd0: 1ad3 subs r3, r2, r3 8000bd2: 2b64 cmp r3, #100 ; 0x64 8000bd4: d901 bls.n 8000bda { return HAL_TIMEOUT; 8000bd6: 2303 movs r3, #3 8000bd8: e277 b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000bda: 4b81 ldr r3, [pc, #516] ; (8000de0 ) 8000bdc: 681a ldr r2, [r3, #0] 8000bde: 2380 movs r3, #128 ; 0x80 8000be0: 029b lsls r3, r3, #10 8000be2: 4013 ands r3, r2 8000be4: d1f0 bne.n 8000bc8 8000be6: e000 b.n 8000bea if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000be8: 46c0 nop ; (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000bea: 687b ldr r3, [r7, #4] 8000bec: 681b ldr r3, [r3, #0] 8000bee: 2202 movs r2, #2 8000bf0: 4013 ands r3, r2 8000bf2: d100 bne.n 8000bf6 8000bf4: e069 b.n 8000cca /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8000bf6: 4b7a ldr r3, [pc, #488] ; (8000de0 ) 8000bf8: 685b ldr r3, [r3, #4] 8000bfa: 220c movs r2, #12 8000bfc: 4013 ands r3, r2 8000bfe: d00b beq.n 8000c18 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 8000c00: 4b77 ldr r3, [pc, #476] ; (8000de0 ) 8000c02: 685b ldr r3, [r3, #4] 8000c04: 220c movs r2, #12 8000c06: 4013 ands r3, r2 8000c08: 2b08 cmp r3, #8 8000c0a: d11c bne.n 8000c46 8000c0c: 4b74 ldr r3, [pc, #464] ; (8000de0 ) 8000c0e: 685a ldr r2, [r3, #4] 8000c10: 2380 movs r3, #128 ; 0x80 8000c12: 025b lsls r3, r3, #9 8000c14: 4013 ands r3, r2 8000c16: d116 bne.n 8000c46 { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000c18: 4b71 ldr r3, [pc, #452] ; (8000de0 ) 8000c1a: 681b ldr r3, [r3, #0] 8000c1c: 2202 movs r2, #2 8000c1e: 4013 ands r3, r2 8000c20: d005 beq.n 8000c2e 8000c22: 687b ldr r3, [r7, #4] 8000c24: 68db ldr r3, [r3, #12] 8000c26: 2b01 cmp r3, #1 8000c28: d001 beq.n 8000c2e { return HAL_ERROR; 8000c2a: 2301 movs r3, #1 8000c2c: e24d b.n 80010ca } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000c2e: 4b6c ldr r3, [pc, #432] ; (8000de0 ) 8000c30: 681b ldr r3, [r3, #0] 8000c32: 22f8 movs r2, #248 ; 0xf8 8000c34: 4393 bics r3, r2 8000c36: 0019 movs r1, r3 8000c38: 687b ldr r3, [r7, #4] 8000c3a: 691b ldr r3, [r3, #16] 8000c3c: 00da lsls r2, r3, #3 8000c3e: 4b68 ldr r3, [pc, #416] ; (8000de0 ) 8000c40: 430a orrs r2, r1 8000c42: 601a str r2, [r3, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000c44: e041 b.n 8000cca } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8000c46: 687b ldr r3, [r7, #4] 8000c48: 68db ldr r3, [r3, #12] 8000c4a: 2b00 cmp r3, #0 8000c4c: d024 beq.n 8000c98 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8000c4e: 4b64 ldr r3, [pc, #400] ; (8000de0 ) 8000c50: 681a ldr r2, [r3, #0] 8000c52: 4b63 ldr r3, [pc, #396] ; (8000de0 ) 8000c54: 2101 movs r1, #1 8000c56: 430a orrs r2, r1 8000c58: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000c5a: f7ff fc9f bl 800059c 8000c5e: 0003 movs r3, r0 8000c60: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000c62: e008 b.n 8000c76 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8000c64: f7ff fc9a bl 800059c 8000c68: 0002 movs r2, r0 8000c6a: 69bb ldr r3, [r7, #24] 8000c6c: 1ad3 subs r3, r2, r3 8000c6e: 2b02 cmp r3, #2 8000c70: d901 bls.n 8000c76 { return HAL_TIMEOUT; 8000c72: 2303 movs r3, #3 8000c74: e229 b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000c76: 4b5a ldr r3, [pc, #360] ; (8000de0 ) 8000c78: 681b ldr r3, [r3, #0] 8000c7a: 2202 movs r2, #2 8000c7c: 4013 ands r3, r2 8000c7e: d0f1 beq.n 8000c64 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000c80: 4b57 ldr r3, [pc, #348] ; (8000de0 ) 8000c82: 681b ldr r3, [r3, #0] 8000c84: 22f8 movs r2, #248 ; 0xf8 8000c86: 4393 bics r3, r2 8000c88: 0019 movs r1, r3 8000c8a: 687b ldr r3, [r7, #4] 8000c8c: 691b ldr r3, [r3, #16] 8000c8e: 00da lsls r2, r3, #3 8000c90: 4b53 ldr r3, [pc, #332] ; (8000de0 ) 8000c92: 430a orrs r2, r1 8000c94: 601a str r2, [r3, #0] 8000c96: e018 b.n 8000cca } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8000c98: 4b51 ldr r3, [pc, #324] ; (8000de0 ) 8000c9a: 681a ldr r2, [r3, #0] 8000c9c: 4b50 ldr r3, [pc, #320] ; (8000de0 ) 8000c9e: 2101 movs r1, #1 8000ca0: 438a bics r2, r1 8000ca2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000ca4: f7ff fc7a bl 800059c 8000ca8: 0003 movs r3, r0 8000caa: 61bb str r3, [r7, #24] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000cac: e008 b.n 8000cc0 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8000cae: f7ff fc75 bl 800059c 8000cb2: 0002 movs r2, r0 8000cb4: 69bb ldr r3, [r7, #24] 8000cb6: 1ad3 subs r3, r2, r3 8000cb8: 2b02 cmp r3, #2 8000cba: d901 bls.n 8000cc0 { return HAL_TIMEOUT; 8000cbc: 2303 movs r3, #3 8000cbe: e204 b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000cc0: 4b47 ldr r3, [pc, #284] ; (8000de0 ) 8000cc2: 681b ldr r3, [r3, #0] 8000cc4: 2202 movs r2, #2 8000cc6: 4013 ands r3, r2 8000cc8: d1f1 bne.n 8000cae } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8000cca: 687b ldr r3, [r7, #4] 8000ccc: 681b ldr r3, [r3, #0] 8000cce: 2208 movs r2, #8 8000cd0: 4013 ands r3, r2 8000cd2: d036 beq.n 8000d42 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8000cd4: 687b ldr r3, [r7, #4] 8000cd6: 69db ldr r3, [r3, #28] 8000cd8: 2b00 cmp r3, #0 8000cda: d019 beq.n 8000d10 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8000cdc: 4b40 ldr r3, [pc, #256] ; (8000de0 ) 8000cde: 6a5a ldr r2, [r3, #36] ; 0x24 8000ce0: 4b3f ldr r3, [pc, #252] ; (8000de0 ) 8000ce2: 2101 movs r1, #1 8000ce4: 430a orrs r2, r1 8000ce6: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8000ce8: f7ff fc58 bl 800059c 8000cec: 0003 movs r3, r0 8000cee: 61bb str r3, [r7, #24] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000cf0: e008 b.n 8000d04 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8000cf2: f7ff fc53 bl 800059c 8000cf6: 0002 movs r2, r0 8000cf8: 69bb ldr r3, [r7, #24] 8000cfa: 1ad3 subs r3, r2, r3 8000cfc: 2b02 cmp r3, #2 8000cfe: d901 bls.n 8000d04 { return HAL_TIMEOUT; 8000d00: 2303 movs r3, #3 8000d02: e1e2 b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000d04: 4b36 ldr r3, [pc, #216] ; (8000de0 ) 8000d06: 6a5b ldr r3, [r3, #36] ; 0x24 8000d08: 2202 movs r2, #2 8000d0a: 4013 ands r3, r2 8000d0c: d0f1 beq.n 8000cf2 8000d0e: e018 b.n 8000d42 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8000d10: 4b33 ldr r3, [pc, #204] ; (8000de0 ) 8000d12: 6a5a ldr r2, [r3, #36] ; 0x24 8000d14: 4b32 ldr r3, [pc, #200] ; (8000de0 ) 8000d16: 2101 movs r1, #1 8000d18: 438a bics r2, r1 8000d1a: 625a str r2, [r3, #36] ; 0x24 /* Get Start Tick */ tickstart = HAL_GetTick(); 8000d1c: f7ff fc3e bl 800059c 8000d20: 0003 movs r3, r0 8000d22: 61bb str r3, [r7, #24] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000d24: e008 b.n 8000d38 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8000d26: f7ff fc39 bl 800059c 8000d2a: 0002 movs r2, r0 8000d2c: 69bb ldr r3, [r7, #24] 8000d2e: 1ad3 subs r3, r2, r3 8000d30: 2b02 cmp r3, #2 8000d32: d901 bls.n 8000d38 { return HAL_TIMEOUT; 8000d34: 2303 movs r3, #3 8000d36: e1c8 b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000d38: 4b29 ldr r3, [pc, #164] ; (8000de0 ) 8000d3a: 6a5b ldr r3, [r3, #36] ; 0x24 8000d3c: 2202 movs r2, #2 8000d3e: 4013 ands r3, r2 8000d40: d1f1 bne.n 8000d26 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8000d42: 687b ldr r3, [r7, #4] 8000d44: 681b ldr r3, [r3, #0] 8000d46: 2204 movs r2, #4 8000d48: 4013 ands r3, r2 8000d4a: d100 bne.n 8000d4e 8000d4c: e0b6 b.n 8000ebc { FlagStatus pwrclkchanged = RESET; 8000d4e: 231f movs r3, #31 8000d50: 18fb adds r3, r7, r3 8000d52: 2200 movs r2, #0 8000d54: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8000d56: 4b22 ldr r3, [pc, #136] ; (8000de0 ) 8000d58: 69da ldr r2, [r3, #28] 8000d5a: 2380 movs r3, #128 ; 0x80 8000d5c: 055b lsls r3, r3, #21 8000d5e: 4013 ands r3, r2 8000d60: d111 bne.n 8000d86 { __HAL_RCC_PWR_CLK_ENABLE(); 8000d62: 4b1f ldr r3, [pc, #124] ; (8000de0 ) 8000d64: 69da ldr r2, [r3, #28] 8000d66: 4b1e ldr r3, [pc, #120] ; (8000de0 ) 8000d68: 2180 movs r1, #128 ; 0x80 8000d6a: 0549 lsls r1, r1, #21 8000d6c: 430a orrs r2, r1 8000d6e: 61da str r2, [r3, #28] 8000d70: 4b1b ldr r3, [pc, #108] ; (8000de0 ) 8000d72: 69da ldr r2, [r3, #28] 8000d74: 2380 movs r3, #128 ; 0x80 8000d76: 055b lsls r3, r3, #21 8000d78: 4013 ands r3, r2 8000d7a: 60fb str r3, [r7, #12] 8000d7c: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8000d7e: 231f movs r3, #31 8000d80: 18fb adds r3, r7, r3 8000d82: 2201 movs r2, #1 8000d84: 701a strb r2, [r3, #0] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d86: 4b19 ldr r3, [pc, #100] ; (8000dec ) 8000d88: 681a ldr r2, [r3, #0] 8000d8a: 2380 movs r3, #128 ; 0x80 8000d8c: 005b lsls r3, r3, #1 8000d8e: 4013 ands r3, r2 8000d90: d11a bne.n 8000dc8 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8000d92: 4b16 ldr r3, [pc, #88] ; (8000dec ) 8000d94: 681a ldr r2, [r3, #0] 8000d96: 4b15 ldr r3, [pc, #84] ; (8000dec ) 8000d98: 2180 movs r1, #128 ; 0x80 8000d9a: 0049 lsls r1, r1, #1 8000d9c: 430a orrs r2, r1 8000d9e: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8000da0: f7ff fbfc bl 800059c 8000da4: 0003 movs r3, r0 8000da6: 61bb str r3, [r7, #24] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000da8: e008 b.n 8000dbc { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8000daa: f7ff fbf7 bl 800059c 8000dae: 0002 movs r2, r0 8000db0: 69bb ldr r3, [r7, #24] 8000db2: 1ad3 subs r3, r2, r3 8000db4: 2b64 cmp r3, #100 ; 0x64 8000db6: d901 bls.n 8000dbc { return HAL_TIMEOUT; 8000db8: 2303 movs r3, #3 8000dba: e186 b.n 80010ca while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000dbc: 4b0b ldr r3, [pc, #44] ; (8000dec ) 8000dbe: 681a ldr r2, [r3, #0] 8000dc0: 2380 movs r3, #128 ; 0x80 8000dc2: 005b lsls r3, r3, #1 8000dc4: 4013 ands r3, r2 8000dc6: d0f0 beq.n 8000daa } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8000dc8: 687b ldr r3, [r7, #4] 8000dca: 689b ldr r3, [r3, #8] 8000dcc: 2b01 cmp r3, #1 8000dce: d10f bne.n 8000df0 8000dd0: 4b03 ldr r3, [pc, #12] ; (8000de0 ) 8000dd2: 6a1a ldr r2, [r3, #32] 8000dd4: 4b02 ldr r3, [pc, #8] ; (8000de0 ) 8000dd6: 2101 movs r1, #1 8000dd8: 430a orrs r2, r1 8000dda: 621a str r2, [r3, #32] 8000ddc: e036 b.n 8000e4c 8000dde: 46c0 nop ; (mov r8, r8) 8000de0: 40021000 .word 0x40021000 8000de4: fffeffff .word 0xfffeffff 8000de8: fffbffff .word 0xfffbffff 8000dec: 40007000 .word 0x40007000 8000df0: 687b ldr r3, [r7, #4] 8000df2: 689b ldr r3, [r3, #8] 8000df4: 2b00 cmp r3, #0 8000df6: d10c bne.n 8000e12 8000df8: 4bb6 ldr r3, [pc, #728] ; (80010d4 ) 8000dfa: 6a1a ldr r2, [r3, #32] 8000dfc: 4bb5 ldr r3, [pc, #724] ; (80010d4 ) 8000dfe: 2101 movs r1, #1 8000e00: 438a bics r2, r1 8000e02: 621a str r2, [r3, #32] 8000e04: 4bb3 ldr r3, [pc, #716] ; (80010d4 ) 8000e06: 6a1a ldr r2, [r3, #32] 8000e08: 4bb2 ldr r3, [pc, #712] ; (80010d4 ) 8000e0a: 2104 movs r1, #4 8000e0c: 438a bics r2, r1 8000e0e: 621a str r2, [r3, #32] 8000e10: e01c b.n 8000e4c 8000e12: 687b ldr r3, [r7, #4] 8000e14: 689b ldr r3, [r3, #8] 8000e16: 2b05 cmp r3, #5 8000e18: d10c bne.n 8000e34 8000e1a: 4bae ldr r3, [pc, #696] ; (80010d4 ) 8000e1c: 6a1a ldr r2, [r3, #32] 8000e1e: 4bad ldr r3, [pc, #692] ; (80010d4 ) 8000e20: 2104 movs r1, #4 8000e22: 430a orrs r2, r1 8000e24: 621a str r2, [r3, #32] 8000e26: 4bab ldr r3, [pc, #684] ; (80010d4 ) 8000e28: 6a1a ldr r2, [r3, #32] 8000e2a: 4baa ldr r3, [pc, #680] ; (80010d4 ) 8000e2c: 2101 movs r1, #1 8000e2e: 430a orrs r2, r1 8000e30: 621a str r2, [r3, #32] 8000e32: e00b b.n 8000e4c 8000e34: 4ba7 ldr r3, [pc, #668] ; (80010d4 ) 8000e36: 6a1a ldr r2, [r3, #32] 8000e38: 4ba6 ldr r3, [pc, #664] ; (80010d4 ) 8000e3a: 2101 movs r1, #1 8000e3c: 438a bics r2, r1 8000e3e: 621a str r2, [r3, #32] 8000e40: 4ba4 ldr r3, [pc, #656] ; (80010d4 ) 8000e42: 6a1a ldr r2, [r3, #32] 8000e44: 4ba3 ldr r3, [pc, #652] ; (80010d4 ) 8000e46: 2104 movs r1, #4 8000e48: 438a bics r2, r1 8000e4a: 621a str r2, [r3, #32] /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8000e4c: 687b ldr r3, [r7, #4] 8000e4e: 689b ldr r3, [r3, #8] 8000e50: 2b00 cmp r3, #0 8000e52: d014 beq.n 8000e7e { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e54: f7ff fba2 bl 800059c 8000e58: 0003 movs r3, r0 8000e5a: 61bb str r3, [r7, #24] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8000e5c: e009 b.n 8000e72 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8000e5e: f7ff fb9d bl 800059c 8000e62: 0002 movs r2, r0 8000e64: 69bb ldr r3, [r7, #24] 8000e66: 1ad3 subs r3, r2, r3 8000e68: 4a9b ldr r2, [pc, #620] ; (80010d8 ) 8000e6a: 4293 cmp r3, r2 8000e6c: d901 bls.n 8000e72 { return HAL_TIMEOUT; 8000e6e: 2303 movs r3, #3 8000e70: e12b b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8000e72: 4b98 ldr r3, [pc, #608] ; (80010d4 ) 8000e74: 6a1b ldr r3, [r3, #32] 8000e76: 2202 movs r2, #2 8000e78: 4013 ands r3, r2 8000e7a: d0f0 beq.n 8000e5e 8000e7c: e013 b.n 8000ea6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e7e: f7ff fb8d bl 800059c 8000e82: 0003 movs r3, r0 8000e84: 61bb str r3, [r7, #24] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8000e86: e009 b.n 8000e9c { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8000e88: f7ff fb88 bl 800059c 8000e8c: 0002 movs r2, r0 8000e8e: 69bb ldr r3, [r7, #24] 8000e90: 1ad3 subs r3, r2, r3 8000e92: 4a91 ldr r2, [pc, #580] ; (80010d8 ) 8000e94: 4293 cmp r3, r2 8000e96: d901 bls.n 8000e9c { return HAL_TIMEOUT; 8000e98: 2303 movs r3, #3 8000e9a: e116 b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8000e9c: 4b8d ldr r3, [pc, #564] ; (80010d4 ) 8000e9e: 6a1b ldr r3, [r3, #32] 8000ea0: 2202 movs r2, #2 8000ea2: 4013 ands r3, r2 8000ea4: d1f0 bne.n 8000e88 } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 8000ea6: 231f movs r3, #31 8000ea8: 18fb adds r3, r7, r3 8000eaa: 781b ldrb r3, [r3, #0] 8000eac: 2b01 cmp r3, #1 8000eae: d105 bne.n 8000ebc { __HAL_RCC_PWR_CLK_DISABLE(); 8000eb0: 4b88 ldr r3, [pc, #544] ; (80010d4 ) 8000eb2: 69da ldr r2, [r3, #28] 8000eb4: 4b87 ldr r3, [pc, #540] ; (80010d4 ) 8000eb6: 4989 ldr r1, [pc, #548] ; (80010dc ) 8000eb8: 400a ands r2, r1 8000eba: 61da str r2, [r3, #28] } } /*----------------------------- HSI14 Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) 8000ebc: 687b ldr r3, [r7, #4] 8000ebe: 681b ldr r3, [r3, #0] 8000ec0: 2210 movs r2, #16 8000ec2: 4013 ands r3, r2 8000ec4: d063 beq.n 8000f8e /* Check the parameters */ assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); /* Check the HSI14 State */ if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) 8000ec6: 687b ldr r3, [r7, #4] 8000ec8: 695b ldr r3, [r3, #20] 8000eca: 2b01 cmp r3, #1 8000ecc: d12a bne.n 8000f24 { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8000ece: 4b81 ldr r3, [pc, #516] ; (80010d4 ) 8000ed0: 6b5a ldr r2, [r3, #52] ; 0x34 8000ed2: 4b80 ldr r3, [pc, #512] ; (80010d4 ) 8000ed4: 2104 movs r1, #4 8000ed6: 430a orrs r2, r1 8000ed8: 635a str r2, [r3, #52] ; 0x34 /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_ENABLE(); 8000eda: 4b7e ldr r3, [pc, #504] ; (80010d4 ) 8000edc: 6b5a ldr r2, [r3, #52] ; 0x34 8000ede: 4b7d ldr r3, [pc, #500] ; (80010d4 ) 8000ee0: 2101 movs r1, #1 8000ee2: 430a orrs r2, r1 8000ee4: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8000ee6: f7ff fb59 bl 800059c 8000eea: 0003 movs r3, r0 8000eec: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8000eee: e008 b.n 8000f02 { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8000ef0: f7ff fb54 bl 800059c 8000ef4: 0002 movs r2, r0 8000ef6: 69bb ldr r3, [r7, #24] 8000ef8: 1ad3 subs r3, r2, r3 8000efa: 2b02 cmp r3, #2 8000efc: d901 bls.n 8000f02 { return HAL_TIMEOUT; 8000efe: 2303 movs r3, #3 8000f00: e0e3 b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) 8000f02: 4b74 ldr r3, [pc, #464] ; (80010d4 ) 8000f04: 6b5b ldr r3, [r3, #52] ; 0x34 8000f06: 2202 movs r2, #2 8000f08: 4013 ands r3, r2 8000f0a: d0f1 beq.n 8000ef0 } } /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8000f0c: 4b71 ldr r3, [pc, #452] ; (80010d4 ) 8000f0e: 6b5b ldr r3, [r3, #52] ; 0x34 8000f10: 22f8 movs r2, #248 ; 0xf8 8000f12: 4393 bics r3, r2 8000f14: 0019 movs r1, r3 8000f16: 687b ldr r3, [r7, #4] 8000f18: 699b ldr r3, [r3, #24] 8000f1a: 00da lsls r2, r3, #3 8000f1c: 4b6d ldr r3, [pc, #436] ; (80010d4 ) 8000f1e: 430a orrs r2, r1 8000f20: 635a str r2, [r3, #52] ; 0x34 8000f22: e034 b.n 8000f8e } else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) 8000f24: 687b ldr r3, [r7, #4] 8000f26: 695b ldr r3, [r3, #20] 8000f28: 3305 adds r3, #5 8000f2a: d111 bne.n 8000f50 { /* Enable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_ENABLE(); 8000f2c: 4b69 ldr r3, [pc, #420] ; (80010d4 ) 8000f2e: 6b5a ldr r2, [r3, #52] ; 0x34 8000f30: 4b68 ldr r3, [pc, #416] ; (80010d4 ) 8000f32: 2104 movs r1, #4 8000f34: 438a bics r2, r1 8000f36: 635a str r2, [r3, #52] ; 0x34 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); 8000f38: 4b66 ldr r3, [pc, #408] ; (80010d4 ) 8000f3a: 6b5b ldr r3, [r3, #52] ; 0x34 8000f3c: 22f8 movs r2, #248 ; 0xf8 8000f3e: 4393 bics r3, r2 8000f40: 0019 movs r1, r3 8000f42: 687b ldr r3, [r7, #4] 8000f44: 699b ldr r3, [r3, #24] 8000f46: 00da lsls r2, r3, #3 8000f48: 4b62 ldr r3, [pc, #392] ; (80010d4 ) 8000f4a: 430a orrs r2, r1 8000f4c: 635a str r2, [r3, #52] ; 0x34 8000f4e: e01e b.n 8000f8e } else { /* Disable ADC control of the Internal High Speed oscillator HSI14 */ __HAL_RCC_HSI14ADC_DISABLE(); 8000f50: 4b60 ldr r3, [pc, #384] ; (80010d4 ) 8000f52: 6b5a ldr r2, [r3, #52] ; 0x34 8000f54: 4b5f ldr r3, [pc, #380] ; (80010d4 ) 8000f56: 2104 movs r1, #4 8000f58: 430a orrs r2, r1 8000f5a: 635a str r2, [r3, #52] ; 0x34 /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI14_DISABLE(); 8000f5c: 4b5d ldr r3, [pc, #372] ; (80010d4 ) 8000f5e: 6b5a ldr r2, [r3, #52] ; 0x34 8000f60: 4b5c ldr r3, [pc, #368] ; (80010d4 ) 8000f62: 2101 movs r1, #1 8000f64: 438a bics r2, r1 8000f66: 635a str r2, [r3, #52] ; 0x34 /* Get Start Tick */ tickstart = HAL_GetTick(); 8000f68: f7ff fb18 bl 800059c 8000f6c: 0003 movs r3, r0 8000f6e: 61bb str r3, [r7, #24] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8000f70: e008 b.n 8000f84 { if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) 8000f72: f7ff fb13 bl 800059c 8000f76: 0002 movs r2, r0 8000f78: 69bb ldr r3, [r7, #24] 8000f7a: 1ad3 subs r3, r2, r3 8000f7c: 2b02 cmp r3, #2 8000f7e: d901 bls.n 8000f84 { return HAL_TIMEOUT; 8000f80: 2303 movs r3, #3 8000f82: e0a2 b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) 8000f84: 4b53 ldr r3, [pc, #332] ; (80010d4 ) 8000f86: 6b5b ldr r3, [r3, #52] ; 0x34 8000f88: 2202 movs r2, #2 8000f8a: 4013 ands r3, r2 8000f8c: d1f1 bne.n 8000f72 #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8000f8e: 687b ldr r3, [r7, #4] 8000f90: 6a1b ldr r3, [r3, #32] 8000f92: 2b00 cmp r3, #0 8000f94: d100 bne.n 8000f98 8000f96: e097 b.n 80010c8 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8000f98: 4b4e ldr r3, [pc, #312] ; (80010d4 ) 8000f9a: 685b ldr r3, [r3, #4] 8000f9c: 220c movs r2, #12 8000f9e: 4013 ands r3, r2 8000fa0: 2b08 cmp r3, #8 8000fa2: d100 bne.n 8000fa6 8000fa4: e06b b.n 800107e { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8000fa6: 687b ldr r3, [r7, #4] 8000fa8: 6a1b ldr r3, [r3, #32] 8000faa: 2b02 cmp r3, #2 8000fac: d14c bne.n 8001048 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8000fae: 4b49 ldr r3, [pc, #292] ; (80010d4 ) 8000fb0: 681a ldr r2, [r3, #0] 8000fb2: 4b48 ldr r3, [pc, #288] ; (80010d4 ) 8000fb4: 494a ldr r1, [pc, #296] ; (80010e0 ) 8000fb6: 400a ands r2, r1 8000fb8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000fba: f7ff faef bl 800059c 8000fbe: 0003 movs r3, r0 8000fc0: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000fc2: e008 b.n 8000fd6 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8000fc4: f7ff faea bl 800059c 8000fc8: 0002 movs r2, r0 8000fca: 69bb ldr r3, [r7, #24] 8000fcc: 1ad3 subs r3, r2, r3 8000fce: 2b02 cmp r3, #2 8000fd0: d901 bls.n 8000fd6 { return HAL_TIMEOUT; 8000fd2: 2303 movs r3, #3 8000fd4: e079 b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000fd6: 4b3f ldr r3, [pc, #252] ; (80010d4 ) 8000fd8: 681a ldr r2, [r3, #0] 8000fda: 2380 movs r3, #128 ; 0x80 8000fdc: 049b lsls r3, r3, #18 8000fde: 4013 ands r3, r2 8000fe0: d1f0 bne.n 8000fc4 } } /* Configure the main PLL clock source, predivider and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8000fe2: 4b3c ldr r3, [pc, #240] ; (80010d4 ) 8000fe4: 6adb ldr r3, [r3, #44] ; 0x2c 8000fe6: 220f movs r2, #15 8000fe8: 4393 bics r3, r2 8000fea: 0019 movs r1, r3 8000fec: 687b ldr r3, [r7, #4] 8000fee: 6ada ldr r2, [r3, #44] ; 0x2c 8000ff0: 4b38 ldr r3, [pc, #224] ; (80010d4 ) 8000ff2: 430a orrs r2, r1 8000ff4: 62da str r2, [r3, #44] ; 0x2c 8000ff6: 4b37 ldr r3, [pc, #220] ; (80010d4 ) 8000ff8: 685b ldr r3, [r3, #4] 8000ffa: 4a3a ldr r2, [pc, #232] ; (80010e4 ) 8000ffc: 4013 ands r3, r2 8000ffe: 0019 movs r1, r3 8001000: 687b ldr r3, [r7, #4] 8001002: 6a9a ldr r2, [r3, #40] ; 0x28 8001004: 687b ldr r3, [r7, #4] 8001006: 6a5b ldr r3, [r3, #36] ; 0x24 8001008: 431a orrs r2, r3 800100a: 4b32 ldr r3, [pc, #200] ; (80010d4 ) 800100c: 430a orrs r2, r1 800100e: 605a str r2, [r3, #4] RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8001010: 4b30 ldr r3, [pc, #192] ; (80010d4 ) 8001012: 681a ldr r2, [r3, #0] 8001014: 4b2f ldr r3, [pc, #188] ; (80010d4 ) 8001016: 2180 movs r1, #128 ; 0x80 8001018: 0449 lsls r1, r1, #17 800101a: 430a orrs r2, r1 800101c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800101e: f7ff fabd bl 800059c 8001022: 0003 movs r3, r0 8001024: 61bb str r3, [r7, #24] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001026: e008 b.n 800103a { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001028: f7ff fab8 bl 800059c 800102c: 0002 movs r2, r0 800102e: 69bb ldr r3, [r7, #24] 8001030: 1ad3 subs r3, r2, r3 8001032: 2b02 cmp r3, #2 8001034: d901 bls.n 800103a { return HAL_TIMEOUT; 8001036: 2303 movs r3, #3 8001038: e047 b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800103a: 4b26 ldr r3, [pc, #152] ; (80010d4 ) 800103c: 681a ldr r2, [r3, #0] 800103e: 2380 movs r3, #128 ; 0x80 8001040: 049b lsls r3, r3, #18 8001042: 4013 ands r3, r2 8001044: d0f0 beq.n 8001028 8001046: e03f b.n 80010c8 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001048: 4b22 ldr r3, [pc, #136] ; (80010d4 ) 800104a: 681a ldr r2, [r3, #0] 800104c: 4b21 ldr r3, [pc, #132] ; (80010d4 ) 800104e: 4924 ldr r1, [pc, #144] ; (80010e0 ) 8001050: 400a ands r2, r1 8001052: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001054: f7ff faa2 bl 800059c 8001058: 0003 movs r3, r0 800105a: 61bb str r3, [r7, #24] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800105c: e008 b.n 8001070 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 800105e: f7ff fa9d bl 800059c 8001062: 0002 movs r2, r0 8001064: 69bb ldr r3, [r7, #24] 8001066: 1ad3 subs r3, r2, r3 8001068: 2b02 cmp r3, #2 800106a: d901 bls.n 8001070 { return HAL_TIMEOUT; 800106c: 2303 movs r3, #3 800106e: e02c b.n 80010ca while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001070: 4b18 ldr r3, [pc, #96] ; (80010d4 ) 8001072: 681a ldr r2, [r3, #0] 8001074: 2380 movs r3, #128 ; 0x80 8001076: 049b lsls r3, r3, #18 8001078: 4013 ands r3, r2 800107a: d1f0 bne.n 800105e 800107c: e024 b.n 80010c8 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 800107e: 687b ldr r3, [r7, #4] 8001080: 6a1b ldr r3, [r3, #32] 8001082: 2b01 cmp r3, #1 8001084: d101 bne.n 800108a { return HAL_ERROR; 8001086: 2301 movs r3, #1 8001088: e01f b.n 80010ca } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 800108a: 4b12 ldr r3, [pc, #72] ; (80010d4 ) 800108c: 685b ldr r3, [r3, #4] 800108e: 617b str r3, [r7, #20] pll_config2 = RCC->CFGR2; 8001090: 4b10 ldr r3, [pc, #64] ; (80010d4 ) 8001092: 6adb ldr r3, [r3, #44] ; 0x2c 8001094: 613b str r3, [r7, #16] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001096: 697a ldr r2, [r7, #20] 8001098: 2380 movs r3, #128 ; 0x80 800109a: 025b lsls r3, r3, #9 800109c: 401a ands r2, r3 800109e: 687b ldr r3, [r7, #4] 80010a0: 6a5b ldr r3, [r3, #36] ; 0x24 80010a2: 429a cmp r2, r3 80010a4: d10e bne.n 80010c4 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 80010a6: 693b ldr r3, [r7, #16] 80010a8: 220f movs r2, #15 80010aa: 401a ands r2, r3 80010ac: 687b ldr r3, [r7, #4] 80010ae: 6adb ldr r3, [r3, #44] ; 0x2c if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80010b0: 429a cmp r2, r3 80010b2: d107 bne.n 80010c4 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) 80010b4: 697a ldr r2, [r7, #20] 80010b6: 23f0 movs r3, #240 ; 0xf0 80010b8: 039b lsls r3, r3, #14 80010ba: 401a ands r2, r3 80010bc: 687b ldr r3, [r7, #4] 80010be: 6a9b ldr r3, [r3, #40] ; 0x28 (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || 80010c0: 429a cmp r2, r3 80010c2: d001 beq.n 80010c8 { return HAL_ERROR; 80010c4: 2301 movs r3, #1 80010c6: e000 b.n 80010ca } } } } return HAL_OK; 80010c8: 2300 movs r3, #0 } 80010ca: 0018 movs r0, r3 80010cc: 46bd mov sp, r7 80010ce: b008 add sp, #32 80010d0: bd80 pop {r7, pc} 80010d2: 46c0 nop ; (mov r8, r8) 80010d4: 40021000 .word 0x40021000 80010d8: 00001388 .word 0x00001388 80010dc: efffffff .word 0xefffffff 80010e0: feffffff .word 0xfeffffff 80010e4: ffc2ffff .word 0xffc2ffff 080010e8 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80010e8: b580 push {r7, lr} 80010ea: b084 sub sp, #16 80010ec: af00 add r7, sp, #0 80010ee: 6078 str r0, [r7, #4] 80010f0: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 80010f2: 687b ldr r3, [r7, #4] 80010f4: 2b00 cmp r3, #0 80010f6: d101 bne.n 80010fc { return HAL_ERROR; 80010f8: 2301 movs r3, #1 80010fa: e0b3 b.n 8001264 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 80010fc: 4b5b ldr r3, [pc, #364] ; (800126c ) 80010fe: 681b ldr r3, [r3, #0] 8001100: 2201 movs r2, #1 8001102: 4013 ands r3, r2 8001104: 683a ldr r2, [r7, #0] 8001106: 429a cmp r2, r3 8001108: d911 bls.n 800112e { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800110a: 4b58 ldr r3, [pc, #352] ; (800126c ) 800110c: 681b ldr r3, [r3, #0] 800110e: 2201 movs r2, #1 8001110: 4393 bics r3, r2 8001112: 0019 movs r1, r3 8001114: 4b55 ldr r3, [pc, #340] ; (800126c ) 8001116: 683a ldr r2, [r7, #0] 8001118: 430a orrs r2, r1 800111a: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 800111c: 4b53 ldr r3, [pc, #332] ; (800126c ) 800111e: 681b ldr r3, [r3, #0] 8001120: 2201 movs r2, #1 8001122: 4013 ands r3, r2 8001124: 683a ldr r2, [r7, #0] 8001126: 429a cmp r2, r3 8001128: d001 beq.n 800112e { return HAL_ERROR; 800112a: 2301 movs r3, #1 800112c: e09a b.n 8001264 } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800112e: 687b ldr r3, [r7, #4] 8001130: 681b ldr r3, [r3, #0] 8001132: 2202 movs r2, #2 8001134: 4013 ands r3, r2 8001136: d015 beq.n 8001164 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001138: 687b ldr r3, [r7, #4] 800113a: 681b ldr r3, [r3, #0] 800113c: 2204 movs r2, #4 800113e: 4013 ands r3, r2 8001140: d006 beq.n 8001150 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8001142: 4b4b ldr r3, [pc, #300] ; (8001270 ) 8001144: 685a ldr r2, [r3, #4] 8001146: 4b4a ldr r3, [pc, #296] ; (8001270 ) 8001148: 21e0 movs r1, #224 ; 0xe0 800114a: 00c9 lsls r1, r1, #3 800114c: 430a orrs r2, r1 800114e: 605a str r2, [r3, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8001150: 4b47 ldr r3, [pc, #284] ; (8001270 ) 8001152: 685b ldr r3, [r3, #4] 8001154: 22f0 movs r2, #240 ; 0xf0 8001156: 4393 bics r3, r2 8001158: 0019 movs r1, r3 800115a: 687b ldr r3, [r7, #4] 800115c: 689a ldr r2, [r3, #8] 800115e: 4b44 ldr r3, [pc, #272] ; (8001270 ) 8001160: 430a orrs r2, r1 8001162: 605a str r2, [r3, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8001164: 687b ldr r3, [r7, #4] 8001166: 681b ldr r3, [r3, #0] 8001168: 2201 movs r2, #1 800116a: 4013 ands r3, r2 800116c: d040 beq.n 80011f0 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800116e: 687b ldr r3, [r7, #4] 8001170: 685b ldr r3, [r3, #4] 8001172: 2b01 cmp r3, #1 8001174: d107 bne.n 8001186 { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001176: 4b3e ldr r3, [pc, #248] ; (8001270 ) 8001178: 681a ldr r2, [r3, #0] 800117a: 2380 movs r3, #128 ; 0x80 800117c: 029b lsls r3, r3, #10 800117e: 4013 ands r3, r2 8001180: d114 bne.n 80011ac { return HAL_ERROR; 8001182: 2301 movs r3, #1 8001184: e06e b.n 8001264 } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8001186: 687b ldr r3, [r7, #4] 8001188: 685b ldr r3, [r3, #4] 800118a: 2b02 cmp r3, #2 800118c: d107 bne.n 800119e { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800118e: 4b38 ldr r3, [pc, #224] ; (8001270 ) 8001190: 681a ldr r2, [r3, #0] 8001192: 2380 movs r3, #128 ; 0x80 8001194: 049b lsls r3, r3, #18 8001196: 4013 ands r3, r2 8001198: d108 bne.n 80011ac { return HAL_ERROR; 800119a: 2301 movs r3, #1 800119c: e062 b.n 8001264 #endif /* RCC_CFGR_SWS_HSI48 */ /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800119e: 4b34 ldr r3, [pc, #208] ; (8001270 ) 80011a0: 681b ldr r3, [r3, #0] 80011a2: 2202 movs r2, #2 80011a4: 4013 ands r3, r2 80011a6: d101 bne.n 80011ac { return HAL_ERROR; 80011a8: 2301 movs r3, #1 80011aa: e05b b.n 8001264 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80011ac: 4b30 ldr r3, [pc, #192] ; (8001270 ) 80011ae: 685b ldr r3, [r3, #4] 80011b0: 2203 movs r2, #3 80011b2: 4393 bics r3, r2 80011b4: 0019 movs r1, r3 80011b6: 687b ldr r3, [r7, #4] 80011b8: 685a ldr r2, [r3, #4] 80011ba: 4b2d ldr r3, [pc, #180] ; (8001270 ) 80011bc: 430a orrs r2, r1 80011be: 605a str r2, [r3, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 80011c0: f7ff f9ec bl 800059c 80011c4: 0003 movs r3, r0 80011c6: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80011c8: e009 b.n 80011de { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 80011ca: f7ff f9e7 bl 800059c 80011ce: 0002 movs r2, r0 80011d0: 68fb ldr r3, [r7, #12] 80011d2: 1ad3 subs r3, r2, r3 80011d4: 4a27 ldr r2, [pc, #156] ; (8001274 ) 80011d6: 4293 cmp r3, r2 80011d8: d901 bls.n 80011de { return HAL_TIMEOUT; 80011da: 2303 movs r3, #3 80011dc: e042 b.n 8001264 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80011de: 4b24 ldr r3, [pc, #144] ; (8001270 ) 80011e0: 685b ldr r3, [r3, #4] 80011e2: 220c movs r2, #12 80011e4: 401a ands r2, r3 80011e6: 687b ldr r3, [r7, #4] 80011e8: 685b ldr r3, [r3, #4] 80011ea: 009b lsls r3, r3, #2 80011ec: 429a cmp r2, r3 80011ee: d1ec bne.n 80011ca } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 80011f0: 4b1e ldr r3, [pc, #120] ; (800126c ) 80011f2: 681b ldr r3, [r3, #0] 80011f4: 2201 movs r2, #1 80011f6: 4013 ands r3, r2 80011f8: 683a ldr r2, [r7, #0] 80011fa: 429a cmp r2, r3 80011fc: d211 bcs.n 8001222 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80011fe: 4b1b ldr r3, [pc, #108] ; (800126c ) 8001200: 681b ldr r3, [r3, #0] 8001202: 2201 movs r2, #1 8001204: 4393 bics r3, r2 8001206: 0019 movs r1, r3 8001208: 4b18 ldr r3, [pc, #96] ; (800126c ) 800120a: 683a ldr r2, [r7, #0] 800120c: 430a orrs r2, r1 800120e: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001210: 4b16 ldr r3, [pc, #88] ; (800126c ) 8001212: 681b ldr r3, [r3, #0] 8001214: 2201 movs r2, #1 8001216: 4013 ands r3, r2 8001218: 683a ldr r2, [r7, #0] 800121a: 429a cmp r2, r3 800121c: d001 beq.n 8001222 { return HAL_ERROR; 800121e: 2301 movs r3, #1 8001220: e020 b.n 8001264 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001222: 687b ldr r3, [r7, #4] 8001224: 681b ldr r3, [r3, #0] 8001226: 2204 movs r2, #4 8001228: 4013 ands r3, r2 800122a: d009 beq.n 8001240 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 800122c: 4b10 ldr r3, [pc, #64] ; (8001270 ) 800122e: 685b ldr r3, [r3, #4] 8001230: 4a11 ldr r2, [pc, #68] ; (8001278 ) 8001232: 4013 ands r3, r2 8001234: 0019 movs r1, r3 8001236: 687b ldr r3, [r7, #4] 8001238: 68da ldr r2, [r3, #12] 800123a: 4b0d ldr r3, [pc, #52] ; (8001270 ) 800123c: 430a orrs r2, r1 800123e: 605a str r2, [r3, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; 8001240: f000 f820 bl 8001284 8001244: 0001 movs r1, r0 8001246: 4b0a ldr r3, [pc, #40] ; (8001270 ) 8001248: 685b ldr r3, [r3, #4] 800124a: 091b lsrs r3, r3, #4 800124c: 220f movs r2, #15 800124e: 4013 ands r3, r2 8001250: 4a0a ldr r2, [pc, #40] ; (800127c ) 8001252: 5cd3 ldrb r3, [r2, r3] 8001254: 000a movs r2, r1 8001256: 40da lsrs r2, r3 8001258: 4b09 ldr r3, [pc, #36] ; (8001280 ) 800125a: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); 800125c: 2000 movs r0, #0 800125e: f7ff f957 bl 8000510 return HAL_OK; 8001262: 2300 movs r3, #0 } 8001264: 0018 movs r0, r3 8001266: 46bd mov sp, r7 8001268: b004 add sp, #16 800126a: bd80 pop {r7, pc} 800126c: 40022000 .word 0x40022000 8001270: 40021000 .word 0x40021000 8001274: 00001388 .word 0x00001388 8001278: fffff8ff .word 0xfffff8ff 800127c: 080013dc .word 0x080013dc 8001280: 20000000 .word 0x20000000 08001284 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8001284: b590 push {r4, r7, lr} 8001286: b08f sub sp, #60 ; 0x3c 8001288: af00 add r7, sp, #0 const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 800128a: 2314 movs r3, #20 800128c: 18fb adds r3, r7, r3 800128e: 4a2b ldr r2, [pc, #172] ; (800133c ) 8001290: ca13 ldmia r2!, {r0, r1, r4} 8001292: c313 stmia r3!, {r0, r1, r4} 8001294: 6812 ldr r2, [r2, #0] 8001296: 601a str r2, [r3, #0] 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 8001298: 1d3b adds r3, r7, #4 800129a: 4a29 ldr r2, [pc, #164] ; (8001340 ) 800129c: ca13 ldmia r2!, {r0, r1, r4} 800129e: c313 stmia r3!, {r0, r1, r4} 80012a0: 6812 ldr r2, [r2, #0] 80012a2: 601a str r2, [r3, #0] 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 80012a4: 2300 movs r3, #0 80012a6: 62fb str r3, [r7, #44] ; 0x2c 80012a8: 2300 movs r3, #0 80012aa: 62bb str r3, [r7, #40] ; 0x28 80012ac: 2300 movs r3, #0 80012ae: 637b str r3, [r7, #52] ; 0x34 80012b0: 2300 movs r3, #0 80012b2: 627b str r3, [r7, #36] ; 0x24 uint32_t sysclockfreq = 0U; 80012b4: 2300 movs r3, #0 80012b6: 633b str r3, [r7, #48] ; 0x30 tmpreg = RCC->CFGR; 80012b8: 4b22 ldr r3, [pc, #136] ; (8001344 ) 80012ba: 685b ldr r3, [r3, #4] 80012bc: 62fb str r3, [r7, #44] ; 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80012be: 6afb ldr r3, [r7, #44] ; 0x2c 80012c0: 220c movs r2, #12 80012c2: 4013 ands r3, r2 80012c4: 2b04 cmp r3, #4 80012c6: d002 beq.n 80012ce 80012c8: 2b08 cmp r3, #8 80012ca: d003 beq.n 80012d4 80012cc: e02d b.n 800132a { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80012ce: 4b1e ldr r3, [pc, #120] ; (8001348 ) 80012d0: 633b str r3, [r7, #48] ; 0x30 break; 80012d2: e02d b.n 8001330 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; 80012d4: 6afb ldr r3, [r7, #44] ; 0x2c 80012d6: 0c9b lsrs r3, r3, #18 80012d8: 220f movs r2, #15 80012da: 4013 ands r3, r2 80012dc: 2214 movs r2, #20 80012de: 18ba adds r2, r7, r2 80012e0: 5cd3 ldrb r3, [r2, r3] 80012e2: 627b str r3, [r7, #36] ; 0x24 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; 80012e4: 4b17 ldr r3, [pc, #92] ; (8001344 ) 80012e6: 6adb ldr r3, [r3, #44] ; 0x2c 80012e8: 220f movs r2, #15 80012ea: 4013 ands r3, r2 80012ec: 1d3a adds r2, r7, #4 80012ee: 5cd3 ldrb r3, [r2, r3] 80012f0: 62bb str r3, [r7, #40] ; 0x28 if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) 80012f2: 6afa ldr r2, [r7, #44] ; 0x2c 80012f4: 2380 movs r3, #128 ; 0x80 80012f6: 025b lsls r3, r3, #9 80012f8: 4013 ands r3, r2 80012fa: d009 beq.n 8001310 { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); 80012fc: 6ab9 ldr r1, [r7, #40] ; 0x28 80012fe: 4812 ldr r0, [pc, #72] ; (8001348 ) 8001300: f7fe ff02 bl 8000108 <__udivsi3> 8001304: 0003 movs r3, r0 8001306: 001a movs r2, r3 8001308: 6a7b ldr r3, [r7, #36] ; 0x24 800130a: 4353 muls r3, r2 800130c: 637b str r3, [r7, #52] ; 0x34 800130e: e009 b.n 8001324 #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); #else /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); 8001310: 6a79 ldr r1, [r7, #36] ; 0x24 8001312: 000a movs r2, r1 8001314: 0152 lsls r2, r2, #5 8001316: 1a52 subs r2, r2, r1 8001318: 0193 lsls r3, r2, #6 800131a: 1a9b subs r3, r3, r2 800131c: 00db lsls r3, r3, #3 800131e: 185b adds r3, r3, r1 8001320: 021b lsls r3, r3, #8 8001322: 637b str r3, [r7, #52] ; 0x34 #endif } sysclockfreq = pllclk; 8001324: 6b7b ldr r3, [r7, #52] ; 0x34 8001326: 633b str r3, [r7, #48] ; 0x30 break; 8001328: e002 b.n 8001330 } #endif /* RCC_CFGR_SWS_HSI48 */ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 800132a: 4b07 ldr r3, [pc, #28] ; (8001348 ) 800132c: 633b str r3, [r7, #48] ; 0x30 break; 800132e: 46c0 nop ; (mov r8, r8) } } return sysclockfreq; 8001330: 6b3b ldr r3, [r7, #48] ; 0x30 } 8001332: 0018 movs r0, r3 8001334: 46bd mov sp, r7 8001336: b00f add sp, #60 ; 0x3c 8001338: bd90 pop {r4, r7, pc} 800133a: 46c0 nop ; (mov r8, r8) 800133c: 080013bc .word 0x080013bc 8001340: 080013cc .word 0x080013cc 8001344: 40021000 .word 0x40021000 8001348: 007a1200 .word 0x007a1200 0800134c <__libc_init_array>: 800134c: b570 push {r4, r5, r6, lr} 800134e: 2600 movs r6, #0 8001350: 4d0c ldr r5, [pc, #48] ; (8001384 <__libc_init_array+0x38>) 8001352: 4c0d ldr r4, [pc, #52] ; (8001388 <__libc_init_array+0x3c>) 8001354: 1b64 subs r4, r4, r5 8001356: 10a4 asrs r4, r4, #2 8001358: 42a6 cmp r6, r4 800135a: d109 bne.n 8001370 <__libc_init_array+0x24> 800135c: 2600 movs r6, #0 800135e: f000 f821 bl 80013a4 <_init> 8001362: 4d0a ldr r5, [pc, #40] ; (800138c <__libc_init_array+0x40>) 8001364: 4c0a ldr r4, [pc, #40] ; (8001390 <__libc_init_array+0x44>) 8001366: 1b64 subs r4, r4, r5 8001368: 10a4 asrs r4, r4, #2 800136a: 42a6 cmp r6, r4 800136c: d105 bne.n 800137a <__libc_init_array+0x2e> 800136e: bd70 pop {r4, r5, r6, pc} 8001370: 00b3 lsls r3, r6, #2 8001372: 58eb ldr r3, [r5, r3] 8001374: 4798 blx r3 8001376: 3601 adds r6, #1 8001378: e7ee b.n 8001358 <__libc_init_array+0xc> 800137a: 00b3 lsls r3, r6, #2 800137c: 58eb ldr r3, [r5, r3] 800137e: 4798 blx r3 8001380: 3601 adds r6, #1 8001382: e7f2 b.n 800136a <__libc_init_array+0x1e> 8001384: 080013ec .word 0x080013ec 8001388: 080013ec .word 0x080013ec 800138c: 080013ec .word 0x080013ec 8001390: 080013f0 .word 0x080013f0 08001394 : 8001394: 0003 movs r3, r0 8001396: 1812 adds r2, r2, r0 8001398: 4293 cmp r3, r2 800139a: d100 bne.n 800139e 800139c: 4770 bx lr 800139e: 7019 strb r1, [r3, #0] 80013a0: 3301 adds r3, #1 80013a2: e7f9 b.n 8001398 080013a4 <_init>: 80013a4: b5f8 push {r3, r4, r5, r6, r7, lr} 80013a6: 46c0 nop ; (mov r8, r8) 80013a8: bcf8 pop {r3, r4, r5, r6, r7} 80013aa: bc08 pop {r3} 80013ac: 469e mov lr, r3 80013ae: 4770 bx lr 080013b0 <_fini>: 80013b0: b5f8 push {r3, r4, r5, r6, r7, lr} 80013b2: 46c0 nop ; (mov r8, r8) 80013b4: bcf8 pop {r3, r4, r5, r6, r7} 80013b6: bc08 pop {r3} 80013b8: 469e mov lr, r3 80013ba: 4770 bx lr