369 lines
16 KiB
C
369 lines
16 KiB
C
/**
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******************************************************************************
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* @file cbtl08gp053.h
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* @author MCD Application Team
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* @brief This file contains all the functions prototypes for the CBTL08GP053
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* (Crossbar switch device for USB Type-C systems).
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __CBTL08GP053_H
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#define __CBTL08GP053_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include <stdint.h>
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#include "../Common/usbtypecswitch.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Components
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* @{
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*/
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/** @addtogroup CBTL08GP053
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* @{
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*/
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#ifdef DBG_BSP_MUX
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typedef struct
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{
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uint8_t RESERVED1; /*!< Address offset: 0x00 */
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uint8_t SYS_CTRL; /*!< Address offset: 0x01 */
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uint8_t OP1_CTRL; /*!< Address offset: 0x02 */
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uint8_t OP2_CTRL; /*!< Address offset: 0x03 */
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uint8_t OP3_CTRL; /*!< Address offset: 0x04 */
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uint8_t OP4_CTRL; /*!< Address offset: 0x05 */
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uint8_t OP5_CTRL; /*!< Address offset: 0x06 */
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uint8_t CROSS5_CTRL; /*!< Address offset: 0x07 */
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uint8_t SW_CTRL; /*!< Address offset: 0x08 */
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uint8_t REVISION; /*!< Address offset: 0x09 */
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} CBTL08GP053_TypeDef;
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extern CBTL08GP053_TypeDef CBTL08GP053;
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#endif /* DBG_BSP_MUX */
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/** @defgroup CBTL08GP053_Exported_Constants
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* @{
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*/
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/******************************* Register Map ********************************/
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#define CBTL08GP053_REG_SYS_CTRL 0x01 /*!< */
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#define CBTL08GP053_REG_OP1_CTRL 0x02 /*!< */
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#define CBTL08GP053_REG_OP2_CTRL 0x03 /*!< */
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#define CBTL08GP053_REG_OP3_CTRL 0x04 /*!< */
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#define CBTL08GP053_REG_OP4_CTRL 0x05 /*!< */
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#define CBTL08GP053_REG_OP5_CTRL 0x06 /*!< */
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#define CBTL08GP053_REG_CROSS5_CTRL 0x07 /*!< */
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#define CBTL08GP053_REG_SW_CTRL 0x08 /*!< */
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#define CBTL08GP053_REG_REVISION 0x09 /*!< */
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/********************* Bit definition for SYS_CTRL register *****************/
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#define CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Pos (7U)
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#define CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Msk (0x1U << CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Pos) /*!< 0x80*/
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#define CBTL08GP053_REG_SYS_CTRL_SWITCH_EN CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Msk /*!< */
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/********************* Bit definition for OP1_CTRL register *****************/
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#define CBTL08GP053_REG_OP1_CTRL_EN_IP1_Pos (0U)
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#define CBTL08GP053_REG_OP1_CTRL_EN_IP1_Msk (0x1U << CBTL08GP053_REG_OP1_CTRL_EN_IP1_Pos) /*!< 0x01 */
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#define CBTL08GP053_REG_OP1_CTRL_EN_IP1 CBTL08GP053_REG_OP1_CTRL_EN_IP1_Msk /*!< */
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#define CBTL08GP053_REG_OP1_CTRL_EN_IP2_Pos (1U)
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#define CBTL08GP053_REG_OP1_CTRL_EN_IP2_Msk (0x1U << CBTL08GP053_REG_OP1_CTRL_EN_IP2_Pos) /*!< 0x02 */
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#define CBTL08GP053_REG_OP1_CTRL_EN_IP2 CBTL08GP053_REG_OP1_CTRL_EN_IP2_Msk /*!< */
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#define CBTL08GP053_REG_OP1_CTRL_EN_IP3_Pos (2U)
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#define CBTL08GP053_REG_OP1_CTRL_EN_IP3_Msk (0x1U << CBTL08GP053_REG_OP1_CTRL_EN_IP3_Pos) /*!< 0x04 */
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#define CBTL08GP053_REG_OP1_CTRL_EN_IP3 CBTL08GP053_REG_OP1_CTRL_EN_IP3_Msk /*!< */
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/********************* Bit definition for OP2_CTRL register *****************/
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#define CBTL08GP053_REG_OP2_CTRL_EN_IP1_Pos (0U)
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#define CBTL08GP053_REG_OP2_CTRL_EN_IP1_Msk (0x1U << CBTL08GP053_REG_OP2_CTRL_EN_IP1_Pos) /*!< 0x01 */
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#define CBTL08GP053_REG_OP2_CTRL_EN_IP1 CBTL08GP053_REG_OP2_CTRL_EN_IP1_Msk /*!< */
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#define CBTL08GP053_REG_OP2_CTRL_EN_IP2_Pos (1U)
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#define CBTL08GP053_REG_OP2_CTRL_EN_IP2_Msk (0x1U << CBTL08GP053_REG_OP2_CTRL_EN_IP2_Pos) /*!< 0x02 */
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#define CBTL08GP053_REG_OP2_CTRL_EN_IP2 CBTL08GP053_REG_OP2_CTRL_EN_IP2_Msk /*!< */
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#define CBTL08GP053_REG_OP2_CTRL_EN_IP3_Pos (2U)
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#define CBTL08GP053_REG_OP2_CTRL_EN_IP3_Msk (0x1U << CBTL08GP053_REG_OP2_CTRL_EN_IP3_Pos) /*!< 0x04 */
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#define CBTL08GP053_REG_OP2_CTRL_EN_IP3 CBTL08GP053_REG_OP2_CTRL_EN_IP3_Msk /*!< */
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/********************* Bit definition for OP3_CTRL register *****************/
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#define CBTL08GP053_REG_OP3_CTRL_EN_IP4_Pos (3U)
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#define CBTL08GP053_REG_OP3_CTRL_EN_IP4_Msk (0x1U << CBTL08GP053_REG_OP3_CTRL_EN_IP4_Pos) /*!< 0x08 */
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#define CBTL08GP053_REG_OP3_CTRL_EN_IP4 CBTL08GP053_REG_OP3_CTRL_EN_IP4_Msk /*!< */
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#define CBTL08GP053_REG_OP3_CTRL_EN_IP5_Pos (4U)
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#define CBTL08GP053_REG_OP3_CTRL_EN_IP5_Msk (0x1U << CBTL08GP053_REG_OP3_CTRL_EN_IP5_Pos) /*!< 0x10 */
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#define CBTL08GP053_REG_OP3_CTRL_EN_IP5 CBTL08GP053_REG_OP3_CTRL_EN_IP5_Msk /*!< */
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#define CBTL08GP053_REG_OP3_CTRL_EN_IP6_Pos (5U)
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#define CBTL08GP053_REG_OP3_CTRL_EN_IP6_Msk (0x1U << CBTL08GP053_REG_OP3_CTRL_EN_IP6_Pos) /*!< 0x20 */
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#define CBTL08GP053_REG_OP3_CTRL_EN_IP6 CBTL08GP053_REG_OP3_CTRL_EN_IP6_Msk /*!< */
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/********************* Bit definition for OP4_CTRL register *****************/
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#define CBTL08GP053_REG_OP4_CTRL_EN_IP4_Pos (3U)
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#define CBTL08GP053_REG_OP4_CTRL_EN_IP4_Msk (0x1U << CBTL08GP053_REG_OP4_CTRL_EN_IP4_Pos) /*!< 0x08 */
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#define CBTL08GP053_REG_OP4_CTRL_EN_IP4 CBTL08GP053_REG_OP4_CTRL_EN_IP4_Msk /*!< */
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#define CBTL08GP053_REG_OP4_CTRL_EN_IP5_Pos (4U)
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#define CBTL08GP053_REG_OP4_CTRL_EN_IP5_Msk (0x1U << CBTL08GP053_REG_OP4_CTRL_EN_IP5_Pos) /*!< 0x10 */
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#define CBTL08GP053_REG_OP4_CTRL_EN_IP5 CBTL08GP053_REG_OP4_CTRL_EN_IP5_Msk /*!< */
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#define CBTL08GP053_REG_OP4_CTRL_EN_IP6_Pos (5U)
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#define CBTL08GP053_REG_OP4_CTRL_EN_IP6_Msk (0x1U << CBTL08GP053_REG_OP4_CTRL_EN_IP6_Pos) /*!< 0x20 */
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#define CBTL08GP053_REG_OP4_CTRL_EN_IP6 CBTL08GP053_REG_OP4_CTRL_EN_IP6_Msk /*!< */
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/********************* Bit definition for OP5_CTRL register *****************/
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#define CBTL08GP053_REG_OP5_CTRL_EN_IP7_Pos (6U)
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#define CBTL08GP053_REG_OP5_CTRL_EN_IP7_Msk (0x1U << CBTL08GP053_REG_OP5_CTRL_EN_IP7_Pos) /*!< 0x40 */
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#define CBTL08GP053_REG_OP5_CTRL_EN_IP7 CBTL08GP053_REG_OP5_CTRL_EN_IP7_Msk /*!< */
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#define CBTL08GP053_REG_OP5_CTRL_EN_IP8_Pos (7U)
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#define CBTL08GP053_REG_OP5_CTRL_EN_IP8_Msk (0x1U << CBTL08GP053_REG_OP5_CTRL_EN_IP8_Pos) /*!< 0x80 */
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#define CBTL08GP053_REG_OP5_CTRL_EN_IP8 CBTL08GP053_REG_OP5_CTRL_EN_IP8_Msk /*!< */
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/****************** Bit definition for CROSS5_CTRL register *****************/
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#define CBTL08GP053_REG_CROSS5_PASS_Pos (0U)
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#define CBTL08GP053_REG_CROSS5_PASS_Msk (0x1U << CBTL08GP053_REG_CROSS5_PASS_Pos) /*!< 0x01 */
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#define CBTL08GP053_REG_CROSS5_PASS CBTL08GP053_REG_CROSS5_PASS_Msk /*!< */
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#define CBTL08GP053_REG_CROSS5_CROSS_Pos (1U)
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#define CBTL08GP053_REG_CROSS5_CROSS_Msk (0x1U << CBTL08GP053_REG_CROSS5_CROSS_Pos) /*!< 0x02 */
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#define CBTL08GP053_REG_CROSS5_CROSS CBTL08GP053_REG_CROSS5_CROSS_Msk /*!< */
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/******************* Bit definition for SW_CTRL register ********************/
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#define CBTL08GP053_REG_SW_OP1_SET_Pos (0U)
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#define CBTL08GP053_REG_SW_OP1_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP1_SET_Pos) /*!< 0x01 */
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#define CBTL08GP053_REG_SW_OP1_SET CBTL08GP053_REG_SW_OP1_SET_Msk /*!< */
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#define CBTL08GP053_REG_SW_OP2_SET_Pos (1U)
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#define CBTL08GP053_REG_SW_OP2_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP2_SET_Pos) /*!< 0x02 */
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#define CBTL08GP053_REG_SW_OP2_SET CBTL08GP053_REG_SW_OP2_SET_Msk /*!< */
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#define CBTL08GP053_REG_SW_OP3_SET_Pos (2U)
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#define CBTL08GP053_REG_SW_OP3_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP3_SET_Pos) /*!< 0x04 */
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#define CBTL08GP053_REG_SW_OP3_SET CBTL08GP053_REG_SW_OP3_SET_Msk /*!< */
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#define CBTL08GP053_REG_SW_OP4_SET_Pos (3U)
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#define CBTL08GP053_REG_SW_OP4_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP4_SET_Pos) /*!< 0x08 */
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#define CBTL08GP053_REG_SW_OP4_SET CBTL08GP053_REG_SW_OP4_SET_Msk /*!< */
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#define CBTL08GP053_REG_SW_OP5_SET_Pos (4U)
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#define CBTL08GP053_REG_SW_OP5_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP5_SET_Pos) /*!< 0x10 */
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#define CBTL08GP053_REG_SW_OP5_SET CBTL08GP053_REG_SW_OP5_SET_Msk /*!< */
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#define CBTL08GP053_REG_SW_X5_SET_Pos (5U)
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#define CBTL08GP053_REG_SW_X5_SET_Msk (0x1U << CBTL08GP053_REG_SW_X5_SET_Pos) /*!< 0x20 */
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#define CBTL08GP053_REG_SW_X5_SET CBTL08GP053_REG_SW_X5_SET_Msk /*!< */
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/******************** Bit definition for REVISION register ******************/
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#define CBTL08GP053_REVISION_REV_ID_Pos (0U)
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#define CBTL08GP053_REVISION_REV_ID_Msk (0xFFU << CBTL08GP053_REVISION_REV_ID_Pos) /*!< 0xFF */
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#define CBTL08GP053_REVISION_REV_ID CBTL08GP053_REVISION_REV_ID_Msk /*!< */
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/** @defgroup CBTL08GP053_DisplayPort_Alternate_Mode
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* @{
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*/
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#define CBTL08GP053_DP_ALTMODE_DFP_D_C_E_NORMAL 0x00U
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#define CBTL08GP053_DP_ALTMODE_DFP_D_C_E_FLIPPED 0x01U
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#define CBTL08GP053_DP_ALTMODE_DFP_D_D_F_NORMAL 0x02U
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#define CBTL08GP053_DP_ALTMODE_DFP_D_D_F_FLIPPED 0x03U
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#define CBTL08GP053_DP_ALTMODE_UFP_D_C_NORMAL 0x04U
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#define CBTL08GP053_DP_ALTMODE_UFP_D_C_FLIPPED 0x05U
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#define CBTL08GP053_DP_ALTMODE_UFP_D_D_NORMAL 0x06U
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#define CBTL08GP053_DP_ALTMODE_UFP_D_D_FLIPPED 0x07U
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#define CBTL08GP053_DP_ALTMODE_UFP_D_E_NORMAL 0x08U
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#define CBTL08GP053_DP_ALTMODE_UFP_D_E_FLIPPED 0x09U
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/**
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* @}
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*/
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/** @defgroup CBTL08GP053_DisplayPort_Standby_Mode
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* @{
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*/
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#define CBTL08GP053_DP_STANDBYMODE_SAFE 0x00U
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#define CBTL08GP053_DP_STANDBYMODE_USB3_NORMAL 0x01U
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#define CBTL08GP053_DP_STANDBYMODE_USB3_FLIPPED 0x02U
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/**
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* @}
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*/
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/**
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* @}
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*/
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#if defined(CBTL08GP053_DEBUG)
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/** @defgroup CBTL08GP053_Exported_Structure CBTL08GP053 Exported Structure
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* @{
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*/
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RESERVED :7;
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uint8_t SWITCH_EN :1;
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};
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} CBTL08GP053_SysCtrlTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t IP1 :1;
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uint8_t IP2 :1;
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uint8_t IP3 :1;
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uint8_t RESERVED :5;
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};
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} CBTL08GP053_Op1CtrlTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t IP1 :1;
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uint8_t IP2 :1;
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uint8_t IP3 :1;
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uint8_t RESERVED :5;
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};
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} CBTL08GP053_Op2CtrlTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RESERVED1 :3;
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uint8_t IP4 :1;
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uint8_t IP5 :1;
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uint8_t IP6 :1;
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uint8_t RESERVED2 :2;
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};
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} CBTL08GP053_Op3CtrlTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RESERVED1 :3;
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uint8_t IP4 :1;
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uint8_t IP5 :1;
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uint8_t IP6 :1;
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uint8_t RESERVED2 :2;
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};
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} CBTL08GP053_Op4CtrlTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RESERVED :6;
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uint8_t IP7 :1;
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uint8_t IP8 :1;
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};
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} CBTL08GP053_Op5CtrlTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t PASS :1;
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uint8_t CROSS :1;
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uint8_t RESERVED :6;
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};
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} CBTL08GP053_Cross5CtrlTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t OP1_SET :1;
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uint8_t OP2_SET :1;
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uint8_t OP3_SET :1;
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uint8_t OP4_SET :1;
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uint8_t OP5_SET :1;
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uint8_t X5_SET :1;
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uint8_t RESERVED :2;
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};
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} CBTL08GP053_SwCtrlTypeDef;
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typedef struct
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{
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CBTL08GP053_SysCtrlTypeDef SysCtrl; /*!< SYS_CTRL register (0x01) */
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CBTL08GP053_Op1CtrlTypeDef Op1Ctrl; /*!< OP1_CTRL Registers (0x02) */
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CBTL08GP053_Op2CtrlTypeDef Op2Ctrl; /*!< OP2_CTRL Registers (0x03) */
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CBTL08GP053_Op3CtrlTypeDef Op3Ctrl; /*!< OP3_CTRL Registers (0x04) */
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CBTL08GP053_Op4CtrlTypeDef Op4Ctrl; /*!< OP4_CTRL Registers (0x05) */
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CBTL08GP053_Op5CtrlTypeDef Op5Ctrl; /*!< OP5_CTRL Registers (0x06) */
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CBTL08GP053_Cross5CtrlTypeDef Cross5Ctrl; /*!< CROSS5_CTRL Registers (0x07) */
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CBTL08GP053_SwCtrlTypeDef SwCtrl; /*!< SW_CTRL Registers (0x08) */
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uint8_t Revision; /*!< REVISION Registers (0x09) */
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} CBTL08GP053_RegistersTypeDef;
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/**
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* @}
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*/
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#endif /* CBTL08GP053_DEBUG */
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/** @defgroup CBTL08GP053_Exported_Functions
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* @{
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*/
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/* USB Type-C Crosspoint Switch management functions */
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uint32_t cbtl08gp053_Init(uint16_t Address);
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void cbtl08gp053_DeInit(uint16_t Address);
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uint32_t cbtl08gp053_PowerOn(uint16_t Address);
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uint32_t cbtl08gp053_PowerOff(uint16_t Address);
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uint32_t cbtl08gp053_SetMode(uint16_t Address, TYPECSWITCH_Mode_t Mode);
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uint32_t cbtl08gp053_IsSupportedMode(TYPECSWITCH_Mode_t Mode);
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/* MUX IO functions */
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uint8_t MUX_IO_Init(void);
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void MUX_IO_DeInit(void);
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uint8_t MUX_IO_Write(uint16_t Addr, uint16_t Reg, uint8_t Data);
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uint8_t MUX_IO_Read(uint16_t Addr, uint16_t Reg, uint8_t *pData);
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uint32_t MUX_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials);
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/**
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* @}
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*/
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/** @defgroup CBTL08GP053_Exported_Variables
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* @{
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*/
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/* Type-C Crosspoint Switch Driver */
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extern TYPECSWITCH_Drv_t cbtl08gp053_drv;
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CBTL08GP053_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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