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Jochen Friedrich
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<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
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<head>
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<meta charset="utf-8" />
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<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
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<title>Release Notes for CBTL08GP053 Component Drivers</title>
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code{white-space: pre-wrap;}
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span.smallcaps{font-variant: small-caps;}
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<div class="card fluid">
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<div class="sectione dark">
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||||
<center>
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||||
<h1 id="release-notes-for-cbtl08gp053-component-drivers"><small>Release Notes for</small> <mark>CBTL08GP053 Component Drivers</mark></h1>
|
||||
<p>Copyright © 2017 STMicroelectronics<br />
|
||||
</p>
|
||||
<a href="https://www.st.com" class="logo"><img src="../../../../_htmresc/st_logo.png" alt="ST logo" /></a>
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</center>
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</div>
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</div>
|
||||
<h1 id="license">License</h1>
|
||||
<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
|
||||
<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
|
||||
<h1 id="purpose">Purpose</h1>
|
||||
<p>This directory contains the CBTL08GP053 component drivers.</p>
|
||||
</div>
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||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history">Update History</h1>
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||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section12" checked aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.0.1 / 23-July-2020</label>
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||||
<div>
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||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<ul>
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||||
<li>Fix minor mispelled words</li>
|
||||
<li>Update Release Notes format</li>
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||||
</ul>
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</div>
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</div>
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<div class="collapse">
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<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.0.0 / 16-November-2017</label>
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||||
<div>
|
||||
<h2 id="main-changes-1">Main Changes</h2>
|
||||
<ul>
|
||||
<li>First official release of CBTL08GP053 Component driver</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
</div>
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||||
</div>
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||||
<footer class="sticky">
|
||||
For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a>
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</html>
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/**
|
||||
******************************************************************************
|
||||
* @file cbtl08gp053.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides a set of functions needed to manage the CBTL08GP053
|
||||
* (Crossbar switch device for USB Type-C systems).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "cbtl08gp053.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CBTL08GP053
|
||||
* @brief This file provides a set of functions needed to drive the
|
||||
* CBTL08GP053 Crossbar switch device for USB Type-C systems.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CBTL08GP053_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CBTL08GP053_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CBTL08GP053_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CBTL08GP053_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
#ifdef DBG_BSP_MUX
|
||||
CBTL08GP053_TypeDef CBTL08GP053 =
|
||||
{
|
||||
.SYS_CTRL = 0x00,
|
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.OP1_CTRL = 0x00,
|
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.OP2_CTRL = 0x00,
|
||||
.OP3_CTRL = 0x00,
|
||||
.OP4_CTRL = 0x00,
|
||||
.OP5_CTRL = 0x00,
|
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.CROSS5_CTRL = 0x01,
|
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.SW_CTRL = 0x00,
|
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.SW_CTRL = 0x00,
|
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.REVISION = 0xA0
|
||||
};
|
||||
#endif /* DBG_BSP_MUX */
|
||||
|
||||
/* Type-C Crosspoint Switch Driver structure initialization */
|
||||
TYPECSWITCH_Drv_t cbtl08gp053_drv = {
|
||||
cbtl08gp053_Init,
|
||||
cbtl08gp053_DeInit,
|
||||
cbtl08gp053_PowerOn,
|
||||
cbtl08gp053_PowerOff,
|
||||
cbtl08gp053_SetMode,
|
||||
cbtl08gp053_IsSupportedMode
|
||||
};
|
||||
|
||||
/* Supported USB Type-C pin assignments */
|
||||
static const uint32_t cbtl08gp053_SupportedModes =
|
||||
( 1 << USB_NORMAL |
|
||||
1 << USB_FLIPPED |
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||||
1 << DFP_D_PIN_ASSIGNMENT_C_NORMAL |
|
||||
1 << DFP_D_PIN_ASSIGNMENT_C_FLIPPED |
|
||||
1 << DFP_D_PIN_ASSIGNMENT_D_NORMAL |
|
||||
1 << DFP_D_PIN_ASSIGNMENT_D_FLIPPED |
|
||||
1 << DFP_D_PIN_ASSIGNMENT_E_NORMAL |
|
||||
1 << DFP_D_PIN_ASSIGNMENT_E_FLIPPED |
|
||||
1 << DFP_D_PIN_ASSIGNMENT_F_NORMAL |
|
||||
1 << DFP_D_PIN_ASSIGNMENT_F_FLIPPED |
|
||||
1 << UFP_D_PIN_ASSIGNMENT_C_NORMAL |
|
||||
1 << UFP_D_PIN_ASSIGNMENT_C_FLIPPED |
|
||||
1 << UFP_D_PIN_ASSIGNMENT_D_NORMAL |
|
||||
1 << UFP_D_PIN_ASSIGNMENT_D_FLIPPED |
|
||||
1 << UFP_D_PIN_ASSIGNMENT_E_NORMAL |
|
||||
1 << UFP_D_PIN_ASSIGNMENT_E_FLIPPED );
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CBTL08GP053_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
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||||
|
||||
/** @defgroup CBTL08GP053_Private_Functions
|
||||
* @{
|
||||
*/
|
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|
||||
/**
|
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* @brief Initialize the CBTL08GP053 and configure the needed hardware resources.
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* @param Address CBTL08GP053 address on communication Bus.
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* @retval 0: successful, else failed
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*/
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uint32_t cbtl08gp053_Init(uint16_t Address)
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{
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uint32_t err_count = 0;
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/* Low level init */
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err_count += MUX_IO_Init();
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/* Restore CBTL08GP053 registers reset values */
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MUX_IO_Write(Address, CBTL08GP053_REG_SYS_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x01);
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MUX_IO_Write(Address, CBTL08GP053_REG_SW_CTRL, 0x00);
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return err_count;
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}
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/**
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* @brief Release the hardware resources required to use the CBTL08GP053.
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* @param Address CBTL08GP053 address on communication Bus.
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* @retval none
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*/
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void cbtl08gp053_DeInit(uint16_t Address)
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{
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/* Restore CBTL08GP053 registers reset values */
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MUX_IO_Write(Address, CBTL08GP053_REG_SYS_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
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MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x01);
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MUX_IO_Write(Address, CBTL08GP053_REG_SW_CTRL, 0x00);
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/* Low level de-init */
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MUX_IO_DeInit();
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}
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/**
|
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* @brief Power on the CBTL08GP053.
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* @param Address CBTL08GP053 address on communication Bus.
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* @retval 0: successful, else failed
|
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*/
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uint32_t cbtl08gp053_PowerOn(uint16_t Address)
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{
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uint32_t err_count = 0;
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/* Set SYS_CTRL.SWTICH_EN bit */
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_SYS_CTRL, CBTL08GP053_REG_SYS_CTRL_SWITCH_EN);
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return err_count;
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}
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|
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/**
|
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* @brief Power down the CBTL08GP053.
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* @param Address CBTL08GP053 address on communication Bus.
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* @retval 0: successful, else failed
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*/
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uint32_t cbtl08gp053_PowerOff(uint16_t Address)
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{
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uint32_t err_count = 0;
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/* Clear SYS_CTRL.SWTICH_EN bit */
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_SYS_CTRL, 0x00);
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return err_count;
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}
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|
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/**
|
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* @brief Configure the CBTL08GP053 according to the requested USB Type-C
|
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* connector pin assignment.
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* @param Address CBTL08GP053 address on communication Bus.
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* @param Mode USB Type-C connector pin assignment
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* @retval 0: success, else error
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*/
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uint32_t cbtl08gp053_SetMode(uint16_t Address, TYPECSWITCH_Mode_t Mode)
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{
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uint32_t err_count = 0;
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uint8_t sw_ctrl = (CBTL08GP053_REG_SW_X5_SET |
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CBTL08GP053_REG_SW_OP1_SET |
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CBTL08GP053_REG_SW_OP2_SET |
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CBTL08GP053_REG_SW_OP3_SET |
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CBTL08GP053_REG_SW_OP4_SET |
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CBTL08GP053_REG_SW_OP5_SET);
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/* Transition to safe mode prior updating cross switch configuration */
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, 0x00);
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, 0x00);
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, 0x00);
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, 0x00);
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x00);
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/* Configure cross switch */
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switch(Mode)
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{
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case USB_NORMAL:
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP1);
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, 0x00);
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP4);
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, 0x00);
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
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err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x00);
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break;
|
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case USB_FLIPPED:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, 0x00);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP1);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, 0x00);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP4);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x00);
|
||||
break;
|
||||
case DFP_D_PIN_ASSIGNMENT_C_NORMAL:
|
||||
case DFP_D_PIN_ASSIGNMENT_E_NORMAL:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP2);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP3);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP5);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP6);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_PASS);
|
||||
break;
|
||||
case DFP_D_PIN_ASSIGNMENT_C_FLIPPED:
|
||||
case DFP_D_PIN_ASSIGNMENT_E_FLIPPED:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP3);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP2);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP6);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP5);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_CROSS);
|
||||
break;
|
||||
case DFP_D_PIN_ASSIGNMENT_D_NORMAL:
|
||||
case DFP_D_PIN_ASSIGNMENT_F_NORMAL:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP1);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP3);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP4);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP6);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_PASS);
|
||||
break;
|
||||
case DFP_D_PIN_ASSIGNMENT_D_FLIPPED:
|
||||
case DFP_D_PIN_ASSIGNMENT_F_FLIPPED:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP3);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP1);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP6);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP4);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_CROSS);
|
||||
break;
|
||||
case UFP_D_PIN_ASSIGNMENT_C_NORMAL:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP2);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP3);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP5);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP6);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_CROSS);
|
||||
break;
|
||||
case UFP_D_PIN_ASSIGNMENT_C_FLIPPED:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP3);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP2);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP6);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP5);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_PASS);
|
||||
break;
|
||||
case UFP_D_PIN_ASSIGNMENT_D_NORMAL:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP1);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP3);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP4);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP6);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_CROSS);
|
||||
break;
|
||||
case UFP_D_PIN_ASSIGNMENT_D_FLIPPED:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP3);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP1);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP6);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP4);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_PASS);
|
||||
break;
|
||||
case UFP_D_PIN_ASSIGNMENT_E_NORMAL:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP2);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP3);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP5);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP6);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_CROSS);
|
||||
break;
|
||||
case UFP_D_PIN_ASSIGNMENT_E_FLIPPED:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP3);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP2);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP6);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP5);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_PASS);
|
||||
break;
|
||||
default:
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, 0x00);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, 0x00);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, 0x00);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, 0x00);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x00);
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_SW_CTRL, sw_ctrl);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable cross switch configuration */
|
||||
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_SW_CTRL, sw_ctrl);
|
||||
|
||||
return err_count;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate whether the requested USB Type-C connector pin assignment
|
||||
* is supported by the CBTL08GP053.
|
||||
* @param Mode USB Type-C connector pin assignment
|
||||
* @retval 0: success, else error
|
||||
*/
|
||||
uint32_t cbtl08gp053_IsSupportedMode(TYPECSWITCH_Mode_t Mode)
|
||||
{
|
||||
return (((1 << Mode) & cbtl08gp053_SupportedModes ) == 0) ? 0 : 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,369 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file cbtl08gp053.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the CBTL08GP053
|
||||
* (Crossbar switch device for USB Type-C systems).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __CBTL08GP053_H
|
||||
#define __CBTL08GP053_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
#include "../Common/usbtypecswitch.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CBTL08GP053
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef DBG_BSP_MUX
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RESERVED1; /*!< Address offset: 0x00 */
|
||||
uint8_t SYS_CTRL; /*!< Address offset: 0x01 */
|
||||
uint8_t OP1_CTRL; /*!< Address offset: 0x02 */
|
||||
uint8_t OP2_CTRL; /*!< Address offset: 0x03 */
|
||||
uint8_t OP3_CTRL; /*!< Address offset: 0x04 */
|
||||
uint8_t OP4_CTRL; /*!< Address offset: 0x05 */
|
||||
uint8_t OP5_CTRL; /*!< Address offset: 0x06 */
|
||||
uint8_t CROSS5_CTRL; /*!< Address offset: 0x07 */
|
||||
uint8_t SW_CTRL; /*!< Address offset: 0x08 */
|
||||
uint8_t REVISION; /*!< Address offset: 0x09 */
|
||||
} CBTL08GP053_TypeDef;
|
||||
|
||||
extern CBTL08GP053_TypeDef CBTL08GP053;
|
||||
#endif /* DBG_BSP_MUX */
|
||||
|
||||
/** @defgroup CBTL08GP053_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
/******************************* Register Map ********************************/
|
||||
#define CBTL08GP053_REG_SYS_CTRL 0x01 /*!< */
|
||||
#define CBTL08GP053_REG_OP1_CTRL 0x02 /*!< */
|
||||
#define CBTL08GP053_REG_OP2_CTRL 0x03 /*!< */
|
||||
#define CBTL08GP053_REG_OP3_CTRL 0x04 /*!< */
|
||||
#define CBTL08GP053_REG_OP4_CTRL 0x05 /*!< */
|
||||
#define CBTL08GP053_REG_OP5_CTRL 0x06 /*!< */
|
||||
#define CBTL08GP053_REG_CROSS5_CTRL 0x07 /*!< */
|
||||
#define CBTL08GP053_REG_SW_CTRL 0x08 /*!< */
|
||||
#define CBTL08GP053_REG_REVISION 0x09 /*!< */
|
||||
|
||||
/********************* Bit definition for SYS_CTRL register *****************/
|
||||
#define CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Pos (7U)
|
||||
#define CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Msk (0x1U << CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Pos) /*!< 0x80*/
|
||||
#define CBTL08GP053_REG_SYS_CTRL_SWITCH_EN CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Msk /*!< */
|
||||
|
||||
/********************* Bit definition for OP1_CTRL register *****************/
|
||||
#define CBTL08GP053_REG_OP1_CTRL_EN_IP1_Pos (0U)
|
||||
#define CBTL08GP053_REG_OP1_CTRL_EN_IP1_Msk (0x1U << CBTL08GP053_REG_OP1_CTRL_EN_IP1_Pos) /*!< 0x01 */
|
||||
#define CBTL08GP053_REG_OP1_CTRL_EN_IP1 CBTL08GP053_REG_OP1_CTRL_EN_IP1_Msk /*!< */
|
||||
#define CBTL08GP053_REG_OP1_CTRL_EN_IP2_Pos (1U)
|
||||
#define CBTL08GP053_REG_OP1_CTRL_EN_IP2_Msk (0x1U << CBTL08GP053_REG_OP1_CTRL_EN_IP2_Pos) /*!< 0x02 */
|
||||
#define CBTL08GP053_REG_OP1_CTRL_EN_IP2 CBTL08GP053_REG_OP1_CTRL_EN_IP2_Msk /*!< */
|
||||
#define CBTL08GP053_REG_OP1_CTRL_EN_IP3_Pos (2U)
|
||||
#define CBTL08GP053_REG_OP1_CTRL_EN_IP3_Msk (0x1U << CBTL08GP053_REG_OP1_CTRL_EN_IP3_Pos) /*!< 0x04 */
|
||||
#define CBTL08GP053_REG_OP1_CTRL_EN_IP3 CBTL08GP053_REG_OP1_CTRL_EN_IP3_Msk /*!< */
|
||||
|
||||
/********************* Bit definition for OP2_CTRL register *****************/
|
||||
#define CBTL08GP053_REG_OP2_CTRL_EN_IP1_Pos (0U)
|
||||
#define CBTL08GP053_REG_OP2_CTRL_EN_IP1_Msk (0x1U << CBTL08GP053_REG_OP2_CTRL_EN_IP1_Pos) /*!< 0x01 */
|
||||
#define CBTL08GP053_REG_OP2_CTRL_EN_IP1 CBTL08GP053_REG_OP2_CTRL_EN_IP1_Msk /*!< */
|
||||
#define CBTL08GP053_REG_OP2_CTRL_EN_IP2_Pos (1U)
|
||||
#define CBTL08GP053_REG_OP2_CTRL_EN_IP2_Msk (0x1U << CBTL08GP053_REG_OP2_CTRL_EN_IP2_Pos) /*!< 0x02 */
|
||||
#define CBTL08GP053_REG_OP2_CTRL_EN_IP2 CBTL08GP053_REG_OP2_CTRL_EN_IP2_Msk /*!< */
|
||||
#define CBTL08GP053_REG_OP2_CTRL_EN_IP3_Pos (2U)
|
||||
#define CBTL08GP053_REG_OP2_CTRL_EN_IP3_Msk (0x1U << CBTL08GP053_REG_OP2_CTRL_EN_IP3_Pos) /*!< 0x04 */
|
||||
#define CBTL08GP053_REG_OP2_CTRL_EN_IP3 CBTL08GP053_REG_OP2_CTRL_EN_IP3_Msk /*!< */
|
||||
|
||||
/********************* Bit definition for OP3_CTRL register *****************/
|
||||
#define CBTL08GP053_REG_OP3_CTRL_EN_IP4_Pos (3U)
|
||||
#define CBTL08GP053_REG_OP3_CTRL_EN_IP4_Msk (0x1U << CBTL08GP053_REG_OP3_CTRL_EN_IP4_Pos) /*!< 0x08 */
|
||||
#define CBTL08GP053_REG_OP3_CTRL_EN_IP4 CBTL08GP053_REG_OP3_CTRL_EN_IP4_Msk /*!< */
|
||||
#define CBTL08GP053_REG_OP3_CTRL_EN_IP5_Pos (4U)
|
||||
#define CBTL08GP053_REG_OP3_CTRL_EN_IP5_Msk (0x1U << CBTL08GP053_REG_OP3_CTRL_EN_IP5_Pos) /*!< 0x10 */
|
||||
#define CBTL08GP053_REG_OP3_CTRL_EN_IP5 CBTL08GP053_REG_OP3_CTRL_EN_IP5_Msk /*!< */
|
||||
#define CBTL08GP053_REG_OP3_CTRL_EN_IP6_Pos (5U)
|
||||
#define CBTL08GP053_REG_OP3_CTRL_EN_IP6_Msk (0x1U << CBTL08GP053_REG_OP3_CTRL_EN_IP6_Pos) /*!< 0x20 */
|
||||
#define CBTL08GP053_REG_OP3_CTRL_EN_IP6 CBTL08GP053_REG_OP3_CTRL_EN_IP6_Msk /*!< */
|
||||
|
||||
/********************* Bit definition for OP4_CTRL register *****************/
|
||||
#define CBTL08GP053_REG_OP4_CTRL_EN_IP4_Pos (3U)
|
||||
#define CBTL08GP053_REG_OP4_CTRL_EN_IP4_Msk (0x1U << CBTL08GP053_REG_OP4_CTRL_EN_IP4_Pos) /*!< 0x08 */
|
||||
#define CBTL08GP053_REG_OP4_CTRL_EN_IP4 CBTL08GP053_REG_OP4_CTRL_EN_IP4_Msk /*!< */
|
||||
#define CBTL08GP053_REG_OP4_CTRL_EN_IP5_Pos (4U)
|
||||
#define CBTL08GP053_REG_OP4_CTRL_EN_IP5_Msk (0x1U << CBTL08GP053_REG_OP4_CTRL_EN_IP5_Pos) /*!< 0x10 */
|
||||
#define CBTL08GP053_REG_OP4_CTRL_EN_IP5 CBTL08GP053_REG_OP4_CTRL_EN_IP5_Msk /*!< */
|
||||
#define CBTL08GP053_REG_OP4_CTRL_EN_IP6_Pos (5U)
|
||||
#define CBTL08GP053_REG_OP4_CTRL_EN_IP6_Msk (0x1U << CBTL08GP053_REG_OP4_CTRL_EN_IP6_Pos) /*!< 0x20 */
|
||||
#define CBTL08GP053_REG_OP4_CTRL_EN_IP6 CBTL08GP053_REG_OP4_CTRL_EN_IP6_Msk /*!< */
|
||||
|
||||
/********************* Bit definition for OP5_CTRL register *****************/
|
||||
#define CBTL08GP053_REG_OP5_CTRL_EN_IP7_Pos (6U)
|
||||
#define CBTL08GP053_REG_OP5_CTRL_EN_IP7_Msk (0x1U << CBTL08GP053_REG_OP5_CTRL_EN_IP7_Pos) /*!< 0x40 */
|
||||
#define CBTL08GP053_REG_OP5_CTRL_EN_IP7 CBTL08GP053_REG_OP5_CTRL_EN_IP7_Msk /*!< */
|
||||
#define CBTL08GP053_REG_OP5_CTRL_EN_IP8_Pos (7U)
|
||||
#define CBTL08GP053_REG_OP5_CTRL_EN_IP8_Msk (0x1U << CBTL08GP053_REG_OP5_CTRL_EN_IP8_Pos) /*!< 0x80 */
|
||||
#define CBTL08GP053_REG_OP5_CTRL_EN_IP8 CBTL08GP053_REG_OP5_CTRL_EN_IP8_Msk /*!< */
|
||||
|
||||
/****************** Bit definition for CROSS5_CTRL register *****************/
|
||||
#define CBTL08GP053_REG_CROSS5_PASS_Pos (0U)
|
||||
#define CBTL08GP053_REG_CROSS5_PASS_Msk (0x1U << CBTL08GP053_REG_CROSS5_PASS_Pos) /*!< 0x01 */
|
||||
#define CBTL08GP053_REG_CROSS5_PASS CBTL08GP053_REG_CROSS5_PASS_Msk /*!< */
|
||||
#define CBTL08GP053_REG_CROSS5_CROSS_Pos (1U)
|
||||
#define CBTL08GP053_REG_CROSS5_CROSS_Msk (0x1U << CBTL08GP053_REG_CROSS5_CROSS_Pos) /*!< 0x02 */
|
||||
#define CBTL08GP053_REG_CROSS5_CROSS CBTL08GP053_REG_CROSS5_CROSS_Msk /*!< */
|
||||
|
||||
/******************* Bit definition for SW_CTRL register ********************/
|
||||
#define CBTL08GP053_REG_SW_OP1_SET_Pos (0U)
|
||||
#define CBTL08GP053_REG_SW_OP1_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP1_SET_Pos) /*!< 0x01 */
|
||||
#define CBTL08GP053_REG_SW_OP1_SET CBTL08GP053_REG_SW_OP1_SET_Msk /*!< */
|
||||
#define CBTL08GP053_REG_SW_OP2_SET_Pos (1U)
|
||||
#define CBTL08GP053_REG_SW_OP2_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP2_SET_Pos) /*!< 0x02 */
|
||||
#define CBTL08GP053_REG_SW_OP2_SET CBTL08GP053_REG_SW_OP2_SET_Msk /*!< */
|
||||
#define CBTL08GP053_REG_SW_OP3_SET_Pos (2U)
|
||||
#define CBTL08GP053_REG_SW_OP3_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP3_SET_Pos) /*!< 0x04 */
|
||||
#define CBTL08GP053_REG_SW_OP3_SET CBTL08GP053_REG_SW_OP3_SET_Msk /*!< */
|
||||
#define CBTL08GP053_REG_SW_OP4_SET_Pos (3U)
|
||||
#define CBTL08GP053_REG_SW_OP4_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP4_SET_Pos) /*!< 0x08 */
|
||||
#define CBTL08GP053_REG_SW_OP4_SET CBTL08GP053_REG_SW_OP4_SET_Msk /*!< */
|
||||
#define CBTL08GP053_REG_SW_OP5_SET_Pos (4U)
|
||||
#define CBTL08GP053_REG_SW_OP5_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP5_SET_Pos) /*!< 0x10 */
|
||||
#define CBTL08GP053_REG_SW_OP5_SET CBTL08GP053_REG_SW_OP5_SET_Msk /*!< */
|
||||
#define CBTL08GP053_REG_SW_X5_SET_Pos (5U)
|
||||
#define CBTL08GP053_REG_SW_X5_SET_Msk (0x1U << CBTL08GP053_REG_SW_X5_SET_Pos) /*!< 0x20 */
|
||||
#define CBTL08GP053_REG_SW_X5_SET CBTL08GP053_REG_SW_X5_SET_Msk /*!< */
|
||||
|
||||
/******************** Bit definition for REVISION register ******************/
|
||||
#define CBTL08GP053_REVISION_REV_ID_Pos (0U)
|
||||
#define CBTL08GP053_REVISION_REV_ID_Msk (0xFFU << CBTL08GP053_REVISION_REV_ID_Pos) /*!< 0xFF */
|
||||
#define CBTL08GP053_REVISION_REV_ID CBTL08GP053_REVISION_REV_ID_Msk /*!< */
|
||||
|
||||
/** @defgroup CBTL08GP053_DisplayPort_Alternate_Mode
|
||||
* @{
|
||||
*/
|
||||
#define CBTL08GP053_DP_ALTMODE_DFP_D_C_E_NORMAL 0x00U
|
||||
#define CBTL08GP053_DP_ALTMODE_DFP_D_C_E_FLIPPED 0x01U
|
||||
#define CBTL08GP053_DP_ALTMODE_DFP_D_D_F_NORMAL 0x02U
|
||||
#define CBTL08GP053_DP_ALTMODE_DFP_D_D_F_FLIPPED 0x03U
|
||||
#define CBTL08GP053_DP_ALTMODE_UFP_D_C_NORMAL 0x04U
|
||||
#define CBTL08GP053_DP_ALTMODE_UFP_D_C_FLIPPED 0x05U
|
||||
#define CBTL08GP053_DP_ALTMODE_UFP_D_D_NORMAL 0x06U
|
||||
#define CBTL08GP053_DP_ALTMODE_UFP_D_D_FLIPPED 0x07U
|
||||
#define CBTL08GP053_DP_ALTMODE_UFP_D_E_NORMAL 0x08U
|
||||
#define CBTL08GP053_DP_ALTMODE_UFP_D_E_FLIPPED 0x09U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CBTL08GP053_DisplayPort_Standby_Mode
|
||||
* @{
|
||||
*/
|
||||
#define CBTL08GP053_DP_STANDBYMODE_SAFE 0x00U
|
||||
#define CBTL08GP053_DP_STANDBYMODE_USB3_NORMAL 0x01U
|
||||
#define CBTL08GP053_DP_STANDBYMODE_USB3_FLIPPED 0x02U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(CBTL08GP053_DEBUG)
|
||||
/** @defgroup CBTL08GP053_Exported_Structure CBTL08GP053 Exported Structure
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RESERVED :7;
|
||||
uint8_t SWITCH_EN :1;
|
||||
};
|
||||
} CBTL08GP053_SysCtrlTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t IP1 :1;
|
||||
uint8_t IP2 :1;
|
||||
uint8_t IP3 :1;
|
||||
uint8_t RESERVED :5;
|
||||
};
|
||||
} CBTL08GP053_Op1CtrlTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t IP1 :1;
|
||||
uint8_t IP2 :1;
|
||||
uint8_t IP3 :1;
|
||||
uint8_t RESERVED :5;
|
||||
};
|
||||
} CBTL08GP053_Op2CtrlTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RESERVED1 :3;
|
||||
uint8_t IP4 :1;
|
||||
uint8_t IP5 :1;
|
||||
uint8_t IP6 :1;
|
||||
uint8_t RESERVED2 :2;
|
||||
};
|
||||
} CBTL08GP053_Op3CtrlTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RESERVED1 :3;
|
||||
uint8_t IP4 :1;
|
||||
uint8_t IP5 :1;
|
||||
uint8_t IP6 :1;
|
||||
uint8_t RESERVED2 :2;
|
||||
};
|
||||
} CBTL08GP053_Op4CtrlTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RESERVED :6;
|
||||
uint8_t IP7 :1;
|
||||
uint8_t IP8 :1;
|
||||
};
|
||||
} CBTL08GP053_Op5CtrlTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t PASS :1;
|
||||
uint8_t CROSS :1;
|
||||
uint8_t RESERVED :6;
|
||||
};
|
||||
} CBTL08GP053_Cross5CtrlTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t OP1_SET :1;
|
||||
uint8_t OP2_SET :1;
|
||||
uint8_t OP3_SET :1;
|
||||
uint8_t OP4_SET :1;
|
||||
uint8_t OP5_SET :1;
|
||||
uint8_t X5_SET :1;
|
||||
uint8_t RESERVED :2;
|
||||
};
|
||||
} CBTL08GP053_SwCtrlTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
CBTL08GP053_SysCtrlTypeDef SysCtrl; /*!< SYS_CTRL register (0x01) */
|
||||
CBTL08GP053_Op1CtrlTypeDef Op1Ctrl; /*!< OP1_CTRL Registers (0x02) */
|
||||
CBTL08GP053_Op2CtrlTypeDef Op2Ctrl; /*!< OP2_CTRL Registers (0x03) */
|
||||
CBTL08GP053_Op3CtrlTypeDef Op3Ctrl; /*!< OP3_CTRL Registers (0x04) */
|
||||
CBTL08GP053_Op4CtrlTypeDef Op4Ctrl; /*!< OP4_CTRL Registers (0x05) */
|
||||
CBTL08GP053_Op5CtrlTypeDef Op5Ctrl; /*!< OP5_CTRL Registers (0x06) */
|
||||
CBTL08GP053_Cross5CtrlTypeDef Cross5Ctrl; /*!< CROSS5_CTRL Registers (0x07) */
|
||||
CBTL08GP053_SwCtrlTypeDef SwCtrl; /*!< SW_CTRL Registers (0x08) */
|
||||
uint8_t Revision; /*!< REVISION Registers (0x09) */
|
||||
} CBTL08GP053_RegistersTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CBTL08GP053_DEBUG */
|
||||
|
||||
/** @defgroup CBTL08GP053_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* USB Type-C Crosspoint Switch management functions */
|
||||
uint32_t cbtl08gp053_Init(uint16_t Address);
|
||||
void cbtl08gp053_DeInit(uint16_t Address);
|
||||
uint32_t cbtl08gp053_PowerOn(uint16_t Address);
|
||||
uint32_t cbtl08gp053_PowerOff(uint16_t Address);
|
||||
uint32_t cbtl08gp053_SetMode(uint16_t Address, TYPECSWITCH_Mode_t Mode);
|
||||
uint32_t cbtl08gp053_IsSupportedMode(TYPECSWITCH_Mode_t Mode);
|
||||
|
||||
/* MUX IO functions */
|
||||
uint8_t MUX_IO_Init(void);
|
||||
void MUX_IO_DeInit(void);
|
||||
uint8_t MUX_IO_Write(uint16_t Addr, uint16_t Reg, uint8_t Data);
|
||||
uint8_t MUX_IO_Read(uint16_t Addr, uint16_t Reg, uint8_t *pData);
|
||||
uint32_t MUX_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CBTL08GP053_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/* Type-C Crosspoint Switch Driver */
|
||||
extern TYPECSWITCH_Drv_t cbtl08gp053_drv;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CBTL08GP053_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Loading…
Add table
Add a link
Reference in a new issue