346 lines
9 KiB
C
346 lines
9 KiB
C
/**
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******************************************************************************
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* @file sn65dp141.c
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* @author MCD Application Team
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* @brief This file provides a set of functions needed to manage the SN65DP141
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* DisplayPort Linear Redriver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "sn65dp141.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Components
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* @{
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*/
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/** @defgroup SN65DP141
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* @brief This file provides a set of functions needed to drive the
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* SN65DP141 DisplayPort Linear Redriver.
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* @{
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*/
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/** @defgroup SN65DP141_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup SN65DP141_Private_Defines
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup SN65DP141_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup SN65DP141_Private_Variables
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* @{
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*/
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/* DisplayPort Linear Redriver Driver structure initialization */
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DPREDRIVER_Drv_t sn65dp141_drv =
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{
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sn65dp141_Init,
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sn65dp141_DeInit,
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sn65dp141_PowerOn,
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sn65dp141_PowerOff,
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sn65dp141_SetEQGain,
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sn65dp141_EnableChannel,
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sn65dp141_DisableChannel
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};
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/**
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* @}
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*/
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/** @defgroup SN65DP141_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup SN65DP141_Private_Functions
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* @{
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*/
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/**
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* @brief Initialize the SN65DP141 and configure the needed hardware resources.
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* @param Address Device address on communication Bus.
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* @retval None
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*/
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uint32_t sn65dp141_Init(uint16_t Address)
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{
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uint32_t err_count = 0;
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/* Low level init */
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err_count += MUX_IO_Init();
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/* Restore SN65DP141 registers reset values */
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CFG, 0x00);
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CHEN, 0x00);
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CH0_CFG, 0x00);
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CH0_EN, 0x00);
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CH1_CFG, 0x00);
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CH1_EN, 0x00);
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CH2_CFG, 0x00);
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CH2_EN, 0x00);
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CH3_CFG, 0x00);
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CH3_EN, 0x00);
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return err_count;
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}
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/**
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* @brief Release the hardware resources required to use the SN65DP141
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* @param Address SN65DP141 address on communication Bus.
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* @retval none
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*/
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void sn65dp141_DeInit(uint16_t Address)
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{
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/* Restore SN65DP141 registers reset values */
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MUX_IO_Write(Address, SN65DP141_REG_CFG, 0x00);
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MUX_IO_Write(Address, SN65DP141_REG_CHEN, 0x00);
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MUX_IO_Write(Address, SN65DP141_REG_CH0_CFG, 0x00);
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MUX_IO_Write(Address, SN65DP141_REG_CH0_EN, 0x00);
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MUX_IO_Write(Address, SN65DP141_REG_CH1_CFG, 0x00);
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MUX_IO_Write(Address, SN65DP141_REG_CH1_EN, 0x00);
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MUX_IO_Write(Address, SN65DP141_REG_CH2_CFG, 0x00);
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MUX_IO_Write(Address, SN65DP141_REG_CH2_EN, 0x00);
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MUX_IO_Write(Address, SN65DP141_REG_CH3_CFG, 0x00);
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MUX_IO_Write(Address, SN65DP141_REG_CH3_EN, 0x00);
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/* Low level de-init */
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MUX_IO_DeInit();
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}
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/**
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* @brief Power on the SN65DP141.
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* @param Address SN65DP141 address on communication Bus.
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* @retval 0: successful, else failed
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*/
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uint32_t sn65dp141_PowerOn(uint16_t Address)
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{
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uint32_t err_count = 0;
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uint8_t cfg;
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/* Read General Device Settings register*/
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err_count += MUX_IO_Read(Address, SN65DP141_REG_CFG, &cfg);
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/* Clear PWRDOWN bit of General Device Settings register */
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cfg &= ~SN65DP141_REG_CFG_PWRDOWN;
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CFG, cfg);
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return err_count;
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}
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/**
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* @brief Power down the SN65DP141.
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* @param Address SN65DP141 address on communication Bus.
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* @retval 0: successful, else failed
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*/
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uint32_t sn65dp141_PowerOff(uint16_t Address)
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{
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uint32_t err_count = 0;
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uint8_t cfg;
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/* Read General Device Settings register*/
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err_count += MUX_IO_Read(Address, SN65DP141_REG_CFG, &cfg);
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/* Set PWRDOWN bit of General Device Settings register */
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cfg |= SN65DP141_REG_CFG_PWRDOWN;
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CFG, cfg);
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return err_count;
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}
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/**
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* @brief Set the equalizer gain for a given channel.
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* @param Address SN65DP141 address on communication Bus.
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* @param ChannelId Channel identifier.
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* This parameter can be take one of the following values:
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* CHANNEL_DP0
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* CHANNEL_DP1
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* CHANNEL_DP2
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* CHANNEL_DP3
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* @param EQGain Equalizer gain.
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* This parameter must be a value between 0x00 and 0x07.
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* @retval 0: successful, else failed
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*/
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uint32_t sn65dp141_SetEQGain(uint16_t Address,
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DPREDRIVER_ChannelId_t ChannelId,
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uint8_t EQGain)
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{
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uint32_t err_count = 0;
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uint8_t chctrl;
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uint8_t cfg;
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switch(ChannelId)
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{
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case CHANNEL_DP0:
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cfg = SN65DP141_REG_CH0_CFG;
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break;
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case CHANNEL_DP1:
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cfg = SN65DP141_REG_CH1_CFG;
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break;
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case CHANNEL_DP2:
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cfg = SN65DP141_REG_CH2_CFG;
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break;
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case CHANNEL_DP3:
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cfg = SN65DP141_REG_CH3_CFG;
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break;
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default:
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cfg = SN65DP141_REG_CH0_CFG;
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break;
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}
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/* Read Channel x Control Settings register */
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err_count += MUX_IO_Read(Address, cfg, &chctrl);
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/* Set the equalizer gain bit field (EQ setting) for concerned channel */
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chctrl = (chctrl & (~(uint8_t)SN65DP141_REG_CHxCFG_EQ_SETTING_Msk)) | (EQGain << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos);
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/* Enable Max gain for TX & RX */
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chctrl |= SN65DP141_REG_CHxCFG_RX_GAIN_1 | SN65DP141_REG_CHxCFG_EQ_DC_GAIN | SN65DP141_REG_CHxCFG_TX_GAIN;
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/* Update Channel x Control Settings register */
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err_count += MUX_IO_Write(Address, cfg, chctrl);
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return err_count;
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}
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/**
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* @brief Enable a DP channel.
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* @param Address SN65DP141 address on communication Bus.
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* @param ChannelId Channel identifier.
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* This parameter can be take one of the following values:
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* CHANNEL_DP0
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* CHANNEL_DP1
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* CHANNEL_DP2
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* CHANNEL_DP3
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* @retval 0: successful, else failed
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*/
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uint32_t sn65dp141_EnableChannel(uint16_t Address,
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DPREDRIVER_ChannelId_t ChannelId)
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{
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uint32_t err_count = 0;
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uint8_t chen;
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/* Read Channel Enable register */
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err_count += MUX_IO_Read(Address, SN65DP141_REG_CHEN, &chen);
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/* Clear LN_EN_CHx bit of Channel Enable register */
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switch(ChannelId)
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{
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case CHANNEL_DP0:
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chen &= ~SN65DP141_REG_CHEN_LN_EN_CH0;
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break;
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case CHANNEL_DP1:
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chen &= ~SN65DP141_REG_CHEN_LN_EN_CH1;
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break;
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case CHANNEL_DP2:
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chen &= ~SN65DP141_REG_CHEN_LN_EN_CH2;
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break;
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case CHANNEL_DP3:
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chen &= ~SN65DP141_REG_CHEN_LN_EN_CH3;
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break;
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default:
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/* Nothing to do */
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break;
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}
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CHEN, chen);
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return err_count;
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}
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/**
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* @brief Disable a DP channel.
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* @param Address SN65DP141 address on communication Bus.
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* @param ChannelId Channel identifier.
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* This parameter can be take one of the following values:
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* CHANNEL_DP0
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* CHANNEL_DP1
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* CHANNEL_DP2
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* CHANNEL_DP3
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* @retval 0: successful, else failed
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*/
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uint32_t sn65dp141_DisableChannel(uint16_t Address,
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DPREDRIVER_ChannelId_t ChannelId)
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{
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uint32_t err_count = 0;
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uint8_t chen;
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/* Read Channel Enable register */
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err_count += MUX_IO_Read(Address, SN65DP141_REG_CHEN, &chen);
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/* Set LN_EN_CHx bit of Channel Enable register */
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switch(ChannelId)
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{
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case CHANNEL_DP0:
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chen |= SN65DP141_REG_CHEN_LN_EN_CH0;
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break;
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case CHANNEL_DP1:
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chen |= SN65DP141_REG_CHEN_LN_EN_CH1;
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break;
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case CHANNEL_DP2:
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chen |= SN65DP141_REG_CHEN_LN_EN_CH2;
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break;
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case CHANNEL_DP3:
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chen |= SN65DP141_REG_CHEN_LN_EN_CH3;
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break;
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default:
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/* Nothing to do */
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break;
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}
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err_count += MUX_IO_Write(Address, SN65DP141_REG_CHEN, chen);
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return err_count;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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