395 lines
15 KiB
C
395 lines
15 KiB
C
/**
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******************************************************************************
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* @file sn65dp141.h
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* @author MCD Application Team
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* @brief Header for sn65dp141.h module
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef SN65DP141_H
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#define SN65DP141_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include <stdint.h>
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#include "../Common/dpredriver.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Components
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* @{
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*/
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/** @addtogroup SN65DP141
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* @{
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*/
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/** @defgroup SN65DP141_Exported_Constants
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* @{
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*/
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/******************************* Register Map ********************************/
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#define SN65DP141_REG_CFG 0x00 /*!< General Device Settings register */
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#define SN65DP141_REG_CHEN 0x01 /*!< Channel Enable register */
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#define SN65DP141_REG_CH0_CFG 0x02 /*!< Channel 0 Control Settings register */
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#define SN65DP141_REG_CH0_EN 0x03 /*!< Channel 0 Enable Settings register */
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#define SN65DP141_REG_CH1_CFG 0x05 /*!< Channel 1 Control Settings register */
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#define SN65DP141_REG_CH1_EN 0x06 /*!< Channel 1 Enable Settings register */
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#define SN65DP141_REG_CH2_CFG 0x08 /*!< Channel 2 Control Settings register */
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#define SN65DP141_REG_CH2_EN 0x09 /*!< Channel 2 Enable Settings register */
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#define SN65DP141_REG_CH3_CFG 0x0B /*!< Channel 3 Control Settings register */
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#define SN65DP141_REG_CH3_EN 0x0C /*!< Channel 3 Enable Settings register */
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/*********** Bit definition for General Device Settings register *************/
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#define SN65DP141_REG_CFG_EQ_MODE_Pos (1U)
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#define SN65DP141_REG_CFG_EQ_MODE_Msk (0x1U << SN65DP141_REG_CFG_EQ_MODE_Pos) /*!< 0x04*/
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#define SN65DP141_REG_CFG_EQ_MODE SN65DP141_REG_CFG_EQ_MODE_Msk /*!< EQ mode (Cable mode v.s. Trace mode) */
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#define SN65DP141_REG_CFG_SYNC_ALL_Pos (3U)
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#define SN65DP141_REG_CFG_SYNC_ALL_Msk (0x1U << SN65DP141_REG_CFG_SYNC_ALL_Pos) /*!< 0x08*/
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#define SN65DP141_REG_CFG_SYNC_ALL SN65DP141_REG_CFG_SYNC_ALL_Msk /*!< All settings from channel 1 will be used on all channels */
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#define SN65DP141_REG_CFG_SYNC_23_Pos (4U)
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#define SN65DP141_REG_CFG_SYNC_23_Msk (0x1U << SN65DP141_REG_CFG_SYNC23_Pos) /*!< 0x10*/
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#define SN65DP141_REG_CFG_SYNC_23 SN65DP141_REG_CFG_SYNC_23_Msk /*!< All settings from channel 2 will be used for channel 2 and 3 */
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#define SN65DP141_REG_CFG_SYNC_01_Pos (5U)
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#define SN65DP141_REG_CFG_SYNC_01_Msk (0x1U << SN65DP141_REG_CFG_SYNC01_Pos) /*!< 0x20*/
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#define SN65DP141_REG_CFG_SYNC_01 SN65DP141_REG_CFG_SYNC_01_Msk /*!< All settings from channel 1 will be used for channel 0 and 1 */
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#define SN65DP141_REG_CFG_PWRDOWN_Pos (6U)
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#define SN65DP141_REG_CFG_PWRDOWN_Msk (0x1U << SN65DP141_REG_CFG_PWRDOWN_Pos) /*!< 0x40*/
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#define SN65DP141_REG_CFG_PWRDOWN SN65DP141_REG_CFG_PWRDOWN_Msk /*!< Power down the device */
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#define SN65DP141_REG_CFG_SW_GPIO_Pos (7U)
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#define SN65DP141_REG_CFG_SW_GPIO_Msk (0x1U << SN65DP141_REG_CFG_SW_GPIO_Pos) /*!< 0x80*/
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#define SN65DP141_REG_CFG_SW_GPIO SN65DP141_REG_CFG_SW_GPIO_Msk /*!< Switching logic is controlled by GPIO or I2C */
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/*********** Bit definition for Channel Enable register *************/
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#define SN65DP141_REG_CHEN_LN_EN_CH0_Pos (0U)
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#define SN65DP141_REG_CHEN_LN_EN_CH0_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH0_Pos) /*!< 0x01 */
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#define SN65DP141_REG_CHEN_LN_EN_CH0 SN65DP141_REG_CHEN_LN_EN_CH0_Msk /*!< Channel 0 enable */
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#define SN65DP141_REG_CHEN_LN_EN_CH1_Pos (1U)
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#define SN65DP141_REG_CHEN_LN_EN_CH1_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH1_Pos) /*!< 0x02 */
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#define SN65DP141_REG_CHEN_LN_EN_CH1 SN65DP141_REG_CHEN_LN_EN_CH1_Msk /*!< Channel 1 enable */
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#define SN65DP141_REG_CHEN_LN_EN_CH2_Pos (2U)
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#define SN65DP141_REG_CHEN_LN_EN_CH2_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH2_Pos) /*!< 0x04 */
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#define SN65DP141_REG_CHEN_LN_EN_CH2 SN65DP141_REG_CHEN_LN_EN_CH2_Msk /*!< Channel 2 enable */
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#define SN65DP141_REG_CHEN_LN_EN_CH3_Pos (3U)
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#define SN65DP141_REG_CHEN_LN_EN_CH3_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH3_Pos) /*!< 0x08 */
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#define SN65DP141_REG_CHEN_LN_EN_CH3 SN65DP141_REG_CHEN_LN_EN_CH3_Msk /*!< Channel 3 enable */
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/*********** Bit definition for Channel x Control Settings register *************/
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#define SN65DP141_REG_CHxCFG_RX_GAIN_Pos (0U)
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#define SN65DP141_REG_CHxCFG_RX_GAIN_Msk (0x3U << SN65DP141_REG_CHxCFG_RX_GAIN_Pos) /*!< 0x03 */
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#define SN65DP141_REG_CHxCFG_RX_GAIN SN65DP141_REG_CHxCFG_RX_GAIN_Msk /*!< Channel[x] RX_GAIN control */
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#define SN65DP141_REG_CHxCFG_RX_GAIN_0 (0x1U << SN65DP141_REG_CHxCFG_RX_GAIN_Pos) /*!< 0x01 */
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#define SN65DP141_REG_CHxCFG_RX_GAIN_1 (0x2U << SN65DP141_REG_CHxCFG_RX_GAIN_Pos) /*!< 0x02 */
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#define SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Pos (2U)
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#define SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Msk (0x1U << SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Pos) /*!< 0x04 */
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#define SN65DP141_REG_CHxCFG_EQ_DC_GAIN SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Msk /*!< Channel[x] EQ DC gain */
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#define SN65DP141_REG_CHxCFG_TX_GAIN_Pos (3U)
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#define SN65DP141_REG_CHxCFG_TX_GAIN_Msk (0x1U << SN65DP141_REG_CHxCFG_TX_GAIN_Pos) /*!< 0x08 */
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#define SN65DP141_REG_CHxCFG_TX_GAIN SN65DP141_REG_CHxCFG_TX_GAIN_Msk /*!< Channel[x] TX_DC_GAIN control */
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#define SN65DP141_REG_CHxCFG_EQ_SETTING_Pos (4U)
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#define SN65DP141_REG_CHxCFG_EQ_SETTING_Msk (0x7U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x70 */
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#define SN65DP141_REG_CHxCFG_EQ_SETTING SN65DP141_REG_CHxCFG_EQ_SETTING_Msk /*!< Channel[x] TX_DC_GAIN control */
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#define SN65DP141_REG_CHxCFG_EQ_SETTING_0 (0x1U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x10 */
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#define SN65DP141_REG_CHxCFG_EQ_SETTING_1 (0x2U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x20 */
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#define SN65DP141_REG_CHxCFG_EQ_SETTING_2 (0x4U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x40 */
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/*********** Bit definition for Channel x Enable Settings register *************/
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#define SN65DP141_REG_CHxCTL_DRV_EN_Pos (0U)
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#define SN65DP141_REG_CHxCTL_DRV_EN_Msk (0x1U << SN65DP141_REG_CHxCTL_DRV_EN_Pos) /*!< 0x01 */
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#define SN65DP141_REG_CHxCTL_DRV_EN SN65DP141_REG_CHxCTL_DRV_EN_Msk /*!< Channel[0] driver stage enable */
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#define SN65DP141_REG_CHxCTL_EQ_EN_Pos (1U)
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#define SN65DP141_REG_CHxCTL_EQ_EN_Msk (0x1U << SN65DP141_REG_CHxCTL_EQ_EN_Pos) /*!< 0x02 */
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#define SN65DP141_REG_CHxCTL_EQ_EN SN65DP141_REG_CHxCTL_EQ_EN_Msk /*!< Channel[0] EQ stage enable */
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#define SN65DP141_REG_CHxCTL_DRV_PEAK_Pos (2U)
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#define SN65DP141_REG_CHxCTL_DRV_PEAK_Msk (0x1U << SN65DP141_REG_CHxCTL_DRV_PEAK_Pos) /*!< 0x04 */
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#define SN65DP141_REG_CHxCTL_DRV_PEAK SN65DP141_REG_CHxCTL_DRV_PEAK_Msk /*!< Channel[0] driver peaking */
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/** @defgroup SN65DP141_Channel_Identifier
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* @{
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*/
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#define SN65DP141_CHANNEL_1 0x00U
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#define SN65DP141_CHANNEL_2 0x01U
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#define SN65DP141_CHANNEL_3 0x04U
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#define SN65DP141_CHANNEL_4 0x08U
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#define SN65DP141_CHANNEL_ALL 0x0FU
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/**
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* @}
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*/
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/** @defgroup SN65DP141_EQ_Mode
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* @{
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*/
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#define SN65DP141_EQ_MODE_CABLE 0x00U
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#define SN65DP141_EQ_MODE_TRACE SN65DP141_REG_CFG_EQ_MODE
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/**
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* @}
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*/
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/** @defgroup SN65DP141_Channel_Tracking
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* @{
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*/
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#define SN65DP141_CHANNEL_TRACKING_NONE 0x00U
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#define SN65DP141_CHANNEL_TRACKING_01 SN65DP141_REG_CFG_SYNC_01
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#define SN65DP141_CHANNEL_TRACKING_23 SN65DP141_REG_CFG_SYNC_23
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#define SN65DP141_CHANNEL_TRACKING_ALL SN65DP141_REG_CFG_SYNC_ALL
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/**
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* @}
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*/
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/** @defgroup SN65DP141_EQGAIN SN65DP141 Equalizer Gain
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* @{
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*/
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#define SN65DP141_EQGAIN_0 0x0U
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#define SN65DP141_EQGAIN_1 0x1U
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#define SN65DP141_EQGAIN_2 0x2U
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#define SN65DP141_EQGAIN_3 0x3U
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#define SN65DP141_EQGAIN_4 0x4U
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#define SN65DP141_EQGAIN_5 0x5U
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#define SN65DP141_EQGAIN_6 0x6U
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#define SN65DP141_EQGAIN_7 0x7U
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/**
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* @}
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*/
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/** @defgroup SN65DP141_Channel_RXGAIN
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* @{
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*/
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#define SN65DP141_CHANNEL_RXGAIN_LOW 0x00U
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#define SN65DP141_CHANNEL_RXGAIN_HIZ SN65DP141_REG_CHxCFG_RX_GAIN_0
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#define SN65DP141_CHANNEL_RXGAIN_HIGH SN65DP141_REG_CHxCFG_RX_GAIN_1
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/**
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* @}
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*/
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/** @defgroup SN65DP141_Channel_EQDCGAIN
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* @{
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*/
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#define SN65DP141_CHANNEL_EQDCGAIN_MINUS6DB 0x00U
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#define SN65DP141_CHANNEL_EQDCGAIN_0DB SN65DP141_REG_CHxCFG_EQ_DC_GAIN
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/**
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* @}
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*/
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/** @defgroup SN65DP141_Channel_TXGAIN
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* @{
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*/
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#define SN65DP141_CHANNEL_RXGAIN_0DB 0x00U
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#define SN65DP141_CHANNEL_RXGAIN_6DB SN65DP141_REG_CHxCFG_TX_GAIN
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/**
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* @}
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*/
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/**
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* @}
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*/
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#if defined(SN65DP141_DEBUG)
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/** @defgroup SN65DP141_Exported_Structure SN65DP141 Exported Structure
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* @{
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*/
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RESERVED :2;
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uint8_t EQ_MODE :1;
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uint8_t SYNC_ALL :1;
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uint8_t SYNC_23 :1;
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uint8_t SYNC_01 :1;
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uint8_t PWRDOWN :1;
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uint8_t SW_GPIO :1;
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};
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} SN65DP141_GeneralTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t LN_EN_CH0 :1;
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uint8_t LN_EN_CH1 :1;
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uint8_t LN_EN_CH2 :1;
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uint8_t LN_EN_CH3 :1;
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uint8_t RESERVED :4;
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};
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} SN65DP141_ChannelEnableTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RX_GAIN_0 :1;
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uint8_t RX_GAIN_1 :1;
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uint8_t EQ_DC_GAIN :1;
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uint8_t TX_GAIN :1;
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uint8_t EQ_Setting_0 :1;
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uint8_t EQ_Setting_1 :1;
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uint8_t EQ_Setting_2 :1;
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uint8_t RESERVED :1;
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};
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} SN65DP141_Channel0CtrlTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RSVDRV_EN :1;
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uint8_t EQ_EN :1;
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uint8_t DRV_PEAK :1;
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uint8_t RESERVED :5;
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};
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} SN65DP141_Channel0EnableTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RX_GAIN_0 :1;
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uint8_t RX_GAIN_1 :1;
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uint8_t EQ_DC_GAIN :1;
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uint8_t TX_GAIN :1;
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uint8_t EQ_Setting_0 :1;
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uint8_t EQ_Setting_1 :1;
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uint8_t EQ_Setting_2 :1;
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uint8_t RESERVED :1;
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};
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} SN65DP141_Channel1CtrlTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RSVDRV_EN :1;
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uint8_t EQ_EN :1;
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uint8_t DRV_PEAK :1;
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uint8_t RESERVED :5;
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};
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} SN65DP141_Channel1EnableTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RX_GAIN_0 :1;
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uint8_t RX_GAIN_1 :1;
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uint8_t EQ_DC_GAIN :1;
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uint8_t TX_GAIN :1;
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uint8_t EQ_Setting_0 :1;
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uint8_t EQ_Setting_1 :1;
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uint8_t EQ_Setting_2 :1;
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uint8_t RESERVED :1;
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};
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} SN65DP141_Channel2CtrlTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RSVDRV_EN :1;
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uint8_t EQ_EN :1;
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uint8_t DRV_PEAK :1;
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uint8_t RESERVED :5;
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};
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} SN65DP141_Channel2EnableTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RX_GAIN_0 :1;
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uint8_t RX_GAIN_1 :1;
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uint8_t EQ_DC_GAIN :1;
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uint8_t TX_GAIN :1;
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uint8_t EQ_Setting_0 :1;
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uint8_t EQ_Setting_1 :1;
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uint8_t EQ_Setting_2 :1;
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uint8_t RESERVED :1;
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};
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} SN65DP141_Channel3CtrlTypeDef;
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typedef union {
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uint8_t Register;
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struct {
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uint8_t RSVDRV_EN :1;
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uint8_t EQ_EN :1;
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uint8_t DRV_PEAK :1;
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uint8_t RESERVED :5;
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};
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} SN65DP141_Channel3EnableTypeDef;
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typedef struct
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{
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SN65DP141_GeneralTypeDef General; /*!< 0x00 (General Device Settings) */
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SN65DP141_ChannelEnableTypeDef ChannelEnable; /*!< 0x01 (Channel Enable) */
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SN65DP141_Channel0CtrlTypeDef Channel0Ctrl; /*!< 0x02 (Channel 0 Control Settings) */
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SN65DP141_Channel0EnableTypeDef Channel0Enable; /*!< 0x03 (Channel 0 Enable Settings) */
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SN65DP141_Channel1CtrlTypeDef Channel1Ctrl; /*!< 0x05 (Channel 1 Control Settings) */
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SN65DP141_Channel1EnableTypeDef Channel1Enable; /*!< 0x06 (Channel 1 Enable Settings) */
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SN65DP141_Channel2CtrlTypeDef Channel2Ctrl; /*!< 0x08 (Channel 2 Control Settings) */
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SN65DP141_Channel2EnableTypeDef Channel2Enable; /*!< 0x09 (Channel 2 Enable Settings) */
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SN65DP141_Channel3CtrlTypeDef Channel3Ctrl; /*!< 0x0B (Channel 3 Control Settings) */
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SN65DP141_Channel3EnableTypeDef Channel3Enable; /*!< 0x0C (Channel 3 Enable Settings) */
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} SN65DP141_RegistersTypeDef;
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/**
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* @}
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*/
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#endif /* SN65DP141_DEBUG */
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/** @defgroup SN65DP141_Exported_Functions
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* @{
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*/
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uint32_t sn65dp141_Init(uint16_t Address);
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void sn65dp141_DeInit(uint16_t Address);
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uint32_t sn65dp141_PowerOn(uint16_t Address);
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uint32_t sn65dp141_PowerOff(uint16_t Address);
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uint32_t sn65dp141_SetEQGain(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId, uint8_t EQGain);
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uint32_t sn65dp141_EnableChannel(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId);
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uint32_t sn65dp141_DisableChannel(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId);
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/* MUX IO functions */
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uint8_t MUX_IO_Init(void);
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void MUX_IO_DeInit(void);
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uint8_t MUX_IO_Write(uint16_t Addr, uint16_t Reg, uint8_t Data);
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uint8_t MUX_IO_Read(uint16_t Addr, uint16_t Reg, uint8_t *pData);
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uint32_t MUX_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials);
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/**
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* @}
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*/
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/** @defgroup SN65DP141_Exported_Variables
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* @{
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*/
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/* DisplayPort Linear Redriver Driver structure */
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extern DPREDRIVER_Drv_t sn65dp141_drv;
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* SN65DP141_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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