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This commit is contained in:
Jochen Friedrich 2021-03-07 18:24:42 +01:00
commit 945d2870aa
17 changed files with 3370 additions and 0 deletions
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10
.gitignore vendored Normal file
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*.asm
*.ihx
*.lk
*.lst
*.map
*.mem
*.rel
*.rst
*.sym

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boards.txt Normal file
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8channel output:
M2 P0.1
OCDCK P0.2
M0 P0.3
M1 P0.4
RS485_DIR P0.5
TXD P0.6
RXD P0.7
SHCP P1.1
STCP P1.2
OE P1.3
DS P1.4
OCDDA P1.6
LC Relays:
S1 P0.0
RED P0.1
OCDCK P0.2
BLUE P0.3
GREEN P0.4
TXD P0.6
RXD P0.7
S2 P1.0
RELAY1 P1.2
RELAY2 P1.5
OCDDA P1.6
2 Relays RS485
RELAY2 P0.1
OCDCK P0.2
IN1 P0.5
TXD P0.6
RXD P0.7
RELAY1 P1.3
RS485_DIR P1.4
IN2 P1.5
OCDDA P1.6

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include/nuvoton/Common.h Normal file
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typedef unsigned char UINT8;
typedef unsigned int UINT16;
typedef unsigned long UINT32;
typedef unsigned char uint8_t;
typedef unsigned int uint16_t;
typedef unsigned long uint32_t;
#define CID_READ 0x0B
#define DID_READ 0x0C
#define ERASE_APROM 0x22
#define READ_APROM 0x00
#define PROGRAM_APROM 0x21
#define ERASE_LDROM
#define READ_LDROM
#define PROGRAM_LDROM
#define READ_CFG 0xC0
#define PROGRAM_CFG 0xE1
#define READ_UID 0x04
void InitialUART0_Timer1(UINT32 u32Baudrate); //T1M = 1, SMOD = 1
void InitialUART0_Timer3(UINT32 u32Baudrate); //Timer3 as Baudrate, SMOD=1, Prescale=0
void InitialUART1_Timer3(UINT32 u32Baudrate);
void Send_Data_To_UART0(UINT8 c);
UINT8 Receive_Data_From_UART0(void);
void Send_Data_To_UART1(UINT8 c);
UINT8 Receive_Data_From_UART1(void);
void InitialUART1(UINT32 u32Baudrate);

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include/nuvoton/Delay.h Normal file
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void Timer0_Delay100us(UINT32 u32CNT);
void Timer0_Delay1ms(UINT32 u32CNT);
void Timer1_Delay10ms(UINT32 u32CNT);
void Timer2_Delay500us(UINT32 u32CNT);
void Timer3_Delay100ms(UINT32 u32CNT);
void Timer0_Delay40ms(UINT32 u32CNT);
void Timer3_Delay10us(UINT32 u32CNT);

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/*--------------------------------------------------------------------------
N76E003.H
Header file for Nuvoton N76E003
--------------------------------------------------------------------------*/
__sfr __at(0x80) P0;
#define __SFR_P0 0x80
__sfr __at(0x81) SP;
#define __SFR_SP 0x81
__sfr __at(0x82) DPL;
#define __SFR_DPL 0x82
__sfr __at(0x83) DPH;
#define __SFR_DPH 0x83
__sfr __at(0x84) RCTRIM0;
#define __SFR_RCTRIM0 0x84
__sfr __at(0x85) RCTRIM1;
#define __SFR_RCTRIM1 0x85
__sfr __at(0x86) RWK;
#define __SFR_RWK 0x86
__sfr __at(0x87) PCON;
#define __SFR_PCON 0x87
__sfr __at(0x88) TCON;
#define __SFR_TCON 0x88
__sfr __at(0x89) TMOD;
#define __SFR_TMOD 0x89
__sfr __at(0x8A) TL0;
#define __SFR_TL0 0x8A
__sfr __at(0x8B) TL1;
#define __SFR_TL1 0x8B
__sfr __at(0x8C) TH0;
#define __SFR_TH0 0x8C
__sfr __at(0x8D) TH1;
#define __SFR_TH1 0x8D
__sfr __at(0x8E) CKCON;
#define __SFR_CKCON 0x8E
__sfr __at(0x8F) WKCON;
#define __SFR_WKCON 0x8F
__sfr __at(0x90) P1;
#define __SFR_P1 0x90
__sfr __at(0x91) SFRS; //TA Protection
#define __SFR_SFRS 0x91
__sfr __at(0x92) CAPCON0;
#define __SFR_CAPCON0 0x92
__sfr __at(0x93) CAPCON1;
#define __SFR_CAPCON1 0x93
__sfr __at(0x94) CAPCON2;
#define __SFR_CAPCON2 0x94
__sfr __at(0x95) CKDIV;
#define __SFR_CKDIV 0x95
__sfr __at(0x96) CKSWT; //TA Protection
#define __SFR_CKSWT 0x96
__sfr __at(0x97) CKEN; //TA Protection
#define __SFR_CKEN 0x97
__sfr __at(0x98) SCON;
#define __SFR_SCON 0x98
__sfr __at(0x99) SBUF;
#define __SFR_SBUF 0x99
__sfr __at(0x9A) SBUF_1;
#define __SFR_SBUF_1 0x9A
__sfr __at(0x9B) EIE;
#define __SFR_EIE 0x9B
__sfr __at(0x9C) EIE1;
#define __SFR_EIE1 0x9C
__sfr __at(0x9F) CHPCON; //TA Protection
#define __SFR_CHPCON 0x9F
__sfr __at(0xA0) P2;
#define __SFR_P2 0xA0
__sfr __at(0xA2) AUXR1;
#define __SFR_AUXR1 0xA2
__sfr __at(0xA3) BODCON0; //TA Protection
#define __SFR_BODCON0 0xA3
__sfr __at(0xA4) IAPTRG; //TA Protection
#define __SFR_IAPTRG 0xA4
__sfr __at(0xA5) IAPUEN; //TA Protection
#define __SFR_IAPUEN 0xA5
__sfr __at(0xA6) IAPAL;
#define __SFR_IAPAL 0xA6
__sfr __at(0xA7) IAPAH;
#define __SFR_IAPAH 0xA7
__sfr __at(0xA8) IE;
#define __SFR_IE 0xA8
__sfr __at(0xA9) SADDR;
#define __SFR_SADDR 0xA9
__sfr __at(0xAA) WDCON; //TA Protection
#define __SFR_WDCON 0xAA
__sfr __at(0xAB) BODCON1; //TA Protection
#define __SFR_BODCON1 0xAB
__sfr __at(0xAC) P3M1;
#define __SFR_P3M1 0xAC
__sfr __at(0xAC) P3S; //Page1
#define __SFR_P3S 0xAC
__sfr __at(0xAD) P3M2;
#define __SFR_P3M2 0xAD
__sfr __at(0xAD) P3SR; //Page1
#define __SFR_P3SR 0xAD
__sfr __at(0xAE) IAPFD;
#define __SFR_IAPFD 0xAE
__sfr __at(0xAF) IAPCN;
#define __SFR_IAPCN 0xAF
__sfr __at(0xB0) P3;
#define __SFR_P3 0xB0
__sfr __at(0xB1) P0M1;
#define __SFR_P0M1 0xB1
__sfr __at(0xB1) P0S; //Page1
#define __SFR_P0S 0xB1
__sfr __at(0xB2) P0M2;
#define __SFR_P0M2 0xB2
__sfr __at(0xB2) P0SR; //Page1
#define __SFR_P0SR 0xB2
__sfr __at(0xB3) P1M1;
#define __SFR_P1M1 0xB3
__sfr __at(0xB3) P1S; //Page1
#define __SFR_P1S 0xB3
__sfr __at(0xB4) P1M2;
#define __SFR_P1M2 0xB4
__sfr __at(0xB4) P1SR; //Page1
#define __SFR_P1SR 0xB4
__sfr __at(0xB5) P2S;
#define __SFR_P2S 0xB5
__sfr __at(0xB7) IPH;
#define __SFR_IPH 0xB7
__sfr __at(0xB7) PWMINTC; //Page1
#define __SFR_PWMINTC 0xB7
__sfr __at(0xB8) IP;
#define __SFR_IP 0xB8
__sfr __at(0xB9) SADEN;
#define __SFR_SADEN 0xB9
__sfr __at(0xBA) SADEN_1;
#define __SFR_SADEN_1 0xBA
__sfr __at(0xBB) SADDR_1;
#define __SFR_SADDR_1 0xBB
__sfr __at(0xBC) I2DAT;
#define __SFR_I2DAT 0xBC
__sfr __at(0xBD) I2STAT;
#define __SFR_I2STAT 0xBD
__sfr __at(0xBE) I2CLK;
#define __SFR_I2CLK 0xBE
__sfr __at(0xBF) I2TOC;
#define __SFR_I2TOC 0xBF
__sfr __at(0xC0) I2CON;
#define __SFR_I2CON 0xC0
__sfr __at(0xC1) I2ADDR;
#define __SFR_I2ADDR 0xC1
__sfr __at(0xC2) ADCRL;
#define __SFR_ADCRL 0xC2
__sfr __at(0xC3) ADCRH;
#define __SFR_ADCRH 0xC3
__sfr __at(0xC4) T3CON;
#define __SFR_T3CON 0xC4
__sfr __at(0xC4) PWM4H; //Page1
#define __SFR_PWM4H 0xC4
__sfr __at(0xC5) RL3;
#define __SFR_RL3 0xC5
__sfr __at(0xC5) PWM5H; //Page1
#define __SFR_PWM5H 0xC5
__sfr __at(0xC6) RH3;
#define __SFR_RH3 0xC6
__sfr __at(0xC6) PIOCON1; //Page1
#define __SFR_PIOCON1 0xC6
__sfr __at(0xC7) TA;
#define __SFR_TA 0xC7
__sfr __at(0xC8) T2CON;
#define __SFR_T2CON 0xC8
__sfr __at(0xC9) T2MOD;
#define __SFR_T2MOD 0xC9
__sfr __at(0xCA) RCMP2L;
#define __SFR_RCMP2L 0xCA
__sfr __at(0xCB) RCMP2H;
#define __SFR_RCMP2H 0xCB
__sfr __at(0xCC) TL2;
#define __SFR_TL2 0xCC
__sfr __at(0xCC) PWM4L; //Page1
#define __SFR_PWM4L 0xCC
__sfr __at(0xCD) TH2;
#define __SFR_TH2 0xCD
__sfr __at(0xCD) PWM5L; //Page1
#define __SFR_PWM5L 0xCD
__sfr __at(0xCE) ADCMPL;
#define __SFR_ADCMPL 0xCE
__sfr __at(0xCF) ADCMPH;
#define __SFR_ADCMPH 0xCF
__sfr __at(0xD0) PSW;
#define __SFR_PSW 0xD0
__sfr __at(0xD1) PWMPH;
#define __SFR_PWMPH 0xD1
__sfr __at(0xD2) PWM0H;
#define __SFR_PWM0H 0xD2
__sfr __at(0xD3) PWM1H;
#define __SFR_PWM1H 0xD3
__sfr __at(0xD4) PWM2H;
#define __SFR_PWM2H 0xD4
__sfr __at(0xD5) PWM3H;
#define __SFR_PWM3H 0xD5
__sfr __at(0xD6) PNP;
#define __SFR_PNP 0xD6
__sfr __at(0xD7) FBD;
#define __SFR_FBD 0xD7
__sfr __at(0xD8) PWMCON0;
#define __SFR_PWMCON0 0xD8
__sfr __at(0xD9) PWMPL;
#define __SFR_PWMPL 0xD9
__sfr __at(0xDA) PWM0L;
#define __SFR_PWM0L 0xDA
__sfr __at(0xDB) PWM1L;
#define __SFR_PWM1L 0xDB
__sfr __at(0xDC) PWM2L;
#define __SFR_PWM2L 0xDC
__sfr __at(0xDD) PWM3L;
#define __SFR_PWM3L 0xDD
__sfr __at(0xDE) PIOCON0;
#define __SFR_PIOCON0 0xDE
__sfr __at(0xDF) PWMCON1;
#define __SFR_PWMCON1 0xDF
__sfr __at(0xE0) ACC;
#define __SFR_ACC 0xE0
__sfr __at(0xE1) ADCCON1;
#define __SFR_ADCCON1 0xE1
__sfr __at(0xE2) ADCCON2;
#define __SFR_ADCCON2 0xE2
__sfr __at(0xE3) ADCDLY;
#define __SFR_ADCDLY 0xE3
__sfr __at(0xE4) C0L;
#define __SFR_C0L 0xE4
__sfr __at(0xE5) C0H;
#define __SFR_C0H 0xE5
__sfr __at(0xE6) C1L;
#define __SFR_C1L 0xE6
__sfr __at(0xE7) C1H;
#define __SFR_C1H 0xE7
__sfr __at(0xE8) ADCCON0;
#define __SFR_ADCCON0 0xE8
__sfr __at(0xE9) PICON;
#define __SFR_PICON 0xE9
__sfr __at(0xEA) PINEN;
#define __SFR_PINEN 0xEA
__sfr __at(0xEB) PIPEN;
#define __SFR_PIPEN 0xEB
__sfr __at(0xEC) PIF;
#define __SFR_PIF 0xEC
__sfr __at(0xED) C2L;
#define __SFR_C2L 0xED
__sfr __at(0xEE) C2H;
#define __SFR_C2H 0xEE
__sfr __at(0xEF) EIP;
#define __SFR_EIP 0xEF
__sfr __at(0xF0) B;
#define __SFR_B 0xF0
__sfr __at(0xF1) CAPCON3;
#define __SFR_CAPCON3 0xF1
__sfr __at(0xF2) CAPCON4;
#define __SFR_CAPCON4 0xF2
__sfr __at(0xF3) SPCR;
#define __SFR_SPCR 0xF3
__sfr __at(0xF3) SPCR2; //Page1
#define __SFR_SPCR2 0xF3
__sfr __at(0xF4) SPSR;
#define __SFR_SPSR 0xF4
__sfr __at(0xF5) SPDR;
#define __SFR_SPDR 0xF5
__sfr __at(0xF6) AINDIDS;
#define __SFR_AINDIDS 0xF6
__sfr __at(0xF7) EIPH;
#define __SFR_EIPH 0xF7
__sfr __at(0xF8) SCON_1;
#define __SFR_SCON_1 0xF8
__sfr __at(0xF9) PDTEN; //TA Protection
#define __SFR_PDTEN 0xF9
__sfr __at(0xFA) PDTCNT; //TA Protection
#define __SFR_PDTCNT 0xFA
__sfr __at(0xFB) PMEN;
#define __SFR_PMEN 0xFB
__sfr __at(0xFC) PMD;
#define __SFR_PMD 0xFC
__sfr __at(0xFE) EIP1;
#define __SFR_EIP1 0xFE
__sfr __at(0xFF) EIPH1;
#define __SFR_EIPH1 0xFF
/* BIT Registers */
/* SCON_1 */
__sbit __at(__SFR_SCON_1^7) SM0_1;
__sbit __at(__SFR_SCON_1^7) FE_1;
__sbit __at(__SFR_SCON_1^6) SM1_1;
__sbit __at(__SFR_SCON_1^5) SM2_1;
__sbit __at(__SFR_SCON_1^4) REN_1;
__sbit __at(__SFR_SCON_1^3) TB8_1;
__sbit __at(__SFR_SCON_1^2) RB8_1;
__sbit __at(__SFR_SCON_1^1) TI_1;
__sbit __at(__SFR_SCON_1^0) RI_1;
/* ADCCON0 */
__sbit __at(__SFR_ADCCON0^7) ADCF;
__sbit __at(__SFR_ADCCON0^6) ADCS;
__sbit __at(__SFR_ADCCON0^5) ETGSEL1;
__sbit __at(__SFR_ADCCON0^4) ETGSEL0;
__sbit __at(__SFR_ADCCON0^3) ADCHS3;
__sbit __at(__SFR_ADCCON0^2) ADCHS2;
__sbit __at(__SFR_ADCCON0^1) ADCHS1;
__sbit __at(__SFR_ADCCON0^0) ADCHS0;
/* PWMCON0 */
__sbit __at(__SFR_PWMCON0^7) PWMRUN;
__sbit __at(__SFR_PWMCON0^6) LOAD;
__sbit __at(__SFR_PWMCON0^5) PWMF;
__sbit __at(__SFR_PWMCON0^4) CLRPWM;
/* PSW */
__sbit __at(__SFR_PSW^7) CY;
__sbit __at(__SFR_PSW^6) AC;
__sbit __at(__SFR_PSW^5) F0;
__sbit __at(__SFR_PSW^4) RS1;
__sbit __at(__SFR_PSW^3) RS0;
__sbit __at(__SFR_PSW^2) OV;
__sbit __at(__SFR_PSW^0) P;
/* T2CON */
__sbit __at(__SFR_T2CON^7) TF2;
__sbit __at(__SFR_T2CON^2) TR2;
__sbit __at(__SFR_T2CON^0) CM_RL2;
/* I2CON */
__sbit __at(__SFR_I2CON^6) I2CEN;
__sbit __at(__SFR_I2CON^5) STA;
__sbit __at(__SFR_I2CON^4) STO;
__sbit __at(__SFR_I2CON^3) SI;
__sbit __at(__SFR_I2CON^2) AA;
__sbit __at(__SFR_I2CON^0) I2CPX;
/* IP */
__sbit __at(__SFR_IP^6) PADC;
__sbit __at(__SFR_IP^5) PBOD;
__sbit __at(__SFR_IP^4) PS;
__sbit __at(__SFR_IP^3) PT1;
__sbit __at(__SFR_IP^2) PX1;
__sbit __at(__SFR_IP^1) PT0;
__sbit __at(__SFR_IP^0) PX0;
/* P3 */
__sbit __at(__SFR_P3^0) P30;
/* IE */
__sbit __at(__SFR_IE^7) EA;
__sbit __at(__SFR_IE^6) EADC;
__sbit __at(__SFR_IE^5) EBOD;
__sbit __at(__SFR_IE^4) ES;
__sbit __at(__SFR_IE^3) ET1;
__sbit __at(__SFR_IE^2) EX1;
__sbit __at(__SFR_IE^1) ET0;
__sbit __at(__SFR_IE^0) EX0;
/* P2 */
__sbit __at(__SFR_P2^0) P20;
/* SCON */
__sbit __at(__SFR_SCON^7) SM0;
__sbit __at(__SFR_SCON^7) FE;
__sbit __at(__SFR_SCON^6) SM1;
__sbit __at(__SFR_SCON^5) SM2;
__sbit __at(__SFR_SCON^4) REN;
__sbit __at(__SFR_SCON^3) TB8;
__sbit __at(__SFR_SCON^2) RB8;
__sbit __at(__SFR_SCON^1) TI;
__sbit __at(__SFR_SCON^0) RI;
/* P1 */
__sbit __at(__SFR_P1^7) P17;
__sbit __at(__SFR_P1^6) P16;
__sbit __at(__SFR_P1^6) TXD_1;
__sbit __at(__SFR_P1^5) P15;
__sbit __at(__SFR_P1^4) P14;
__sbit __at(__SFR_P1^4) SDA;
__sbit __at(__SFR_P1^3) P13;
__sbit __at(__SFR_P1^3) SCL;
__sbit __at(__SFR_P1^2) P12;
__sbit __at(__SFR_P1^1) P11;
__sbit __at(__SFR_P1^0) P10;
/* TCON */
__sbit __at(__SFR_TCON^7) TF1;
__sbit __at(__SFR_TCON^6) TR1;
__sbit __at(__SFR_TCON^5) TF0;
__sbit __at(__SFR_TCON^4) TR0;
__sbit __at(__SFR_TCON^3) IE1;
__sbit __at(__SFR_TCON^2) IT1;
__sbit __at(__SFR_TCON^1) IE0;
__sbit __at(__SFR_TCON^0) IT0;
/* P0 */
__sbit __at(__SFR_P0^7) P07;
__sbit __at(__SFR_P0^7) RXD;
__sbit __at(__SFR_P0^6) P06;
__sbit __at(__SFR_P0^6) TXD;
__sbit __at(__SFR_P0^5) P05;
__sbit __at(__SFR_P0^4) P04;
__sbit __at(__SFR_P0^4) STADC;
__sbit __at(__SFR_P0^3) P03;
__sbit __at(__SFR_P0^2) P02;
__sbit __at(__SFR_P0^2) RXD_1;
__sbit __at(__SFR_P0^1) P01;
__sbit __at(__SFR_P0^1) MISO;
__sbit __at(__SFR_P0^0) P00;
__sbit __at(__SFR_P0^0) MOSI;
/*--------------------------------------------------------------------------
N76E003.H
Header file for Nuvoton N76E003
--------------------------------------------------------------------------*/

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include/nuvoton/SFR_Macro.h Normal file
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/*--------------------------------------------------------------------------
N76E003 Function_define.h V1.02
All function define inital setting file for Nuvoton N76E003
--------------------------------------------------------------------------*/
#include <stdio.h>
#define nop _nop_();
//16 --> 8 x 2
#define HIBYTE(v1) ((UINT8)((v1)>>8)) //v1 is UINT16
#define LOBYTE(v1) ((UINT8)((v1)&0xFF))
//8 x 2 --> 16
#define MAKEWORD(v1,v2) ((((UINT16)(v1))<<8)+(UINT16)(v2)) //v1,v2 is UINT8
//8 x 4 --> 32
#define MAKELONG(v1,v2,v3,v4) (UINT32)((v1<<32)+(v2<<16)+(v3<<8)+v4) //v1,v2,v3,v4 is UINT8
//32 --> 16 x 2
#define YBYTE1(v1) ((UINT16)((v1)>>16)) //v1 is UINT32
#define YBYTE0(v1) ((UINT16)((v1)&0xFFFF))
//32 --> 8 x 4
#define TBYTE3(v1) ((UINT8)((v1)>>24)) //v1 is UINT32
#define TBYTE2(v1) ((UINT8)((v1)>>16))
#define TBYTE1(v1) ((UINT8)((v1)>>8))
#define TBYTE0(v1) ((UINT8)((v1)&0xFF))
#define SET_BIT0 0x01
#define SET_BIT1 0x02
#define SET_BIT2 0x04
#define SET_BIT3 0x08
#define SET_BIT4 0x10
#define SET_BIT5 0x20
#define SET_BIT6 0x40
#define SET_BIT7 0x80
#define SET_BIT8 0x0100
#define SET_BIT9 0x0200
#define SET_BIT10 0x0400
#define SET_BIT11 0x0800
#define SET_BIT12 0x1000
#define SET_BIT13 0x2000
#define SET_BIT14 0x4000
#define SET_BIT15 0x8000
#define CLR_BIT0 0xFE
#define CLR_BIT1 0xFD
#define CLR_BIT2 0xFB
#define CLR_BIT3 0xF7
#define CLR_BIT4 0xEF
#define CLR_BIT5 0xDF
#define CLR_BIT6 0xBF
#define CLR_BIT7 0x7F
#define CLR_BIT8 0xFEFF
#define CLR_BIT9 0xFDFF
#define CLR_BIT10 0xFBFF
#define CLR_BIT11 0xF7FF
#define CLR_BIT12 0xEFFF
#define CLR_BIT13 0xDFFF
#define CLR_BIT14 0xBFFF
#define CLR_BIT15 0x7FFF
#define FAIL 1
#define PASS 0
/*****************************************************************************************
* For GPIO INIT setting
*****************************************************************************************/
//------------------- Define Port as Quasi mode -------------------
#define P00_Quasi_Mode P0M1&=~SET_BIT0;P0M2&=~SET_BIT0
#define P01_Quasi_Mode P0M1&=~SET_BIT1;P0M2&=~SET_BIT1
#define P02_Quasi_Mode P0M1&=~SET_BIT2;P0M2&=~SET_BIT2
#define P03_Quasi_Mode P0M1&=~SET_BIT3;P0M2&=~SET_BIT3
#define P04_Quasi_Mode P0M1&=~SET_BIT4;P0M2&=~SET_BIT4
#define P05_Quasi_Mode P0M1&=~SET_BIT5;P0M2&=~SET_BIT5
#define P06_Quasi_Mode P0M1&=~SET_BIT6;P0M2&=~SET_BIT6
#define P07_Quasi_Mode P0M1&=~SET_BIT7;P0M2&=~SET_BIT7
#define P10_Quasi_Mode P1M1&=~SET_BIT0;P1M2&=~SET_BIT0
#define P11_Quasi_Mode P1M1&=~SET_BIT1;P1M2&=~SET_BIT1
#define P12_Quasi_Mode P1M1&=~SET_BIT2;P1M2&=~SET_BIT2
#define P13_Quasi_Mode P1M1&=~SET_BIT3;P1M2&=~SET_BIT3
#define P14_Quasi_Mode P1M1&=~SET_BIT4;P1M2&=~SET_BIT4
#define P15_Quasi_Mode P1M1&=~SET_BIT5;P1M2&=~SET_BIT5
#define P16_Quasi_Mode P1M1&=~SET_BIT6;P1M2&=~SET_BIT6
#define P17_Quasi_Mode P1M1&=~SET_BIT7;P1M2&=~SET_BIT7
#define P30_Quasi_Mode P3M1&=~SET_BIT0;P3M2&=~SET_BIT0
//------------------- Define Port as Push Pull mode -------------------
#define P00_PushPull_Mode P0M1&=~SET_BIT0;P0M2|=SET_BIT0
#define P01_PushPull_Mode P0M1&=~SET_BIT1;P0M2|=SET_BIT1
#define P02_PushPull_Mode P0M1&=~SET_BIT2;P0M2|=SET_BIT2
#define P03_PushPull_Mode P0M1&=~SET_BIT3;P0M2|=SET_BIT3
#define P04_PushPull_Mode P0M1&=~SET_BIT4;P0M2|=SET_BIT4
#define P05_PushPull_Mode P0M1&=~SET_BIT5;P0M2|=SET_BIT5
#define P06_PushPull_Mode P0M1&=~SET_BIT6;P0M2|=SET_BIT6
#define P07_PushPull_Mode P0M1&=~SET_BIT7;P0M2|=SET_BIT7
#define P10_PushPull_Mode P1M1&=~SET_BIT0;P1M2|=SET_BIT0
#define P11_PushPull_Mode P1M1&=~SET_BIT1;P1M2|=SET_BIT1
#define P12_PushPull_Mode P1M1&=~SET_BIT2;P1M2|=SET_BIT2
#define P13_PushPull_Mode P1M1&=~SET_BIT3;P1M2|=SET_BIT3
#define P14_PushPull_Mode P1M1&=~SET_BIT4;P1M2|=SET_BIT4
#define P15_PushPull_Mode P1M1&=~SET_BIT5;P1M2|=SET_BIT5
#define P16_PushPull_Mode P1M1&=~SET_BIT6;P1M2|=SET_BIT6
#define P17_PushPull_Mode P1M1&=~SET_BIT7;P1M2|=SET_BIT7
#define P30_PushPull_Mode P3M1&=~SET_BIT0;P3M2|=SET_BIT0
#define GPIO1_PushPull_Mode P1M1&=~SET_BIT0;P1M2|=SET_BIT0
//------------------- Define Port as Input Only mode -------------------
#define P00_Input_Mode P0M1|=SET_BIT0;P0M2&=~SET_BIT0
#define P01_Input_Mode P0M1|=SET_BIT1;P0M2&=~SET_BIT1
#define P02_Input_Mode P0M1|=SET_BIT2;P0M2&=~SET_BIT2
#define P03_Input_Mode P0M1|=SET_BIT3;P0M2&=~SET_BIT3
#define P04_Input_Mode P0M1|=SET_BIT4;P0M2&=~SET_BIT4
#define P05_Input_Mode P0M1|=SET_BIT5;P0M2&=~SET_BIT5
#define P06_Input_Mode P0M1|=SET_BIT6;P0M2&=~SET_BIT6
#define P07_Input_Mode P0M1|=SET_BIT7;P0M2&=~SET_BIT7
#define P10_Input_Mode P1M1|=SET_BIT0;P1M2&=~SET_BIT0
#define P11_Input_Mode P1M1|=SET_BIT1;P1M2&=~SET_BIT1
#define P12_Input_Mode P1M1|=SET_BIT2;P1M2&=~SET_BIT2
#define P13_Input_Mode P1M1|=SET_BIT3;P1M2&=~SET_BIT3
#define P14_Input_Mode P1M1|=SET_BIT4;P1M2&=~SET_BIT4
#define P15_Input_Mode P1M1|=SET_BIT5;P1M2&=~SET_BIT5
#define P16_Input_Mode P1M1|=SET_BIT6;P1M2&=~SET_BIT6
#define P17_Input_Mode P1M1|=SET_BIT7;P1M2&=~SET_BIT7
#define P30_Input_Mode P3M1|=SET_BIT0;P3M2&=~SET_BIT0
//-------------------Define Port as Open Drain mode -------------------
#define P00_OpenDrain_Mode P0M1|=SET_BIT0;P0M2|=SET_BIT0
#define P01_OpenDrain_Mode P0M1|=SET_BIT1;P0M2|=SET_BIT1
#define P02_OpenDrain_Mode P0M1|=SET_BIT2;P0M2|=SET_BIT2
#define P03_OpenDrain_Mode P0M1|=SET_BIT3;P0M2|=SET_BIT3
#define P04_OpenDrain_Mode P0M1|=SET_BIT4;P0M2|=SET_BIT4
#define P05_OpenDrain_Mode P0M1|=SET_BIT5;P0M2|=SET_BIT5
#define P06_OpenDrain_Mode P0M1|=SET_BIT6;P0M2|=SET_BIT6
#define P07_OpenDrain_Mode P0M1|=SET_BIT7;P0M2|=SET_BIT7
#define P10_OpenDrain_Mode P1M1|=SET_BIT0;P1M2|=SET_BIT0
#define P11_OpenDrain_Mode P1M1|=SET_BIT1;P1M2|=SET_BIT1
#define P12_OpenDrain_Mode P1M1|=SET_BIT2;P1M2|=SET_BIT2
#define P13_OpenDrain_Mode P1M1|=SET_BIT3;P1M2|=SET_BIT3
#define P14_OpenDrain_Mode P1M1|=SET_BIT4;P1M2|=SET_BIT4
#define P15_OpenDrain_Mode P1M1|=SET_BIT5;P1M2|=SET_BIT5
#define P16_OpenDrain_Mode P1M1|=SET_BIT6;P1M2|=SET_BIT6
#define P17_OpenDrain_Mode P1M1|=SET_BIT7;P1M2|=SET_BIT7
#define P30_OpenDrain_Mode P3M1|=SET_BIT0;P3M2|=SET_BIT0
//--------- Define all port as quasi mode ---------
#define Set_All_GPIO_Quasi_Mode P0M1=0;P0M2=0;P1M1=0;P1M2=0;P3M1=0;P3M2=0
#define set_GPIO1 P12=1
#define clr_GPIO1 P12=0
/****************************************************************************
Enable INT port 0~3
***************************************************************************/
#define Enable_INT_Port0 PICON &= 0xFB;
#define Enable_INT_Port1 PICON |= 0x01;
#define Enable_INT_Port2 PICON |= 0x02;
#define Enable_INT_Port3 PICON |= 0x03;
/*****************************************************************************
Enable each bit low level trig mode
*****************************************************************************/
#define Enable_BIT7_LowLevel_Trig PICON&=0x7F;PINEN|=0x80;PIPEN&=0x7F
#define Enable_BIT6_LowLevel_Trig PICON&=0x7F;PINEN|=0x40;PIPEN&=0xBF
#define Enable_BIT5_LowLevel_Trig PICON&=0xBF;PINEN|=0x20;PIPEN&=0xDF
#define Enable_BIT4_LowLevel_Trig PICON&=0xBF;PINEN|=0x10;PIPEN&=0xEF
#define Enable_BIT3_LowLevel_Trig PICON&=0xDF;PINEN|=0x08;PIPEN&=0xF7
#define Enable_BIT2_LowLevel_Trig PICON&=0xEF;PINEN|=0x04;PIPEN&=0xFB
#define Enable_BIT1_LowLevel_Trig PICON&=0xF7;PINEN|=0x02;PIPEN&=0xFD
#define Enable_BIT0_LowLevel_Trig PICON&=0xFD;PINEN|=0x01;PIPEN&=0xFE
/*****************************************************************************
Enable each bit high level trig mode
*****************************************************************************/
#define Enable_BIT7_HighLevel_Trig PICON&=0x7F;PINEN&=0x7F;PIPEN|=0x80
#define Enable_BIT6_HighLevel_Trig PICON&=0x7F;PINEN&=0xBF;PIPEN|=0x40
#define Enable_BIT5_HighLevel_Trig PICON&=0xBF;PINEN&=0xDF;PIPEN|=0x20
#define Enable_BIT4_HighLevel_Trig PICON&=0xBF;PINEN&=0xEF;PIPEN|=0x10
#define Enable_BIT3_HighLevel_Trig PICON&=0xDF;PINEN&=0xF7;PIPEN|=0x08
#define Enable_BIT2_HighLevel_Trig PICON&=0xEF;PINEN&=0xFB;PIPEN|=0x04
#define Enable_BIT1_HighLevel_Trig PICON&=0xF7;PINEN&=0xFD;PIPEN|=0x02
#define Enable_BIT0_HighLevel_Trig PICON&=0xFD;PINEN&=0xFE;PIPEN|=0x01
/*****************************************************************************
Enable each bit falling edge trig mode
*****************************************************************************/
#define Enable_BIT7_FallEdge_Trig PICON|=0x80;PINEN|=0x80;PIPEN&=0x7F
#define Enable_BIT6_FallEdge_Trig PICON|=0x80;PINEN|=0x40;PIPEN&=0xBF
#define Enable_BIT5_FallEdge_Trig PICON|=0x40;PINEN|=0x20;PIPEN&=0xDF
#define Enable_BIT4_FallEdge_Trig PICON|=0x40;PINEN|=0x10;PIPEN&=0xEF
#define Enable_BIT3_FallEdge_Trig PICON|=0x20;PINEN|=0x08;PIPEN&=0xF7
#define Enable_BIT2_FallEdge_Trig PICON|=0x10;PINEN|=0x04;PIPEN&=0xFB
#define Enable_BIT1_FallEdge_Trig PICON|=0x08;PINEN|=0x02;PIPEN&=0xFD
#define Enable_BIT0_FallEdge_Trig PICON|=0x04;PINEN|=0x01;PIPEN&=0xFE
/*****************************************************************************
Enable each bit rasing edge trig mode
*****************************************************************************/
#define Enable_BIT7_RasingEdge_Trig PICON|=0x80;PINEN&=0x7F;PIPEN|=0x80
#define Enable_BIT6_RasingEdge_Trig PICON|=0x80;PINEN&=0xBF;PIPEN|=0x40
#define Enable_BIT5_RasingEdge_Trig PICON|=0x40;PINEN&=0xDF;PIPEN|=0x20
#define Enable_BIT4_RasingEdge_Trig PICON|=0x40;PINEN&=0xEF;PIPEN|=0x10
#define Enable_BIT3_RasingEdge_Trig PICON|=0x20;PINEN&=0xF7;PIPEN|=0x08
#define Enable_BIT2_RasingEdge_Trig PICON|=0x10;PINEN&=0xFB;PIPEN|=0x04
#define Enable_BIT1_RasingEdge_Trig PICON|=0x08;PINEN&=0xFD;PIPEN|=0x02
#define Enable_BIT0_RasingEdge_Trig PICON|=0x04;PINEN&=0xFE;PIPEN|=0x01
/*****************************************************************************************
* For TIMER VALUE setting is base on " option -> C51 -> Preprocesser Symbols -> Define "
*****************************************************************************************/
#ifdef FOSC_110592 // if Fsys = 11.0592MHz
#define TIMER_DIV12_VALUE_10us 65536-9 //9*12/11.0592 = 10 uS, // Timer divider = 12 for TM0/TM1
#define TIMER_DIV12_VALUE_1ms 65536-923 //923*12/11.0592 = 1 mS // Timer divider = 12
#define TIMER_DIV12_VALUE_10ms 65536-9216 //18432*12/22118400 = 10 ms // Timer divider = 12
#define TIMER_DIV4_VALUE_10us 65536-28 //28*4/11.0592 = 10 uS // Timer divider = 4 for TM2/TM3
#define TIMER_DIV4_VALUE_1ms 65536-2765 //2765*4/11.0592 = 1 mS // Timer divider = 4
#define TIMER_DIV4_VALUE_100us 65536-277 //553*4/22118400 = 100 us // Timer divider = 4
#define TIMER_DIV4_VALUE_200us 65536-553 //1106*4/22118400 = 200 us // Timer divider = 4
#define TIMER_DIV4_VALUE_500us 65536-1383 //2765*4/22118400 = 500 us // Timer divider = 4
#define TIMER_DIV16_VALUE_10ms 65536-6912 //1500*16/22118400 = 10 ms // Timer divider = 16
#define TIMER_DIV64_VALUE_30ms 65536-5184 //10368*64/22118400 = 30 ms // Timer divider = 64
#define TIMER_DIV128_VALUE_100ms 65536-8640 //17280*128/22118400 = 100 ms // Timer divider = 128
#define TIMER_DIV128_VALUE_200ms 65536-17280 //34560*128/22118400 = 200 ms // Timer divider = 128
#define TIMER_DIV256_VALUE_500ms 65536-21600 //43200*256/22118400 = 500 ms // Timer divider = 256
#define TIMER_DIV512_VALUE_1s 65536-21600 //43200*512/22118400 = 1 s // Timer divider = 512
#endif
#ifdef FOSC_160000 // if Fsys = 16MHz
#define TIMER_DIV12_VALUE_10us 65536-13 //13*12/16000000 = 10 uS, // Timer divider = 12 for TM0/TM1
#define TIMER_DIV12_VALUE_100us 65536-130 //130*12/16000000 = 10 uS, // Timer divider = 12
#define TIMER_DIV12_VALUE_1ms 65536-1334 //1334*12/16000000 = 1 mS, // Timer divider = 12
#define TIMER_DIV12_VALUE_10ms 65536-13334 //13334*12/16000000 = 10 mS // Timer divider = 12
#define TIMER_DIV12_VALUE_40ms 65536-53336 //53336*12/16000000 = 40 ms // Timer divider = 12
#define TIMER_DIV4_VALUE_10us 65536-40 //40*4/16000000 = 10 uS, // Timer divider = 4 for TM2/TM3
#define TIMER_DIV4_VALUE_100us 65536-400 //400*4/16000000 = 100 us // Timer divider = 4
#define TIMER_DIV4_VALUE_200us 65536-800 //800*4/16000000 = 200 us // Timer divider = 4
#define TIMER_DIV4_VALUE_500us 65536-2000 //2000*4/16000000 = 500 us // Timer divider = 4
#define TIMER_DIV4_VALUE_1ms 65536-4000 //4000*4/16000000 = 1 mS, // Timer divider = 4
#define TIMER_DIV16_VALUE_10ms 65536-10000 //10000*16/16000000 = 10 ms // Timer divider = 16
#define TIMER_DIV64_VALUE_30ms 65536-7500 //7500*64/16000000 = 30 ms // Timer divider = 64
#define TIMER_DIV128_VALUE_100ms 65536-12500 //12500*128/16000000 = 100 ms // Timer divider = 128
#define TIMER_DIV128_VALUE_200ms 65536-25000 //25000*128/16000000 = 200 ms // Timer divider = 128
#define TIMER_DIV256_VALUE_500ms 65536-31250 //31250*256/16000000 = 500 ms // Timer divider = 256
#define TIMER_DIV512_VALUE_1s 65536-31250 //31250*512/16000000 = 1 s. // Timer Divider = 512
#endif
#ifdef FOSC_184320 // if Fsys = 18.432MHz
#define TIMER_DIV12_VALUE_10us 65536-15 //15*12/18.432 = 10 uS, Timer Clock = Fsys/12
#define TIMER_DIV12_VALUE_1ms 65536-1536 //1536*12/18.432 = 1 mS, Timer Clock = Fsys/12
#define TIMER_DIV4_VALUE_10us 65536-46 //46*4/18.432 = 10 uS, Timer Clock = Fsys/4
#define TIMER_DIV4_VALUE_1ms 65536-4608 //4608*4/18.432 = 1 mS, Timer Clock = Fsys/4
#endif
#ifdef FOSC_200000 // if Fsys = 20 MHz
#define TIMER_DIV12_VALUE_10us 65536-17 //17*12/20000000 = 10 uS, Timer Clock = Fsys/12
#define TIMER_DIV12_VALUE_1ms 65536-1667 //1667*12/20000000 = 1 mS, Timer Clock = Fsys/12
#define TIMER_DIV4_VALUE_10us 65536-50 //50*4/20000000 = 10 uS, Timer Clock = Fsys/4
#define TIMER_DIV4_VALUE_1ms 65536-5000 //5000*4/20000000 = 1 mS, Timer Clock = Fsys/4
#endif
#ifdef FOSC_221184 // if Fsys = 22.1184 MHz
#define TIMER_DIV12_VALUE_10us 65536-18 //18*12/22118400 = 10 uS, // Timer divider = 12
#define TIMER_DIV12_VALUE_1ms 65536-1843 //1843*12/22118400 = 1 mS, // Timer divider = 12
#define TIMER_DIV12_VALUE_10ms 65536-18432 //18432*12/22118400 = 10 ms // Timer divider = 12
#define TIMER_DIV4_VALUE_10us 65536-56 //9*4/22118400 = 10 uS, // Timer divider = 4
#define TIMER_DIV4_VALUE_1ms 65536-5530 //923*4/22118400 = 1 mS, // Timer divider = 4
#define TIMER_DIV4_VALUE_100us 65536-553 //553*4/22118400 = 100 us // Timer divider = 4
#define TIMER_DIV4_VALUE_200us 65536-1106 //1106*4/22118400 = 200 us // Timer divider = 4
#define TIMER_DIV4_VALUE_500us 65536-2765 //2765*4/22118400 = 500 us // Timer divider = 4
#define TIMER_DIV16_VALUE_10ms 65536-13824 //1500*16/22118400 = 10 ms // Timer divider = 16
#define TIMER_DIV64_VALUE_30ms 65536-10368 //10368*64/22118400 = 30 ms // Timer divider = 64
#define TIMER_DIV128_VALUE_100ms 65536-17280 //17280*128/22118400 = 100 ms // Timer divider = 128
#define TIMER_DIV128_VALUE_200ms 65536-34560 //34560*128/22118400 = 200 ms // Timer divider = 128
#define TIMER_DIV256_VALUE_500ms 65536-43200 //43200*256/22118400 = 500 ms // Timer divider = 256
#define TIMER_DIV512_VALUE_1s 65536-43200 //43200*512/22118400 = 1 s // Timer divider = 512
#endif
#ifdef FOSC_240000 // if Fsys = 20 MHz
#define TIMER_DIV12_VALUE_10us 65536-20 //20*12/24000000 = 10 uS, // Timer divider = 12
#define TIMER_DIV12_VALUE_1ms 65536-2000 //2000*12/24000000 = 1 mS, // Timer divider = 12
#define TIMER_DIV12_VALUE_10ms 65536-20000 //2000*12/24000000 = 10 mS // Timer divider = 12
#define TIMER_DIV4_VALUE_10us 65536-60 //60*4/24000000 = 10 uS, // Timer divider = 4
#define TIMER_DIV4_VALUE_100us 65536-600 //600*4/24000000 = 100 us // Timer divider = 4
#define TIMER_DIV4_VALUE_200us 65536-1200 //1200*4/24000000 = 200 us // Timer divider = 4
#define TIMER_DIV4_VALUE_500us 65536-3000 //3000*4/24000000 = 500 us // Timer divider = 4
#define TIMER_DIV4_VALUE_1ms 65536-6000 //6000*4/24000000 = 1 mS, // Timer divider = 4
#define TIMER_DIV16_VALUE_10ms 65536-15000 //15000*16/24000000 = 10 ms // Timer divider = 16
#define TIMER_DIV64_VALUE_30ms 65536-11250 //11250*64/24000000 = 30 ms // Timer divider = 64
#define TIMER_DIV128_VALUE_100ms 65536-18750 //37500*128/24000000 = 200 ms // Timer divider = 128
#define TIMER_DIV128_VALUE_200ms 65536-37500 //37500*128/24000000 = 200 ms // Timer divider = 128
#define TIMER_DIV256_VALUE_500ms 65536-46875 //46875*256/24000000 = 500 ms // Timer divider = 256
#define TIMER_DIV512_VALUE_1s 65536-46875 //46875*512/24000000 = 1 s. // Timer Divider = 512
#endif
//-------------------- Timer0 function define --------------------
#define TIMER1_MODE0_ENABLE TMOD&=0x0F
#define TIMER1_MODE1_ENABLE TMOD&=0x0F;TMOD|=0x10
#define TIMER1_MODE2_ENABLE TMOD&=0x0F;TMOD|=0x20
#define TIMER1_MODE3_ENABLE TMOD&=0x0F;TMOD|=0x30
//-------------------- Timer1 function define --------------------
#define TIMER0_MODE0_ENABLE TMOD&=0xF0
#define TIMER0_MODE1_ENABLE TMOD&=0xF0;TMOD|=0x01
#define TIMER0_MODE2_ENABLE TMOD&=0xF0;TMOD|=0x02
#define TIMER0_MODE3_ENABLE TMOD&=0xF0;TMOD|=0x03
//-------------------- Timer2 function define --------------------
#define TIMER2_DIV_4 T2MOD|=0x10;T2MOD&=0x9F
#define TIMER2_DIV_16 T2MOD|=0x20;T2MOD&=0xAF
#define TIMER2_DIV_32 T2MOD|=0x30;T2MOD&=0xBF
#define TIMER2_DIV_64 T2MOD|=0x40;T2MOD&=0xCF
#define TIMER2_DIV_128 T2MOD|=0x50;T2MOD&=0xDF
#define TIMER2_DIV_256 T2MOD|=0x60;T2MOD&=0xEF
#define TIMER2_DIV_512 T2MOD|=0x70
#define TIMER2_Auto_Reload_Delay_Mode T2CON&=~SET_BIT0;T2MOD|=SET_BIT7;T2MOD|=SET_BIT3
#define TIMER2_Compare_Capture_Mode T2CON|=SET_BIT0;T2MOD&=~SET_BIT7;T2MOD|=SET_BIT2
#define TIMER2_CAP0_Capture_Mode T2CON&=~SET_BIT0;T2MOD=0x89
#define TIMER2_CAP1_Capture_Mode T2CON&=~SET_BIT0;T2MOD=0x8A
#define TIMER2_CAP2_Capture_Mode T2CON&=~SET_BIT0;T2MOD=0x8B
//-------------------- Timer2 Capture define --------------------
//--- Falling Edge -----
#define IC0_P12_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC1_P11_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x01;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC2_P10_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x02;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC3_P00_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x03;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC3_P04_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x04;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC4_P01_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x05;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC5_P03_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x06;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC6_P05_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x07;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC7_P15_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x08;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC0_P12_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5
#define IC1_P11_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x10;CAPCON0|=SET_BIT5;CAPCON0|=SET_BIT5
#define IC2_P10_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x20;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5
#define IC3_P00_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x30;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5
#define IC3_P04_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x40;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5
#define IC4_P01_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x50;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5
#define IC5_P03_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x60;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5
#define IC6_P05_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x70;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5
#define IC7_P15_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x80;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5
#define IC0_P12_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6
#define IC1_P11_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x10;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6
#define IC2_P10_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x20;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6
#define IC3_P00_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x30;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6
#define IC3_P04_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x40;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6
#define IC4_P01_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x50;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6
#define IC5_P03_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x60;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6
#define IC6_P05_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x70;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6
#define IC7_P15_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x80;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6
//----- Rising edge ----
#define IC0_P12_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;
#define IC1_P11_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x01;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;
#define IC2_P10_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x02;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;
#define IC3_P00_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x03;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;
#define IC3_P04_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x04;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;
#define IC4_P01_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x05;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;
#define IC5_P03_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x06;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;
#define IC6_P05_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x07;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;
#define IC7_P15_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x08;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4;
#define IC0_P12_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0FCAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC1_P11_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x10;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC2_P10_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x20;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC3_P00_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x30;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC3_P04_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x40;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC4_P01_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x50;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC5_P03_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x60;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC6_P05_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x70;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC7_P15_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x80;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC0_P12_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC1_P11_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x01;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC2_P10_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x02;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC3_P00_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x03;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC3_P04_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x04;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC4_P01_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x05;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC5_P03_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x06;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC6_P05_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x07;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC7_P15_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x08;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
//-----BOTH edge ----
#define IC0_P12_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC1_P11_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x01;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC2_P10_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x02;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC3_P00_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x03;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC3_P04_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x04;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC4_P01_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x05;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC5_P03_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x06;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC6_P05_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x07;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC7_P15_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x08;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4
#define IC0_P12_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5
#define IC1_P11_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x10;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC2_P10_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x20;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC3_P00_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x30;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC3_P04_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x40;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC4_P01_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x50;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC5_P03_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x60;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC6_P05_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x70;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC7_P15_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x80;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5;
#define IC0_P12_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC1_P11_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x01;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC2_P10_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x02;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC3_P00_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x03;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC3_P04_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x04;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC4_P01_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x05;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC5_P03_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x06;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC6_P05_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x07;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define IC7_P15_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x08;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6;
#define TIMER2_IC2_DISABLE CAPCON0&=~SET_BIT6
#define TIMER2_IC1_DISABLE CAPCON0&=~SET_BIT5
#define TIMER2_IC0_DISABLE CAPCON0&=~SET_BIT4
/*****************************************************************************************
* For PWM setting
*****************************************************************************************/
//--------- PMW clock source select define ---------------------
#define PWM_CLOCK_FSYS CKCON&=0xBF
#define PWM_CLOCK_TIMER1 CKCON|=0x40
//--------- PWM clock devide define ----------------------------
#define PWM_CLOCK_DIV_2 PWMCON1|=0x01;PWMCON1&=0xF9
#define PWM_CLOCK_DIV_4 PWMCON1|=0x02;PWMCON1&=0xFA
#define PWM_CLOCK_DIV_8 PWMCON1|=0x03;PWMCON1&=0xFB
#define PWM_CLOCK_DIV_16 PWMCON1|=0x04;PWMCON1&=0xFC
#define PWM_CLOCK_DIV_32 PWMCON1|=0x05;PWMCON1&=0xFD
#define PWM_CLOCK_DIV_64 PWMCON1|=0x06;PWMCON1&=0xFE
#define PWM_CLOCK_DIV_128 PWMCON1|=0x07
//--------- PWM I/O select define ------------------------------
#define PWM5_P15_OUTPUT_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x20;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.5 as PWM5 output enable
#define PWM5_P03_OUTPUT_ENABLE PIOCON0|=0x20 //P0.3 as PWM5
#define PWM4_P01_OUTPUT_ENABLE PIOCON0|=0x10 //P0.1 as PWM4 output enable
#define PWM3_P04_OUTPUT_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x08;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P0.4 as PWM3 output enable
#define PWM3_P00_OUTPUT_ENABLE PIOCON0|=0x08 //P0.0 as PWM3
#define PWM2_P05_OUTPUT_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x04;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.0 as PWM2 output enable
#define PWM2_P10_OUTPUT_ENABLE PIOCON0|=0x04 //P1.0 as PWM2
#define PWM1_P14_OUTPUT_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x02;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.4 as PWM1 output enable
#define PWM1_P11_OUTPUT_ENABLE PIOCON0|=0x02 //P1.1 as PWM1
#define PWM0_P12_OUTPUT_ENABLE PIOCON0|=0x01 //P1.2 as PWM0 output enable
#define ALL_PWM_OUTPUT_ENABLE PIOCON0=0xFF;PIOCON1=0xFF
#define PWM5_P15_OUTPUT_DISABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xDF;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.5 as PWM5 output disable
#define PWM5_P03_OUTPUT_DISABLE PIOCON0&=0xDF //P0.3 as PWM5
#define PWM4_P01_OUTPUT_DISABLE PIOCON0&=0xEF //P0.1 as PWM4 output disable
#define PWM3_P04_OUTPUT_DISABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xF7;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P0.4 as PWM3 output disable
#define PWM3_P00_OUTPUT_DISABLE PIOCON0&=0xF7 //P0.0 as PWM3
#define PWM2_P05_OUTPUT_DISABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xFB;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.0 as PWM2 output disable
#define PWM2_P10_OUTPUT_DISABLE PIOCON0&=0xFB //P1.0 as PWM2
#define PWM1_P14_OUTPUT_DISABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xFD;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.4 as PWM1 output disable
#define PWM1_P11_OUTPUT_DISABLE PIOCON0&=0xFD //P1.1 as PWM1
#define PWM0_P12_OUTPUT_DISABLE PIOCON0&=0xFE //P1.2 as PWM0 output disable
#define ALL_PWM_OUTPUT_DISABLE PIOCON0=0x00;PIOCON1=0x00
//--------- PWM I/O Polarity Control ---------------------------
#define PWM5_OUTPUT_INVERSE PNP|=0x20
#define PWM4_OUTPUT_INVERSE PNP|=0x10
#define PWM3_OUTPUT_INVERSE PNP|=0x08
#define PWM2_OUTPUT_INVERSE PNP|=0x04
#define PWM1_OUTPUT_INVERSE PNP|=0x02
#define PWM0_OUTPUT_INVERSE PNP|=0x01
#define PWM_OUTPUT_ALL_INVERSE PNP=0xFF
#define PWM5_OUTPUT_NORMAL PNP&=0xDF
#define PWM4_OUTPUT_NORMAL PNP&=0xEF
#define PWM3_OUTPUT_NORMAL PNP&=0xF7
#define PWM2_OUTPUT_NORMAL PNP&=0xFB
#define PWM1_OUTPUT_NORMAL PNP&=0xFD
#define PWM0_OUTPUT_NORMAL PNP&=0xFE
#define PWM_OUTPUT_ALL_NORMAL PNP=0x00
//--------- PWM type define ------------------------------------
#define PWM_EDGE_TYPE PWMCON1&=~SET_BIT4
#define PWM_CENTER_TYPE PWMCON1|=SET_BIT4
//--------- PWM mode define ------------------------------------
#define PWM_IMDEPENDENT_MODE PWMCON1&=0x3F
#define PWM_COMPLEMENTARY_MODE PWMCON1|=0x40;PWMCON1&=0x7F
#define PWM_SYNCHRONIZED_MODE PWMCON1|=0x80;PWMCON1&=0xBF
#define PWM_GP_MODE_ENABLE PWMCON1|=0x20
#define PWM_GP_MODE_DISABLE PWMCON1&=0xDF
//--------- PMW interrupt setting ------------------------------
#define PWM_FALLING_INT BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xCF;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
#define PWM_RISING_INT BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=0x10;PWMCON0&=0xDF;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
#define PWM_CENTRAL_POINT_INT BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=0x20;PWMCON0&=0xEF;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
#define PWM_PERIOD_END_INT BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=0x30;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
//--------- PWM interrupt pin select ---------------------------
#define PWM_INT_PWM0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
#define PWM_INT_PWM1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x01;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
#define PWM_INT_PWM2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x02;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
#define PWM_INT_PWM3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x03;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
#define PWM_INT_PWM4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x04;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
#define PWM_INT_PWM5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x05;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
//--------- PWM Dead time setting ------------------------------
#define PWM45_DEADTIME_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=0x04;EA=BIT_TMP
#define PWM34_DEADTIME_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=0x02;EA=BIT_TMP
#define PWM01_DEADTIME_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=0x01;EA=BIT_TMP
/*****************************************************************************************
* For ADC INIT setting
*****************************************************************************************/
#define Enable_ADC_AIN0 ADCCON0&=0xF0;P17_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT0;ADCCON1|=SET_BIT0 //P17
#define Enable_ADC_AIN1 ADCCON0&=0xF0;ADCCON0|=0x01;P30_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT1;ADCCON1|=SET_BIT0 //P30
#define Enable_ADC_AIN2 ADCCON0&=0xF0;ADCCON0|=0x02;P07_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT2;ADCCON1|=SET_BIT0 //P07
#define Enable_ADC_AIN3 ADCCON0&=0xF0;ADCCON0|=0x03;P06_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT3;ADCCON1|=SET_BIT0 //P06
#define Enable_ADC_AIN4 ADCCON0&=0xF0;ADCCON0|=0x04;P05_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT4;ADCCON1|=SET_BIT0 //P05
#define Enable_ADC_AIN5 ADCCON0&=0xF0;ADCCON0|=0x05;P04_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT5;ADCCON1|=SET_BIT0 //P04
#define Enable_ADC_AIN6 ADCCON0&=0xF0;ADCCON0|=0x06;P03_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT6;ADCCON1|=SET_BIT0 //P03
#define Enable_ADC_AIN7 ADCCON0&=0xF0;ADCCON0|=0x07;P11_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT7;ADCCON1|=SET_BIT0 //P11
#define Enable_ADC_BandGap ADCCON0|=SET_BIT3;ADCCON0&=0xF8;ADCCON1|=SET_BIT0 //Band-gap 1.22V
#define Disable_ADC ADCCON1&=0xFE;
#define PWM0_FALLINGEDGE_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1
#define PWM2_FALLINGEDGE_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1
#define PWM4_FALLINGEDGE_TRIG_ADC ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1
#define PWM0_RISINGEDGE_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1
#define PWM2_RISINGEDGE_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1
#define PWM4_RISINGEDGE_TRIG_ADC ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1
#define PWM0_CENTRAL_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1
#define PWM2_CENTRAL_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1
#define PWM4_CENTRAL_TRIG_ADC ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1
#define PWM0_END_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1
#define PWM2_END_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1
#define PWM4_END_TRIG_ADC ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1
#define P04_FALLINGEDGE_TRIG_ADC ADCCON0|=0x30;ADCCON1&=0xF3;ADCCON1|=SET_BIT1;ADCCON1&=~SET_BIT6
#define P13_FALLINGEDGE_TRIG_ADC ADCCON0|=0x30;ADCCON1&=0xF3;ADCCON1|=SET_BIT1;ADCCON1|=SET_BIT6
#define P04_RISINGEDGE_TRIG_ADC ADCCON0|=0x30;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;ADCCON1&=~SET_BIT6
#define P13_RISINGEDGE_TRIG_ADC ADCCON0|=0x30;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;ADCCON1|=SET_BIT6
/*****************************************************************************************
* For SPI INIT setting
*****************************************************************************************/
#define SPICLK_DIV2 clr_SPR0;clr_SPR1
#define SPICLK_DIV4 set_SPR0;clr_SPR1
#define SPICLK_DIV8 clr_SPR0;set_SPR1
#define SPICLK_DIV16 set_SPR0;set_SPR1
#define Enable_SPI_Interrupt set_ESPI;set_EA
#define SS P15

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lctech-relay-altfw/build.sh Executable file
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sdcc -mmcs51 -o 2relays.ihx main.c -D FOSC_160000 -I../include

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lctech-relay-altfw/config.json Normal file
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{
"boot_select": "aprom",
"pwm_enabled_during_ocd": false,
"ocd_enabled": true,
"reset_pin_disabled": false,
"locked": false,
"ldrom_size": "0kb",
"bod_disabled": false,
"bod_voltage": "2v2",
"iap_enabled_in_brownout": false,
"bod_reset_disabled": false,
"wdt": "disabled"
}

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lctech-relay-altfw/main.c Normal file
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#include <nuvoton/functions.h>
#include <nuvoton/N76E003.h>
#include <nuvoton/Common.h>
#include <nuvoton/Delay.h>
#include <nuvoton/SFR_Macro.h>
#include <string.h>
#define RELAY1 P12
#define RELAY2 P15
#define RED P01
#define GREEN P04
#define BLUE P03
#define PWM_GREEN PWM3L
#define PWM_BLUE PWM5L
#define PWM_RED PWM4L
#define BUTTON1 P00
#define BUTTON2 P10
#define MAXCMD 64
__sbit BIT_TMP;
__sbit S1;
__sbit S2;
unsigned char crc;
unsigned char getchar1(void)
{
UINT8 c;
while (!RI);
c = SBUF;
RI = 0;
return (c);
}
int putchar1 (unsigned char c)
{
crc += c;
TI = 0;
SBUF = c;
while(TI==0);
return 0;
}
void sendpkt(unsigned char cmd, unsigned int len, unsigned char *buffer) {
unsigned int i;
crc = 0;
putchar1(0x55);
putchar1(0xAA);
putchar1(0x03);
putchar1(cmd);
putchar1(len >> 8);
putchar1(len & 0xFF);
for (i=0; i<len; i++) {
putchar1(buffer[i]);
}
putchar1(crc);
}
void tuya_receive (unsigned int len, unsigned char *buffer) {
unsigned char dpid;
unsigned char dtype;
unsigned int dlen;
if (len < 4) return;
dpid = buffer[0];
dtype = buffer[1];
dlen = buffer[2] << 8 + buffer[3];
switch(dpid) {
case 1:
RELAY1 = buffer[4] ? 0 : 1;
break;
case 2:
RELAY2 = buffer[4] ? 0 : 1;
break;
case 3:
BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;
PWM_RED = buffer[4];
TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP;
LOAD = 1;
break;
case 4:
PWM_GREEN = buffer[4];
LOAD = 1;
break;
case 5:
BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;
PWM_BLUE = buffer[4];
TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP;
LOAD = 1;
break;
}
sendpkt(7, len, buffer);
}
void process(unsigned char cmd, unsigned int len, unsigned char *buffer) {
static unsigned char restart = 0;
switch (cmd) {
case 0: /* Heartbeat */
buffer[0] = restart;
restart = 1;
sendpkt(0, 1, buffer);
break;
case 1: /* Identify */
strcpy(buffer,"Nuovo");
len = strlen(buffer);
sendpkt(1, len, buffer);
break;
case 3: /* WIFI State */
sendpkt(3, 0, NULL);
break;
case 6: /* Set Command */
tuya_receive(len, buffer);
break;
case 8: /* Query Command */
break;
}
}
void recvpkt(void)
{
static unsigned char state = 0;
static unsigned char cmd;
static unsigned int len;
static unsigned char rcrc;
static unsigned char i;
static unsigned char command[MAXCMD];
if (RI) {
int inByte = getchar1();
switch (state) {
case 0:
if (inByte == 0x55) state++;
rcrc = 0;
break;
case 1:
if (inByte == 0xaa) state++; else state = 0;
break;
case 2:
if (inByte == 0) state++; else state = 0;
break;
case 3:
cmd = inByte;
state++;
break;
case 4:
len = inByte << 8;
state++;
break;
case 5:
len += inByte;
if (len < MAXCMD) state++; else state = 0;
if (len == 0) state++;
i = 0;
break;
case 6:
command[i] = inByte;
i++;
if (len == i) state++;
break;
case 7:
if (inByte == rcrc)
process(cmd, len, command);
state = 0;
break;
}
rcrc = rcrc + inByte;
}
}
void uart_loop() {
static unsigned int S1_debounce = 0;
static unsigned int S2_debounce = 0;
unsigned char buf[5];
recvpkt();
if (BUTTON1 != S1) {
if (S1_debounce == 4096) {
S1 = BUTTON1;
S1_debounce = 0;
if (!S1) {
RELAY1 = !RELAY1;
buf[0] = 1;
buf[1] = 1;
buf[2] = 0;
buf[3] = 1;
buf[4] = (1 - RELAY1);
sendpkt(7, 5, buf);
}
}
S1_debounce++;
} else {
S1_debounce = 0;
}
if (BUTTON2 != S2) {
if (S2_debounce == 4096) {
S2 = BUTTON2;
S2_debounce = 0;
if (!S2) {
RELAY2 = !RELAY2;
buf[0] = 2;
buf[1] = 1;
buf[2] = 0;
buf[3] = 1;
buf[4] = (1 - RELAY2);
sendpkt(7, 5, buf);
}
}
S2_debounce++;
} else {
S2_debounce = 0;
}
}
void uart_init(UINT32 u32Baudrate) //T1M = 1, SMOD = 1
{
P06_PushPull_Mode;
P07_Input_Mode;
SCON = 0x50; //UART0 Mode1,REN=1,TI=1
TMOD |= 0x20; //Timer1 Mode1
set_SMOD; //UART0 Double Rate Enable
set_T1M;
clr_BRCK; //Serial port 0 baud rate clock source = Timer1
#ifdef FOSC_160000
TH1 = 256 - (1000000 / u32Baudrate + 1); /*16 MHz */
#endif
#ifdef FOSC_166000
TH1 = 256 - (1037500 / u32Baudrate); /*16.6 MHz */
#endif
set_TR1;
set_TI; //For printf function must setting TI = 1
}
int main()
{
uart_init(9600);
/* Relays */
RELAY1 = 0;
RELAY2 = 0;
P12_PushPull_Mode;
P15_PushPull_Mode;
/* LEDS */
P01_PushPull_Mode;
P04_PushPull_Mode;
P03_PushPull_Mode;
/* Buttons */
P00_Quasi_Mode;
P10_Quasi_Mode;
/* buttonz */
PWMPH = 0;
PWMPL = 255;
PWM_CLOCK_FSYS;
PWM_CLOCK_DIV_128;
PWM_IMDEPENDENT_MODE;
PWM_EDGE_TYPE;
PWM5_P03_OUTPUT_ENABLE;
PWM3_P04_OUTPUT_ENABLE;
PWM4_P01_OUTPUT_ENABLE;
RED = 0;
GREEN = 0;
BLUE = 0;
BUTTON1 = 1;
BUTTON2 = 1;
S1 = 0;
S2 = 0;
BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;
PWM4H = 0;
PWM_RED = 0;
PWM5H = 0;
PWM_BLUE = 0;
TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP;
PWM3H = 0;
PWM_GREEN = 0;
LOAD = 1;
PWMRUN = 1;
while (1)
{
uart_loop();
}
}

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n76e003_blink/blink_raw.c Normal file
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/* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#include <stdint.h>
#include "n76e003.h"
// 16Mhz clock
#define CLOCK 16000000L
// Divide by 12
#define T0CLOCK ((CLOCK)/12L)
// Per milisecond
#define T0_1MS ((T0CLOCK)/1000L)
static void msdelay(uint32_t count)
{
int16_t reload = -T0_1MS;
// Input = Fsys/12
SET_FIELD(CKCON, T0M, 0);
// Mode 1
SET_FIELD(TMOD, T0M, 1);
// Start
TR0 = 1;
while (count != 0)
{
TL0 = reload & 0xFF;
TH0 = reload >> 8 & 0xFF;;
while(!TF0);
TF0 = 0;
count--;
}
TR0 = 0;
}
void main() {
// Set pins in old-skool Quasi Bidirectional mode
P0M1 = 0;
P0M2 = 0;
P1M1 = 0;
P1M2 = 0;
P3M1 = 0;
P3M2 = 0;
for (;;) {
int i;
for (i = 0; i < 10; i++) {
P01 = 0;
P13 = 0;
msdelay(500);
P01 = 0;
P13 = 0;
msdelay(500);
P01 = 0;
P13 = 0;
msdelay(500);
P01 = 0;
P13 = 0;
msdelay(500);
}
}
}

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n76e003_blink/config.json Normal file
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{
"boot_select": "aprom",
"pwm_enabled_during_ocd": false,
"ocd_enabled": true,
"reset_pin_disabled": false,
"locked": false,
"ldrom_size": "0kb",
"bod_disabled": false,
"bod_voltage": "2v2",
"iap_enabled_in_brownout": false,
"bod_reset_disabled": false,
"wdt": "disabled"
}

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n76e003_blink/n76e003.h Normal file
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/* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef N76E003_H
#define N76E003_H
#include <compiler.h>
#define DEFINE_FIELD(reg, field, bit, len) \
reg##_##field##_Pos = (bit), \
reg##_##field##_Msk = (((1 << (len)) - 1) << (bit)),
#define GET_FIELD(reg, field) \
(((reg) & reg##_##field##_Msk) >> reg##_##field##_Pos)
#define SET_FIELD(reg, field, val) \
do { \
(reg) = ((reg) & ~(reg##_##field##_Msk)) | \
(((val) << (reg##_##field##_Pos)) & (reg##_##field##_Msk)); \
} while(0)
SFR(P0, 0x80);
SFR(SP, 0x81);
SFR(DPL, 0x82);
SFR(DPH, 0x83);
SFR(RCTRIM0, 0x84);
SFR(RCTRIM1, 0x85);
SFR(RWK, 0x86);
SFR(PCON, 0x87);
enum {
DEFINE_FIELD(PCON, SMOD, 7, 1)
DEFINE_FIELD(PCON, SMOD0, 6, 1)
DEFINE_FIELD(PCON, POF, 4, 1)
DEFINE_FIELD(PCON, GF1, 3, 1)
DEFINE_FIELD(PCON, GF0, 2, 1)
DEFINE_FIELD(PCON, PD, 1, 1)
DEFINE_FIELD(PCON, IDL, 0, 1)
};
SFR(TCON, 0x88);
SFR(TMOD, 0x89);
enum {
DEFINE_FIELD(TMOD, T0M, 0, 2)
DEFINE_FIELD(TMOD, T0CT, 2, 1)
DEFINE_FIELD(TMOD, T0GATE, 3, 1)
DEFINE_FIELD(TMOD, T1M, 4, 2)
DEFINE_FIELD(TMOD, T1CT, 6, 1)
DEFINE_FIELD(TMOD, T1GATE, 7, 1)
};
SFR(TL0, 0x8A);
SFR(TL1, 0x8B);
SFR(TH0, 0x8C);
SFR(TH1, 0x8D);
SFR(CKCON, 0x8E);
enum {
DEFINE_FIELD(CKCON, PWMCKS, 6, 1)
DEFINE_FIELD(CKCON, T1M, 4, 1)
DEFINE_FIELD(CKCON, T0M, 3, 1)
DEFINE_FIELD(CKCON, CLOEN, 1, 1)
};
SFR(WKCON, 0x8F);
SFR(P1, 0x90);
SFR(SFRS, 0x91); //TA Protection
SFR(CAPCON0, 0x92);
SFR(CAPCON1, 0x93);
SFR(CAPCON2, 0x94);
SFR(CKDIV, 0x95);
SFR(CKSWT, 0x96); //TA Protection
SFR(CKEN, 0x97); //TA Protection
SFR(SCON, 0x98);
SFR(SBUF, 0x99);
SFR(SBUF_1, 0x9A);
SFR(EIE, 0x9B);
SFR(EIE1, 0x9C);
SFR(CHPCON, 0x9F); //TA Protection
enum {
EIE_ET2_BIT = (1 << 7),
EIE_ESPI_BIT = (1 << 6),
EIE_EFB_BIT = (1 << 5),
EIE_EWDT_BIT = (1 << 4),
EIE_EPWM_BIT = (1 << 3),
EIE_ECAP_BIT = (1 << 2),
EIE_EPI_BIT = (1 << 1),
EIE_EI2C_BIT = (1 << 1),
};
SFR(P2, 0xA0);
SFR(AUXR1, 0xA2);
SFR(BODCON0, 0xA3); //TA Protection
SFR(IAPTRG, 0xA4); //TA Protection
SFR(IAPUEN, 0xA5); //TA Protection
SFR(IAPAL, 0xA6);
SFR(IAPAH, 0xA7);
SFR(IE, 0xA8);
SFR(SADDR, 0xA9);
SFR(WDCON, 0xAA); //TA Protection
SFR(BODCON1, 0xAB); //TA Protection
SFR(P3M1, 0xAC);
SFR(P3S, 0xAC); //Page1
SFR(P3M2, 0xAD);
SFR(P3SR, 0xAD); //Page1
SFR(IAPFD, 0xAE);
SFR(IAPCN, 0xAF);
SFR(P3, 0xB0);
SFR(P0M1, 0xB1);
SFR(P0S, 0xB1); //Page1
SFR(P0M2, 0xB2);
SFR(P0SR, 0xB2); //Page1
SFR(P1M1, 0xB3);
SFR(P1S, 0xB3); //Page1
SFR(P1M2, 0xB4);
SFR(P1SR, 0xB4); //Page1
SFR(P2S, 0xB5);
SFR(IPH, 0xB7);
SFR(PWMINTC, 0xB7); //Page1
SFR(IP, 0xB8);
SFR(SADEN, 0xB9);
SFR(SADEN_1, 0xBA);
SFR(SADDR_1, 0xBB);
SFR(I2DAT, 0xBC);
SFR(I2STAT, 0xBD);
SFR(I2CLK, 0xBE);
SFR(I2TOC, 0xBF);
SFR(I2CON, 0xC0);
SFR(I2ADDR, 0xC1);
enum {
I2CSTAT_BUS_ERROR = 0x00,
I2CSTAT_BUS_RELEASED = 0xF8,
I2CSTAT_M_START = 0x08,
I2CSTAT_M_REPEAT_START = 0x10,
I2CSTAT_M_TX_ADDR_ACK = 0x18,
I2CSTAT_M_TX_ADDR_NACK = 0x20,
I2CSTAT_M_TX_DATA_ACK = 0x28,
I2CSTAT_M_TX_DATA_NACK = 0x30,
I2CSTAT_M_ARB_LOST = 0x38,
I2CSTAT_M_RX_ADDR_ACK = 0x40,
I2CSTAT_M_RX_ADDR_NACK = 0x48,
I2CSTAT_M_RX_DATA_ACK = 0x50,
I2CSTAT_M_RX_DATA_NACK = 0x58,
I2CSTAT_S_TX_REPEAT_START_OR_STOP = 0xA0,
I2CSTAT_S_TX_ARB_LOST = 0xB0,
I2CSTAT_S_TX_DATA_ACK = 0xB8,
I2CSTAT_S_TX_DATA_NACK = 0xC0,
I2CSTAT_S_TX_LAST_DATA_ACK = 0xC8,
I2CSTAT_S_RX_ACK = 0x60,
I2CSTAT_S_RX_ARB_LOST = 0x68,
I2CSTAT_S_RX_DATA_ACK = 0x80,
I2CSTAT_S_RX_DATA_NACK = 0x88,
I2CSTAT_GC_ADDR_ACK = 0x70,
I2CSTAT_GC_ARB_LOST = 0x78,
I2CSTAT_GC_DATA_ACK = 0x90,
I2CSTAT_GC_DATA_NACK = 0x98,
};
SFR(ADCRL, 0xC2);
SFR(ADCRH, 0xC3);
SFR(T3CON, 0xC4);
enum {
DEFINE_FIELD(T3CON, SMOD_1, 7, 1)
DEFINE_FIELD(T3CON, SMOD0_1, 6, 1)
DEFINE_FIELD(T3CON, BRCK, 5, 1)
DEFINE_FIELD(T3CON, TF3, 4, 1)
DEFINE_FIELD(T3CON, TR3, 3, 1)
DEFINE_FIELD(T3CON, T3PS, 0, 3)
};
SFR(PWM4H, 0xC4); //Page1
SFR(RL3, 0xC5);
SFR(PWM5H, 0xC5); //Page1
SFR(RH3, 0xC6);
SFR(PIOCON1, 0xC6); //Page1
SFR(TA, 0xC7);
SFR(T2CON, 0xC8);
SFR(T2MOD, 0xC9);
SFR(RCMP2L, 0xCA);
SFR(RCMP2H, 0xCB);
SFR(TL2, 0xCC);
SFR(PWM4L, 0xCC); //Page1
SFR(TH2, 0xCD);
SFR(PWM5L, 0xCD); //Page1
SFR(ADCMPL, 0xCE);
SFR(ADCMPH, 0xCF);
SFR(PSW, 0xD0);
SFR(PWMPH, 0xD1);
SFR(PWM0H, 0xD2);
SFR(PWM1H, 0xD3);
SFR(PWM2H, 0xD4);
SFR(PWM3H, 0xD5);
SFR(PNP, 0xD6);
SFR(FBD, 0xD7);
SFR(PWMCON0, 0xD8);
SFR(PWMPL, 0xD9);
SFR(PWM0L, 0xDA);
SFR(PWM1L, 0xDB);
SFR(PWM2L, 0xDC);
SFR(PWM3L, 0xDD);
SFR(PIOCON0, 0xDE);
SFR(PWMCON1, 0xDF);
SFR(ACC, 0xE0);
SFR(ADCCON1, 0xE1);
SFR(ADCCON2, 0xE2);
SFR(ADCDLY, 0xE3);
SFR(C0L, 0xE4);
SFR(C0H, 0xE5);
SFR(C1L, 0xE6);
SFR(C1H, 0xE7);
SFR(ADCCON0, 0xE8);
SFR(PICON, 0xE9);
SFR(PINEN, 0xEA);
SFR(PIPEN, 0xEB);
SFR(PIF, 0xEC);
SFR(C2L, 0xED);
SFR(C2H, 0xEE);
SFR(EIP, 0xEF);
SFR(B, 0xF0);
SFR(CAPCON3, 0xF1);
SFR(CAPCON4, 0xF2);
SFR(SPCR, 0xF3);
SFR(SPCR2, 0xF3); //Page1
SFR(SPSR, 0xF4);
SFR(SPDR, 0xF5);
SFR(AINDIDS, 0xF6);
SFR(EIPH, 0xF7);
SFR(SCON_1, 0xF8);
SFR(PDTEN, 0xF9); //TA Protection
SFR(PDTCNT, 0xFA); //TA Protection
SFR(PMEN, 0xFB);
SFR(PMD, 0xFC);
SFR(EIP1, 0xFE);
SFR(EIPH1, 0xFF);
/* BIT Registers */
/* SCON_1 */
SBIT(SM0_1, 0xF8, 7);
SBIT(FE_1, 0xF8, 7);
SBIT(SM1_1, 0xF8, 6);
SBIT(SM2_1, 0xF8, 5);
SBIT(REN_1, 0xF8, 4);
SBIT(TB8_1, 0xF8, 3);
SBIT(RB8_1, 0xF8, 2);
SBIT(TI_1, 0xF8, 1);
SBIT(RI_1, 0xF8, 0);
/* ADCCON0 */
SBIT(ADCF, 0xE8, 7);
SBIT(ADCS, 0xE8, 6);
SBIT(ETGSEL1,0xE8, 5);
SBIT(ETGSEL0,0xE8, 4);
SBIT(ADCHS3, 0xE8, 3);
SBIT(ADCHS2, 0xE8, 2);
SBIT(ADCHS1, 0xE8, 1);
SBIT(ADCHS0, 0xE8, 0);
/* PWMCON0 */
SBIT(PWMRUN, 0xD8, 7);
SBIT(LOAD, 0xD8, 6);
SBIT(PWMF, 0xD8, 5);
SBIT(CLRPWM, 0xD8, 4);
/* PSW */
SBIT(CY, 0xD0, 7);
SBIT(AC, 0xD0, 6);
SBIT(F0, 0xD0, 5);
SBIT(RS1, 0xD0, 4);
SBIT(RS0, 0xD0, 3);
SBIT(OV, 0xD0, 2);
SBIT(P, 0xD0, 0);
/* T2CON */
SBIT(TF2, 0xC8, 7);
SBIT(TR2, 0xC8, 2);
SBIT(CM_RL2, 0xC8, 0);
/* I2CON
* Naming differs from Nuvoton headers:
* I2C prefixes added to ambiguous bits
*/
SBIT(I2CEN, 0xC0, 6);
SBIT(I2CSTA, 0xC0, 5);
SBIT(I2CSTO, 0xC0, 4);
SBIT(I2CSI, 0xC0, 3);
SBIT(I2CAA, 0xC0, 2);
SBIT(I2CPX, 0xC0, 0);
/* IP */
SBIT(PADC, 0xB8, 6);
SBIT(PBOD, 0xB8, 5);
SBIT(PS, 0xB8, 4);
SBIT(PT1, 0xB8, 3);
SBIT(PX1, 0xB8, 2);
SBIT(PT0, 0xB8, 1);
SBIT(PX0, 0xB8, 0);
/* P3 */
SBIT(P30, 0xB0, 0);
/* IE */
SBIT(EA, 0xA8, 7);
SBIT(EADC, 0xA8, 6);
SBIT(EBOD, 0xA8, 5);
SBIT(ES, 0xA8, 4);
SBIT(ET1, 0xA8, 3);
SBIT(EX1, 0xA8, 2);
SBIT(ET0, 0xA8, 1);
SBIT(EX0, 0xA8, 0);
/* P2 */
SBIT(P20, 0xA0, 0);
/* SCON */
SBIT(SM0, 0x98, 7);
SBIT(FE, 0x98, 7);
SBIT(SM1, 0x98, 6);
SBIT(SM2, 0x98, 5);
SBIT(REN, 0x98, 4);
SBIT(TB8, 0x98, 3);
SBIT(RB8, 0x98, 2);
SBIT(TI, 0x98, 1);
SBIT(RI, 0x98, 0);
/* P1 */
SBIT(P17, 0x90, 7);
SBIT(P16, 0x90, 6);
SBIT(TXD_1, 0x90, 6);
SBIT(P15, 0x90, 5);
SBIT(P14, 0x90, 4);
SBIT(SDA, 0x90, 4);
SBIT(P13, 0x90, 3);
SBIT(SCL, 0x90, 3);
SBIT(P12, 0x90, 2);
SBIT(P11, 0x90, 1);
SBIT(P10, 0x90, 0);
/* TCON */
SBIT(TF1, 0x88, 7);
SBIT(TR1, 0x88, 6);
SBIT(TF0, 0x88, 5);
SBIT(TR0, 0x88, 4);
SBIT(IE1, 0x88, 3);
SBIT(IT1, 0x88, 2);
SBIT(IE0, 0x88, 1);
SBIT(IT0, 0x88, 0);
/* P0 */
SBIT(P07, 0x80, 7);
SBIT(RXD, 0x80, 7);
SBIT(P06, 0x80, 6);
SBIT(TXD, 0x80, 6);
SBIT(P05, 0x80, 5);
SBIT(P04, 0x80, 4);
SBIT(STADC, 0x80, 4);
SBIT(P03, 0x80, 3);
SBIT(P02, 0x80, 2);
SBIT(RXD_1, 0x80, 2);
SBIT(P01, 0x80, 1);
SBIT(MISO, 0x80, 1);
SBIT(P00, 0x80, 0);
SBIT(MOSI, 0x80, 0);
#define TA_UNPROTECT() do { \
TA = 0xAA; \
TA = 0x55; \
} while(0)
#define SFR_PAGE(n) do { \
TA_UNPROTECT(); \
SFRS = n; \
} while (0)
#endif

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/*---------------------------------------------------------------------------------------------------------*/
/* */
/* Copyright(c) 2016 Nuvoton Technology Corp. All rights reserved. */
/* */
/*---------------------------------------------------------------------------------------------------------*/
//***********************************************************************************************************
// Nuvoton Technoledge Corp.
// Website: http://www.nuvoton.com
// E-Mail : MicroC-8bit@nuvoton.com
// Date : Apr/21/2016
//***********************************************************************************************************
#include "nuvoton/N76E003.h"
#include "nuvoton/Common.h"
#include "nuvoton/Delay.h"
#include "nuvoton/SFR_Macro.h"
#include "nuvoton/functions.h"
//-------------------------------------------------------------------------
void Timer0_Delay100us(UINT32 u32CNT)
{
clr_T0M; //T0M=0, Timer0 Clock = Fsys/12
TMOD |= 0x01; //Timer0 is 16-bit mode
set_TR0; //Start Timer0
while (u32CNT != 0)
{
TL0 = LOBYTE(TIMER_DIV12_VALUE_100us); //Find define in "Function_define.h" "TIMER VALUE"
TH0 = HIBYTE(TIMER_DIV12_VALUE_100us);
while (TF0 != 1); //Check Timer0 Time-Out Flag
clr_TF0;
u32CNT --;
}
clr_TR0; //Stop Timer0
}
//------------------------------------------------------------------------------
void Timer0_Delay1ms(UINT32 u32CNT)
{
clr_T0M; //T0M=0, Timer0 Clock = Fsys/12
TMOD |= 0x01; //Timer0 is 16-bit mode
set_TR0; //Start Timer0
while (u32CNT != 0)
{
TL0 = LOBYTE(TIMER_DIV12_VALUE_1ms); //Find define in "Function_define.h" "TIMER VALUE"
TH0 = HIBYTE(TIMER_DIV12_VALUE_1ms);
while (TF0 != 1); //Check Timer0 Time-Out Flag
clr_TF0;
u32CNT --;
}
clr_TR0; //Stop Timer0
}
//------------------------------------------------------------------------------
void Timer1_Delay10ms(UINT32 u32CNT)
{
clr_T1M; //T1M=0, Timer1 Clock = Fsys/12
TMOD |= 0x10; //Timer1 is 16-bit mode
set_TR1; //Start Timer1
while (u32CNT != 0)
{
TL1 = LOBYTE(TIMER_DIV12_VALUE_10ms); //Find define in "Function_define.h" "TIMER VALUE"
TH1 = HIBYTE(TIMER_DIV12_VALUE_10ms);
while (TF1 != 1); //Check Timer1 Time-Out Flag
clr_TF1;
u32CNT --;
}
clr_TR1; //Stop Timer1
}
//------------------------------------------------------------------------------
void Timer2_Delay500us(UINT32 u32CNT)
{
clr_T2DIV2; //Timer2 Clock = Fsys/4
clr_T2DIV1;
set_T2DIV0;
set_TR2; //Start Timer2
while (u32CNT != 0)
{
TL2 = LOBYTE(TIMER_DIV4_VALUE_500us); //Find define in "Function_define.h" "TIMER VALUE"
TH2 = HIBYTE(TIMER_DIV4_VALUE_500us);
while (TF2 != 1); //Check Timer2 Time-Out Flag
clr_TF2;
u32CNT --;
}
clr_TR2; //Stop Timer2
}
//------------------------------------------------------------------------------
void Timer3_Delay100ms(UINT32 u32CNT)
{
T3CON = 0x07; //Timer3 Clock = Fsys/128
set_TR3; //Trigger Timer3
while (u32CNT != 0)
{
RL3 = LOBYTE(TIMER_DIV128_VALUE_100ms); //Find define in "Function_define.h" "TIMER VALUE"
RH3 = HIBYTE(TIMER_DIV128_VALUE_100ms);
while ((T3CON&SET_BIT4) != SET_BIT4); //Check Timer3 Time-Out Flag
clr_TF3;
u32CNT --;
}
clr_TR3; //Stop Timer3
}
//------------------------------------------------------------------------------
void Timer3_Delay10us(UINT32 u32CNT)
{
T3CON = 0x07; //Timer3 Clock = Fsys/128
set_TR3; //Trigger Timer3
while (u32CNT != 0)
{
RL3 = LOBYTE(TIMER_DIV4_VALUE_10us); //Find define in "Function_define.h" "TIMER VALUE"
RH3 = HIBYTE(TIMER_DIV4_VALUE_10us);
while ((T3CON&SET_BIT4) != SET_BIT4); //Check Timer3 Time-Out Flag
clr_TF3;
u32CNT --;
}
clr_TR3; //Stop Timer3
}

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sdcc -mmcs51 -c Delay.c -D FOSC_160000 -I../include
#sdcc -mmcs51 -c Common.c -D FOSC_160000 -I../include
sdcc -mmcs51 -o 2relays.ihx main.c Delay.rel -D FOSC_160000 -I../include

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relay-tuyafw/config.json Normal file
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{
"boot_select": "aprom",
"pwm_enabled_during_ocd": false,
"ocd_enabled": true,
"reset_pin_disabled": false,
"locked": false,
"ldrom_size": "0kb",
"bod_disabled": false,
"bod_voltage": "2v2",
"iap_enabled_in_brownout": false,
"bod_reset_disabled": false,
"wdt": "disabled"
}

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#include <nuvoton/functions.h>
#include <nuvoton/N76E003.h>
#include <nuvoton/Common.h>
#include <nuvoton/SFR_Macro.h>
#include <string.h>
#define RELAY2 P01
#define RELAY1 P13
#define IN1 P05
#define IN2 P15
#define MAXCMD 64
unsigned char crc;
unsigned char getchar1(void)
{
UINT8 c;
while (!RI);
c = SBUF;
RI = 0;
return (c);
}
int putchar1 (unsigned char c)
{
crc += c;
TI = 0;
SBUF = c;
while(TI==0);
return 0;
}
void sendpkt(unsigned char cmd, unsigned int len, unsigned char *buffer) {
unsigned int i;
crc = 0;
putchar1(0x55);
putchar1(0xAA);
putchar1(0x03);
putchar1(cmd);
putchar1(len >> 8);
putchar1(len & 0xFF);
for (i=0; i<len; i++) {
putchar1(buffer[i]);
}
putchar1(crc);
}
void tuya_receive (unsigned int len, unsigned char *buffer) {
unsigned char dpid;
unsigned char dtype;
unsigned int dlen;
if (len < 4) return;
dpid = buffer[0];
dtype = buffer[1];
dlen = buffer[2] << 8 + buffer[3];
switch(dpid) {
case 1:
RELAY1 = buffer[4] ? 1 : 0;
break;
case 2:
RELAY2 = buffer[4] ? 1 : 0;
break;
}
sendpkt(7, len, buffer);
}
void process(unsigned char cmd, unsigned int len, unsigned char *buffer) {
static unsigned char restart = 0;
switch (cmd) {
case 0: /* Heartbeat */
buffer[0] = restart;
restart = 1;
sendpkt(0, 1, buffer);
break;
case 1: /* Identify */
strcpy(buffer,"Nuovo");
len = strlen(buffer);
sendpkt(1, len, buffer);
break;
case 3: /* WIFI State */
sendpkt(3, 0, NULL);
break;
case 6: /* Set Command */
tuya_receive(len, buffer);
break;
case 8: /* Query Command */
break;
}
}
void recvpkt(void)
{
static unsigned char state = 0;
static unsigned char cmd;
static unsigned int len;
static unsigned char rcrc;
static unsigned char i;
static unsigned char command[MAXCMD];
if (RI) {
int inByte = getchar1();
switch (state) {
case 0:
if (inByte == 0x55) state++;
rcrc = 0;
break;
case 1:
if (inByte == 0xaa) state++; else state = 0;
break;
case 2:
if (inByte == 0) state++; else state = 0;
break;
case 3:
cmd = inByte;
state++;
break;
case 4:
len = inByte << 8;
state++;
break;
case 5:
len += inByte;
if (len < MAXCMD) state++; else state = 0;
if (len == 0) state++;
i = 0;
break;
case 6:
command[i] = inByte;
i++;
if (len == i) state++;
break;
case 7:
if (inByte == rcrc)
process(cmd, len, command);
state = 0;
break;
}
rcrc = rcrc + inByte;
}
}
void uart_loop() {
recvpkt();
}
void uart_init(UINT32 u32Baudrate) //T1M = 1, SMOD = 1
{
P06_PushPull_Mode;
P07_Input_Mode;
SCON = 0x50; //UART0 Mode1,REN=1,TI=1
TMOD |= 0x20; //Timer1 Mode1
set_SMOD; //UART0 Double Rate Enable
set_T1M;
clr_BRCK; //Serial port 0 baud rate clock source = Timer1
#ifdef FOSC_160000
TH1 = 256 - (1000000 / u32Baudrate + 1); /*16 MHz */
#endif
#ifdef FOSC_166000
TH1 = 256 - (1037500 / u32Baudrate); /*16.6 MHz */
#endif
set_TR1;
set_TI; //For printf function must setting TI = 1
}
int main()
{
uart_init(9600);
/* Relays */
RELAY1 = 0;
RELAY2 = 0;
P01_PushPull_Mode;
P13_PushPull_Mode;
/* Inputs */
P05_Input_Mode;
P15_Input_Mode;
while (1)
{
uart_loop();
}
}