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Jochen Friedrich 2021-01-01 14:06:20 +01:00
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11
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[ProjectFiles]
HeaderPath=../Drivers/BSP/STM32G0C1E-EV
[Others]
Define=
HALModule=
[Groups]
Application/User=
Doc=../readme.txt;
Drivers/STM32G0xx_HAL_Driver=
Drivers/BSP/STM32G0C1E-EV=../Drivers/BSP/STM32G0C1E-EV/stm32g0c1e_eval_pwr.c;

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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
<head>
<meta charset="utf-8" />
<meta name="generator" content="pandoc" />
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<title>Release Notes for BSP Components Common Drivers</title>
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<div class="row">
<div class="col-sm-12 col-lg-4">
<div class="card fluid">
<div class="sectione dark">
<center>
<h1 id="release-notes-for-bsp-components-common-drivers"><small>Release Notes for</small> <mark>BSP Components Common Drivers</mark></h1>
<p>Copyright © 2017 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img src="../../../../_htmresc/st_logo.png" alt="ST logo" /></a>
</center>
</div>
</div>
<h1 id="license">License</h1>
<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
<h1 id="purpose">Purpose</h1>
<p>This directory contains the BSP components common drivers.</p>
</div>
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
<input type="checkbox" id="collapse-section22" checked aria-hidden="true"> <label for="collapse-section22" aria-hidden="true">V5.1.2 / 03-April-2019</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>Update release notes format</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section21" aria-hidden="true"> <label for="collapse-section21" aria-hidden="true">V5.1.1 / 31-August-2018</label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li>Reformat the BSD 3-Clause license declaration in the files header (replace license terms by a web reference to OSI website where those terms lie)</li>
<li>Correct sensor names in headers files hsensor.h and psensor.h</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section20" aria-hidden="true"> <label for="collapse-section20" aria-hidden="true">V5.1.0 / 21-November-2017</label>
<div>
<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Add dpredriver.h: support of DP redriver class</li>
<li>Add pwrmon.h: support of power monitor class</li>
<li>Add usbtypecswitch.h: support of USB type C switch class</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section19" aria-hidden="true"> <label for="collapse-section19" aria-hidden="true">V5.0.0 / 01-March-2017</label>
<div>
<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>Add hsensor.h: support of humidity class</li>
<li>Add psensor.h: support of pressure class</li>
<li>Update tsensor.h: Temperature can be negative</li>
<li>Update accelero.h: LowPower API can enable or disable the low power mode</li>
<li>Update magneto.h: LowPower API can enable or disable the low power mode</li>
</ul>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">Notes:</span></span></strong></p>
<p>This version breaks the compatibility with previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section18" aria-hidden="true"> <label for="collapse-section18" aria-hidden="true">V4.0.1 / 21-July-2015</label>
<div>
<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>tsensor.h: Fix compilation issue on TSENSOR_InitTypeDef</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section17" aria-hidden="true"> <label for="collapse-section17" aria-hidden="true">V4.0.0 / 22-June-2015</label>
<div>
<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>accelero.h: add *DeInit field in ACCELERO_DrvTypeDef structure</li>
<li>audio.h: add *DeInit field in AUDIO_DrvTypeDef structure</li>
<li>idd.h:
<ul>
<li>add Shunt0StabDelay, Shunt1StabDelay, Shunt2StabDelay, Shunt3StabDelay, Shunt4StabDelay and ShuntNbOnBoard fields in IDD_ConfigTypeDef structure</li>
<li>rename ShuntNumber field to ShuntNbUsed in IDD_ConfigTypeDef structure</li>
</ul></li>
<li>magneto.h: add *DeInit field in MAGNETO_DrvTypeDef structure</li>
</ul>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">Important Note:</span></span></strong></p>
<p>This release V4.0.0 is not backward compatible with V3.0.0.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section16" aria-hidden="true"> <label for="collapse-section16" aria-hidden="true">V3.0.0 / 28-April-2015</label>
<div>
<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>accelero.h: add <em>LowPower</em> field in ACCELERO_DrvTypeDef structure</li>
<li>magneto.h: add <em>LowPower</em> field in MAGNETO_DrvTypeDef structure</li>
<li>gyro.h: add <em>DeInit</em> and <em>LowPower</em> fields in GYRO_DrvTypeDef structure</li>
<li>camera.h: add CAMERA_COLOR_EFFECT_NONE define</li>
<li>idd.h:
<ul>
<li>add MeasureNb, DeltaDelayUnit and DeltaDelayValue fields in IDD_ConfigTypeDef structure</li>
<li>rename PreDelay field to PreDelayUnit in IDD_ConfigTypeDef structure</li>
</ul></li>
</ul>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">Important Note:</span></span></strong></p>
<p>This release V3.0.0 is not backward compatible with V2.2.0.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section155" aria-hidden="true"> <label for="collapse-section155" aria-hidden="true">V2.2.0 / 09-February-2015</label>
<div>
<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>Magnetometer driver function prototypes added (magneto.h file)</li>
<li>Update “idd.h” file to provide DeInit() and WakeUp() services in IDD current measurement driver</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V2.1.0 / 06-February-2015</label>
<div>
<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>IDD current measurement driver function prototypes added (idd.h file)</li>
<li>io.h: add new typedef enum IO_PinState with IO_PIN_RESET and IO_PIN_SET values</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V2.0.0 / 15-December-2014</label>
<div>
<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>Update “io.h” file to support MFX (Multi Function eXpander) device available on some STM32 boards
<ul>
<li>add new entries for IO_ModeTypedef enumeration structure</li>
<li>update the IO_DrvTypeDef structure
<ul>
<li>Update all return values and function parameters to uint32_t</li>
<li>Add a return value for Config field</li>
</ul></li>
</ul></li>
</ul>
<p><strong><span class="underline"><span style="font-size: 10pt; font-family: Verdana; color: black;">Important Note:</span></span></strong></p>
<p>This version V2.0.0 is not backward compatible with V1.2.1.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.2.1 / 02-December-2014</label>
<div>
<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li>gyro.h: change “__GIRO_H” by “__GYRO_H” to fix compilation issue under Mac OS</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.2.0 / 18-June-2014</label>
<div>
<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li>EPD (E Paper Display) driver function prototype added (epd.h file)</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.1.0 / 21-March-2014</label>
<div>
<h2 id="main-changes-12">Main Changes</h2>
<ul>
<li>Temperature Sensor driver function prototype added</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.0.0 / 18-February-2014</label>
<div>
<h2 id="main-changes-13">Main Changes</h2>
<ul>
<li>First official release with Accelerometer, Audio, Camera, Gyroscope, IO, LCD and Touch Screen drivers function prototypes</li>
</ul>
</div>
</div>
</div>
</div>
<footer class="sticky">
For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a>
</footer>
</body>
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USB-PD_Provider_1port/Drivers/BSP/Components/Common/accelero.h Normal file
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/**
******************************************************************************
* @file accelero.h
* @author MCD Application Team
* @brief This header file contains the functions prototypes for the Accelerometer driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __ACCELERO_H
#define __ACCELERO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup ACCELERO
* @{
*/
/** @defgroup ACCELERO_Exported_Types
* @{
*/
/** @defgroup ACCELERO_Driver_structure Accelerometer Driver structure
* @{
*/
typedef struct
{
void (*Init)(uint16_t);
void (*DeInit)(void);
uint8_t (*ReadID)(void);
void (*Reset)(void);
void (*LowPower)(uint16_t);
void (*ConfigIT)(void);
void (*EnableIT)(uint8_t);
void (*DisableIT)(uint8_t);
uint8_t (*ITStatus)(uint16_t);
void (*ClearIT)(void);
void (*FilterConfig)(uint8_t);
void (*FilterCmd)(uint8_t);
void (*GetXYZ)(int16_t *);
}ACCELERO_DrvTypeDef;
/**
* @}
*/
/** @defgroup ACCELERO_Configuration_structure Accelerometer Configuration structure
* @{
*/
/* ACCELERO struct */
typedef struct
{
uint8_t Power_Mode; /* Power-down/Normal Mode */
uint8_t AccOutput_DataRate; /* OUT data rate */
uint8_t Axes_Enable; /* Axes enable */
uint8_t High_Resolution; /* High Resolution enabling/disabling */
uint8_t BlockData_Update; /* Block Data Update */
uint8_t Endianness; /* Endian Data selection */
uint8_t AccFull_Scale; /* Full Scale selection */
uint8_t Communication_Mode;
}ACCELERO_InitTypeDef;
/* ACCELERO High Pass Filter struct */
typedef struct
{
uint8_t HighPassFilter_Mode_Selection; /* Internal filter mode */
uint8_t HighPassFilter_CutOff_Frequency; /* High pass filter cut-off frequency */
uint8_t HighPassFilter_AOI1; /* HPF_enabling/disabling for AOI function on interrupt 1 */
uint8_t HighPassFilter_AOI2; /* HPF_enabling/disabling for AOI function on interrupt 2 */
uint8_t HighPassFilter_Data_Sel;
uint8_t HighPassFilter_Stat;
}ACCELERO_FilterConfigTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ACCELERO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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USB-PD_Provider_1port/Drivers/BSP/Components/Common/audio.h Normal file
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/**
******************************************************************************
* @file audio.h
* @author MCD Application Team
* @brief This header file contains the common defines and functions prototypes
* for the Audio driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AUDIO_H
#define __AUDIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup AUDIO
* @{
*/
/** @defgroup AUDIO_Exported_Constants
* @{
*/
/* Codec audio Standards */
#define CODEC_STANDARD 0x04
#define I2S_STANDARD I2S_STANDARD_PHILIPS
/**
* @}
*/
/** @defgroup AUDIO_Exported_Types
* @{
*/
/** @defgroup AUDIO_Driver_structure Audio Driver structure
* @{
*/
typedef struct
{
uint32_t (*Init)(uint16_t, uint16_t, uint8_t, uint32_t);
void (*DeInit)(void);
uint32_t (*ReadID)(uint16_t);
uint32_t (*Play)(uint16_t, uint16_t*, uint16_t);
uint32_t (*Pause)(uint16_t);
uint32_t (*Resume)(uint16_t);
uint32_t (*Stop)(uint16_t, uint32_t);
uint32_t (*SetFrequency)(uint16_t, uint32_t);
uint32_t (*SetVolume)(uint16_t, uint8_t);
uint32_t (*SetMute)(uint16_t, uint32_t);
uint32_t (*SetOutputMode)(uint16_t, uint8_t);
uint32_t (*Reset)(uint16_t);
}AUDIO_DrvTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __AUDIO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file camera.h
* @author MCD Application Team
* @brief This header file contains the common defines and functions prototypes
* for the camera driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __CAMERA_H
#define __CAMERA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup CAMERA
* @{
*/
/** @defgroup CAMERA_Exported_Types
* @{
*/
/** @defgroup CAMERA_Driver_structure Camera Driver structure
* @{
*/
typedef struct
{
void (*Init)(uint16_t, uint32_t);
uint16_t (*ReadID)(uint16_t);
void (*Config)(uint16_t, uint32_t, uint32_t, uint32_t);
}CAMERA_DrvTypeDef;
/**
* @}
*/
/**
* @}
*/
/** @defgroup CAMERA_Exported_Constants
* @{
*/
#define CAMERA_R160x120 0x00 /* QQVGA Resolution */
#define CAMERA_R320x240 0x01 /* QVGA Resolution */
#define CAMERA_R480x272 0x02 /* 480x272 Resolution */
#define CAMERA_R640x480 0x03 /* VGA Resolution */
#define CAMERA_CONTRAST_BRIGHTNESS 0x00 /* Camera contrast brightness features */
#define CAMERA_BLACK_WHITE 0x01 /* Camera black white feature */
#define CAMERA_COLOR_EFFECT 0x03 /* Camera color effect feature */
#define CAMERA_BRIGHTNESS_LEVEL0 0x00 /* Brightness level -2 */
#define CAMERA_BRIGHTNESS_LEVEL1 0x01 /* Brightness level -1 */
#define CAMERA_BRIGHTNESS_LEVEL2 0x02 /* Brightness level 0 */
#define CAMERA_BRIGHTNESS_LEVEL3 0x03 /* Brightness level +1 */
#define CAMERA_BRIGHTNESS_LEVEL4 0x04 /* Brightness level +2 */
#define CAMERA_CONTRAST_LEVEL0 0x05 /* Contrast level -2 */
#define CAMERA_CONTRAST_LEVEL1 0x06 /* Contrast level -1 */
#define CAMERA_CONTRAST_LEVEL2 0x07 /* Contrast level 0 */
#define CAMERA_CONTRAST_LEVEL3 0x08 /* Contrast level +1 */
#define CAMERA_CONTRAST_LEVEL4 0x09 /* Contrast level +2 */
#define CAMERA_BLACK_WHITE_BW 0x00 /* Black and white effect */
#define CAMERA_BLACK_WHITE_NEGATIVE 0x01 /* Negative effect */
#define CAMERA_BLACK_WHITE_BW_NEGATIVE 0x02 /* BW and Negative effect */
#define CAMERA_BLACK_WHITE_NORMAL 0x03 /* Normal effect */
#define CAMERA_COLOR_EFFECT_NONE 0x00 /* No effects */
#define CAMERA_COLOR_EFFECT_BLUE 0x01 /* Blue effect */
#define CAMERA_COLOR_EFFECT_GREEN 0x02 /* Green effect */
#define CAMERA_COLOR_EFFECT_RED 0x03 /* Red effect */
#define CAMERA_COLOR_EFFECT_ANTIQUE 0x04 /* Antique effect */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CAMERA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

104
USB-PD_Provider_1port/Drivers/BSP/Components/Common/dpredriver.h Normal file
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/**
******************************************************************************
* @file dpredriver.h
* @author MCD Application Team
* @brief This header file contains the functions prototypes for the
* DisplayPort Linear Redriver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __DPREDRIVER_H
#define __DPREDRIVER_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup DPREDRIVER
* @{
*/
/** @defgroup DPREDRIVER_Exported_Types
* @{
*/
/** @defgroup DPREDRIVER_Channel_Identifier Channel Identifier
* @{
*/
typedef enum {
CHANNEL_DP0 = 0,
CHANNEL_DP1,
CHANNEL_DP2,
CHANNEL_DP3,
CHANNEL_RX1,
CHANNEL_RX2,
CHANNEL_SSTX
} DPREDRIVER_ChannelId_t;
/**
* @}
*/
/** @defgroup DPREDRIVER_Driver_structure DisplayPort Linear Redriver Driver structure
* @{
*/
typedef struct
{
uint32_t (*Init)(uint16_t);
void (*DeInit)(uint16_t);
uint32_t (*PowerOn)(uint16_t);
uint32_t (*PowerOff)(uint16_t);
uint32_t (*SetEQGain)(uint16_t, DPREDRIVER_ChannelId_t, uint8_t);
uint32_t (*EnableChannel)(uint16_t, DPREDRIVER_ChannelId_t);
uint32_t (*DisableChannel)(uint16_t, DPREDRIVER_ChannelId_t);
}DPREDRIVER_Drv_t;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __DPREDRIVER_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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USB-PD_Provider_1port/Drivers/BSP/Components/Common/epd.h Normal file
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/**
******************************************************************************
* @file epd.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the
* EPD (E Paper Display) driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __EPD_H
#define __EPD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup Common
* @{
*/
/** @addtogroup EPD
* @{
*/
/** @defgroup EPD_Exported_Types
* @{
*/
/** @defgroup EPD_Driver_structure E Paper Display Driver structure
* @{
*/
typedef struct
{
void (*Init)(void);
void (*WritePixel)(uint8_t);
/* Optimized operation */
void (*SetDisplayWindow)(uint16_t, uint16_t, uint16_t, uint16_t);
void (*RefreshDisplay)(void);
void (*CloseChargePump)(void);
uint16_t (*GetEpdPixelWidth)(void);
uint16_t (*GetEpdPixelHeight)(void);
void (*DrawImage)(uint16_t, uint16_t, uint16_t, uint16_t, uint8_t*);
}
EPD_DrvTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* EPD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file gyro.h
* @author MCD Application Team
* @brief This header file contains the functions prototypes for the gyroscope driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GYRO_H
#define __GYRO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup GYRO
* @{
*/
/** @defgroup GYRO_Exported_Types
* @{
*/
/** @defgroup GYRO_Driver_structure Gyroscope Driver structure
* @{
*/
typedef struct
{
void (*Init)(uint16_t);
void (*DeInit)(void);
uint8_t (*ReadID)(void);
void (*Reset)(void);
void (*LowPower)(uint16_t);
void (*ConfigIT)(uint16_t);
void (*EnableIT)(uint8_t);
void (*DisableIT)(uint8_t);
uint8_t (*ITStatus)(uint16_t, uint16_t);
void (*ClearIT)(uint16_t, uint16_t);
void (*FilterConfig)(uint8_t);
void (*FilterCmd)(uint8_t);
void (*GetXYZ)(float *);
}GYRO_DrvTypeDef;
/**
* @}
*/
/** @defgroup GYRO_Config_structure Gyroscope Configuration structure
* @{
*/
typedef struct
{
uint8_t Power_Mode; /* Power-down/Sleep/Normal Mode */
uint8_t Output_DataRate; /* OUT data rate */
uint8_t Axes_Enable; /* Axes enable */
uint8_t Band_Width; /* Bandwidth selection */
uint8_t BlockData_Update; /* Block Data Update */
uint8_t Endianness; /* Endian Data selection */
uint8_t Full_Scale; /* Full Scale selection */
}GYRO_InitTypeDef;
/* GYRO High Pass Filter struct */
typedef struct
{
uint8_t HighPassFilter_Mode_Selection; /* Internal filter mode */
uint8_t HighPassFilter_CutOff_Frequency; /* High pass filter cut-off frequency */
}GYRO_FilterConfigTypeDef;
/*GYRO Interrupt struct */
typedef struct
{
uint8_t Latch_Request; /* Latch interrupt request into CLICK_SRC register */
uint8_t Interrupt_Axes; /* X, Y, Z Axes Interrupts */
uint8_t Interrupt_ActiveEdge; /* Interrupt Active edge */
}GYRO_InterruptConfigTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __GYRO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file hsensor.h
* @author MCD Application Team
* @brief This header file contains the functions prototypes for the
* Humidity Sensor driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HSENSOR_H
#define __HSENSOR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup HSENSOR
* @{
*/
/** @defgroup HSENSOR_Exported_Types
* @{
*/
/** @defgroup HSENSOR_Driver_structure Humidity Sensor Driver structure
* @{
*/
typedef struct
{
void (*Init)(uint16_t);
uint8_t (*ReadID)(uint16_t);
float (*ReadHumidity)(uint16_t);
}HSENSOR_DrvTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HSENSOR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file idd.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the IDD driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __IDD_H
#define __IDD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup IDD
* @{
*/
/** @defgroup IDD_Exported_Types IDD Exported Types
* @{
*/
/** @defgroup IDD_Config_structure IDD Configuration structure
* @{
*/
typedef struct
{
uint16_t AmpliGain; /*!< Specifies ampli gain value
*/
uint16_t VddMin; /*!< Specifies minimum MCU VDD can reach to protect MCU from reset
*/
uint16_t Shunt0Value; /*!< Specifies value of Shunt 0 if existing
*/
uint16_t Shunt1Value; /*!< Specifies value of Shunt 1 if existing
*/
uint16_t Shunt2Value; /*!< Specifies value of Shunt 2 if existing
*/
uint16_t Shunt3Value; /*!< Specifies value of Shunt 3 if existing
*/
uint16_t Shunt4Value; /*!< Specifies value of Shunt 4 if existing
*/
uint16_t Shunt0StabDelay; /*!< Specifies delay of Shunt 0 stabilization if existing
*/
uint16_t Shunt1StabDelay; /*!< Specifies delay of Shunt 1 stabilization if existing
*/
uint16_t Shunt2StabDelay; /*!< Specifies delay of Shunt 2 stabilization if existing
*/
uint16_t Shunt3StabDelay; /*!< Specifies delay of Shunt 3 stabilization if existing
*/
uint16_t Shunt4StabDelay; /*!< Specifies delay of Shunt 4 stabilization if existing
*/
uint8_t ShuntNbOnBoard; /*!< Specifies number of shunts that are present on board
This parameter can be a value of @ref IDD_shunt_number */
uint8_t ShuntNbUsed; /*!< Specifies number of shunts used for measurement
This parameter can be a value of @ref IDD_shunt_number */
uint8_t VrefMeasurement; /*!< Specifies if Vref is automatically measured before each Idd measurement
This parameter can be a value of @ref IDD_Vref_Measurement */
uint8_t Calibration; /*!< Specifies if calibration is done before each Idd measurement
*/
uint8_t PreDelayUnit; /*!< Specifies Pre delay unit
This parameter can be a value of @ref IDD_PreDelay */
uint8_t PreDelayValue; /*!< Specifies Pre delay value in selected unit
*/
uint8_t MeasureNb; /*!< Specifies number of Measure to be performed
This parameter can be a value between 1 and 256 */
uint8_t DeltaDelayUnit; /*!< Specifies Delta delay unit
This parameter can be a value of @ref IDD_DeltaDelay */
uint8_t DeltaDelayValue; /*!< Specifies Delta delay between 2 measures
value can be between 1 and 128 */
}IDD_ConfigTypeDef;
/**
* @}
*/
/** @defgroup IDD_Driver_structure IDD Driver structure
* @{
*/
typedef struct
{
void (*Init)(uint16_t);
void (*DeInit)(uint16_t);
uint16_t (*ReadID)(uint16_t);
void (*Reset)(uint16_t);
void (*LowPower)(uint16_t);
void (*WakeUp)(uint16_t);
void (*Start)(uint16_t);
void (*Config)(uint16_t,IDD_ConfigTypeDef);
void (*GetValue)(uint16_t, uint32_t *);
void (*EnableIT)(uint16_t);
void (*ClearIT)(uint16_t);
uint8_t (*GetITStatus)(uint16_t);
void (*DisableIT)(uint16_t);
void (*ErrorEnableIT)(uint16_t);
void (*ErrorClearIT)(uint16_t);
uint8_t (*ErrorGetITStatus)(uint16_t);
void (*ErrorDisableIT)(uint16_t);
uint8_t (*ErrorGetSrc)(uint16_t);
uint8_t (*ErrorGetCode)(uint16_t);
}IDD_DrvTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __IDD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file io.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the IO driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __IO_H
#define __IO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup IO
* @{
*/
/** @defgroup IO_Exported_Types
* @{
*/
/**
* @brief IO Bit SET and Bit RESET enumeration
*/
typedef enum
{
IO_PIN_RESET = 0,
IO_PIN_SET
}IO_PinState;
typedef enum
{
IO_MODE_INPUT = 0, /* input floating */
IO_MODE_OUTPUT, /* output Push Pull */
IO_MODE_IT_RISING_EDGE, /* float input - irq detect on rising edge */
IO_MODE_IT_FALLING_EDGE, /* float input - irq detect on falling edge */
IO_MODE_IT_LOW_LEVEL, /* float input - irq detect on low level */
IO_MODE_IT_HIGH_LEVEL, /* float input - irq detect on high level */
/* following modes only available on MFX*/
IO_MODE_ANALOG, /* analog mode */
IO_MODE_OFF, /* when pin isn't used*/
IO_MODE_INPUT_PU, /* input with internal pull up resistor */
IO_MODE_INPUT_PD, /* input with internal pull down resistor */
IO_MODE_OUTPUT_OD, /* Open Drain output without internal resistor */
IO_MODE_OUTPUT_OD_PU, /* Open Drain output with internal pullup resistor */
IO_MODE_OUTPUT_OD_PD, /* Open Drain output with internal pulldown resistor */
IO_MODE_OUTPUT_PP, /* PushPull output without internal resistor */
IO_MODE_OUTPUT_PP_PU, /* PushPull output with internal pullup resistor */
IO_MODE_OUTPUT_PP_PD, /* PushPull output with internal pulldown resistor */
IO_MODE_IT_RISING_EDGE_PU, /* push up resistor input - irq on rising edge */
IO_MODE_IT_RISING_EDGE_PD, /* push dw resistor input - irq on rising edge */
IO_MODE_IT_FALLING_EDGE_PU, /* push up resistor input - irq on falling edge */
IO_MODE_IT_FALLING_EDGE_PD, /* push dw resistor input - irq on falling edge */
IO_MODE_IT_LOW_LEVEL_PU, /* push up resistor input - irq detect on low level */
IO_MODE_IT_LOW_LEVEL_PD, /* push dw resistor input - irq detect on low level */
IO_MODE_IT_HIGH_LEVEL_PU, /* push up resistor input - irq detect on high level */
IO_MODE_IT_HIGH_LEVEL_PD, /* push dw resistor input - irq detect on high level */
}IO_ModeTypedef;
/** @defgroup IO_Driver_structure IO Driver structure
* @{
*/
typedef struct
{
void (*Init)(uint16_t);
uint16_t (*ReadID)(uint16_t);
void (*Reset)(uint16_t);
void (*Start)(uint16_t, uint32_t);
uint8_t (*Config)(uint16_t, uint32_t, IO_ModeTypedef);
void (*WritePin)(uint16_t, uint32_t, uint8_t);
uint32_t (*ReadPin)(uint16_t, uint32_t);
void (*EnableIT)(uint16_t);
void (*DisableIT)(uint16_t);
uint32_t (*ITStatus)(uint16_t, uint32_t);
void (*ClearIT)(uint16_t, uint32_t);
}IO_DrvTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __IO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file lcd.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the LCD driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __LCD_H
#define __LCD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup LCD
* @{
*/
/** @defgroup LCD_Exported_Types
* @{
*/
/** @defgroup LCD_Driver_structure LCD Driver structure
* @{
*/
typedef struct
{
void (*Init)(void);
uint16_t (*ReadID)(void);
void (*DisplayOn)(void);
void (*DisplayOff)(void);
void (*SetCursor)(uint16_t, uint16_t);
void (*WritePixel)(uint16_t, uint16_t, uint16_t);
uint16_t (*ReadPixel)(uint16_t, uint16_t);
/* Optimized operation */
void (*SetDisplayWindow)(uint16_t, uint16_t, uint16_t, uint16_t);
void (*DrawHLine)(uint16_t, uint16_t, uint16_t, uint16_t);
void (*DrawVLine)(uint16_t, uint16_t, uint16_t, uint16_t);
uint16_t (*GetLcdPixelWidth)(void);
uint16_t (*GetLcdPixelHeight)(void);
void (*DrawBitmap)(uint16_t, uint16_t, uint8_t*);
void (*DrawRGBImage)(uint16_t, uint16_t, uint16_t, uint16_t, uint8_t*);
}LCD_DrvTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file magneto.h
* @author MCD Application Team
* @brief This header file contains the functions prototypes for the MAGNETO driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAGNETO_H
#define __MAGNETO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup MAGNETO
* @{
*/
/** @defgroup MAGNETO_Exported_Types
* @{
*/
/** @defgroup MAGNETO_Config_structure Magnetometer Configuration structure
* @{
*/
typedef struct
{
uint8_t Register1;
uint8_t Register2;
uint8_t Register3;
uint8_t Register4;
uint8_t Register5;
}MAGNETO_InitTypeDef;
/**
* @}
*/
/** @defgroup MAGNETO_Driver_structure Magnetometer Driver structure
* @{
*/
typedef struct
{
void (*Init)(MAGNETO_InitTypeDef);
void (*DeInit)(void);
uint8_t (*ReadID)(void);
void (*Reset)(void);
void (*LowPower)(uint16_t);
void (*ConfigIT)(void);
void (*EnableIT)(uint8_t);
void (*DisableIT)(uint8_t);
uint8_t (*ITStatus)(uint16_t);
void (*ClearIT)(void);
void (*FilterConfig)(uint8_t);
void (*FilterCmd)(uint8_t);
void (*GetXYZ)(int16_t *);
}MAGNETO_DrvTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __MAGNETO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file psensor.h
* @author MCD Application Team
* @brief This header file contains the functions prototypes for the
* Pressure Sensor driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __PSENSOR_H
#define __PSENSOR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup PSENSOR
* @{
*/
/** @defgroup PSENSOR_Exported_Types
* @{
*/
/** @defgroup PSENSOR_Driver_structure Pressure Sensor Driver structure
* @{
*/
typedef struct
{
void (*Init)(uint16_t);
uint8_t (*ReadID)(uint16_t);
float (*ReadPressure)(uint16_t);
}PSENSOR_DrvTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __PSENSOR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file pwrmon.h
* @author MCD Application Team
* @brief This header file contains the functions prototypes for the
* Current/Power Monitor device driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __PWRMON_H
#define __PWRMON_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup PWRMON
* @{
*/
/** @defgroup PWRMON_Exported_Types
* @{
*/
/** @defgroup PWRMON_Operating_Mode_enum Power Monitor Operating Mode enums
* @{
*/
typedef enum {
OPERATING_MODE_TRIGGERED = 0,
OPERATING_MODE_CONTINUOUS,
OPERATING_MODE_NB
} PWRMON_OperatingMode_t;
/**
* @}
*/
/** @defgroup PWRMON_Conversion_Time_enum Power Monitor Conversion_Time enums
* @{
*/
typedef enum {
CONVERT_TIME_140 = 0,
CONVERT_TIME_204,
CONVERT_TIME_332,
CONVERT_TIME_588,
CONVERT_TIME_1100,
CONVERT_TIME_2116,
CONVERT_TIME_4156,
CONVERT_TIME_8244,
CONVERT_TIME_NB
} PWRMON_ConvertTime_t;
/**
* @}
*/
/** @defgroup PWRMON_Conversion_Time_enum Power Monitor Conversion_Time enums
* @{
*/
typedef enum {
AVERAGING_MODE_1 = 0,
AVERAGING_MODE_4,
AVERAGING_MODE_16,
AVERAGING_MODE_64,
AVERAGING_MODE_128,
AVERAGING_MODE_256,
AVERAGING_MODE_512,
AVERAGING_MODE_1024,
AVERAGING_MODE_NB
} PWRMON_AveragingMode_t;
/**
* @}
*/
/** @defgroup PWRMON_Device_Configuration_structure Power Monitor Device Configuration structure
* @{
*/
typedef struct
{
PWRMON_ConvertTime_t ShuntConvertTime;
PWRMON_ConvertTime_t BusConvertTime;
PWRMON_AveragingMode_t AveragingMode;
} PWRMON_Config_t;
/**
* @}
*/
/** @defgroup PWRMON_Alert_Polarity_enum Power Monitor Alert Polarity enums
* @{
*/
typedef enum {
ALERT_POLARITY_NORMAL = 0,
ALERT_POLARITY_INVERTED,
ALERT_POLARITY_NB
} PWRMON_AlertPolarity_t;
/**
* @}
*/
/** @defgroup PWRMON_Alert_Latch_Enable_enum Power Monitor Alert Latch Enable enums
* @{
*/
typedef enum {
ALERT_LATCH_DISABLE = 0,
ALERT_LATCH_ENABLE,
ALERT_LATCH_NB
} PWRMON_AlertLatchEnable_t;
/**
* @}
*/
/** @defgroup PWRMON_Alert_Function_enum Power Monitor Alert Function enums
* @{
*/
typedef enum {
ALERT_FUNCTION_NONE = 0,
ALERT_FUNCTION_SOL,
ALERT_FUNCTION_SUL,
ALERT_FUNCTION_BOL,
ALERT_FUNCTION_BUL,
ALERT_FUNCTION_POL,
ALERT_FUNCTION_NB,
} PWRMON_AlertFunction_t;
/**
* @}
*/
/** @defgroup PWRMON_Alert_Configuration_structure Power Monitor Alert Configuration structure
* @{
*/
typedef struct
{
PWRMON_AlertPolarity_t Polarity;
PWRMON_AlertLatchEnable_t LatchEnable;
} PWRMON_AlertPinConfig_t;
/**
* @}
*/
/** @defgroup PWRMON_Voltage_Input_enum Power Monitor Voltage Input enums
* @{
*/
typedef enum {
VOLTAGE_INPUT_SHUNT = 0,
VOLTAGE_INPUT_BUS,
VOLTAGE_INPUT_ALL,
VOLTAGE_INPUT_NB
} PWRMON_InputSignal_t;
/**
* @}
*/
/** @defgroup PWRMON_Flag_enum Power Monitor Flag enums
* @{
*/
typedef enum {
FLAG_ALERT_FUNCTION = 0,
FLAG_CONVERSION_READY,
FLAG_MATH_OVERFLOW,
FLAG_NB
} PWRMON_Flag_t;
/**
* @}
*/
/** @defgroup PWRMON_Driver_structure Power Monitor Driver structure
* @{
*/
typedef struct
{
void (*Init)(uint16_t, PWRMON_Config_t *);
void (*DeInit)(uint16_t);
uint16_t (*ReadId)(uint16_t);
void (*Reset)(uint16_t);
void (*SetCalibration)(uint16_t, uint16_t);
uint16_t (*GetCalibration)(uint16_t);
void (*SetAlertFunction)(uint16_t, PWRMON_AlertFunction_t);
PWRMON_AlertFunction_t (*GetAlertFunction)(uint16_t);
void (*AlertPinConfig)(uint16_t, PWRMON_AlertPinConfig_t *);
void (*SetVBusThreshold)(uint16_t, uint16_t);
uint16_t (*GetVBusThreshold)(uint16_t);
void (*SetVShuntThreshold)(uint16_t, int16_t);
int16_t (*GetVShuntThreshold)(uint16_t);
void (*SetPowerThreshold)(uint16_t, uint32_t);
uint32_t (*GetPowerThreshold)(uint16_t);
void (*AlertThresholdEnableIT)(uint16_t);
void (*AlertThresholdDisableIT)(uint16_t);
void (*ConversionReadyEnableIT)(uint16_t);
void (*ConversionReadyDisableIT)(uint16_t);
void (*StartConversion)(uint16_t, PWRMON_InputSignal_t, PWRMON_OperatingMode_t);
void (*StopConversion)(uint16_t);
uint16_t (*GetVBus)(uint16_t);
int16_t (*GetVShunt)(uint16_t);
uint16_t (*GetPower)(uint16_t);
int16_t (*GetCurrent)(uint16_t);
uint8_t (*GetFlag)(uint16_t, PWRMON_Flag_t);
} PWRMON_Drv_t;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __PWRMON_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file ts.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the Touch Screen driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TS_H
#define __TS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup TS
* @{
*/
/** @defgroup TS_Exported_Types
* @{
*/
/** @defgroup TS_Driver_structure Touch Sensor Driver structure
* @{
*/
typedef struct
{
void (*Init)(uint16_t);
uint16_t (*ReadID)(uint16_t);
void (*Reset)(uint16_t);
void (*Start)(uint16_t);
uint8_t (*DetectTouch)(uint16_t);
void (*GetXY)(uint16_t, uint16_t*, uint16_t*);
void (*EnableIT)(uint16_t);
void (*ClearIT)(uint16_t);
uint8_t (*GetITStatus)(uint16_t);
void (*DisableIT)(uint16_t);
}TS_DrvTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __TS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file tsensor.h
* @author MCD Application Team
* @brief This header file contains the functions prototypes for the
* Temperature Sensor driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TSENSOR_H
#define __TSENSOR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup TSENSOR
* @{
*/
/** @defgroup TSENSOR_Exported_Types
* @{
*/
/** @defgroup TSENSOR_Config_structure Temperature Sensor Configuration structure
* @{
*/
typedef struct
{
uint8_t AlertMode; /* Alert Mode Temperature out of range*/
uint8_t ConversionMode; /* Continuous/One Shot Mode */
uint8_t ConversionResolution; /* Temperature Resolution */
uint8_t ConversionRate; /* Number of measure per second */
int8_t TemperatureLimitHigh; /* High Temperature Limit Range */
int8_t TemperatureLimitLow; /* Low Temperature Limit Range */
}TSENSOR_InitTypeDef;
/**
* @}
*/
/** @defgroup TSENSOR_Driver_structure Temperature Sensor Driver structure
* @{
*/
typedef struct
{
void (*Init)(uint16_t, TSENSOR_InitTypeDef *);
uint8_t (*IsReady)(uint16_t, uint32_t);
uint8_t (*ReadStatus)(uint16_t);
float (*ReadTemp)(uint16_t);
}TSENSOR_DrvTypeDef;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __TSENSOR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file usbtypecswitch.h
* @author MCD Application Team
* @brief This header file contains the functions prototypes for the
* crossbar switch device for USB Type-C systems.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBTYPECSWITCH_H
#define __USBTYPECSWITCH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup TYPECSWITCH
* @{
*/
/** @defgroup TYPECSWITCH_Exported_Types
* @{
*/
typedef enum {
USB_NORMAL = 0,
USB_FLIPPED,
DFP_D_PIN_ASSIGNMENT_A_NORMAL,
DFP_D_PIN_ASSIGNMENT_A_FLIPPED,
DFP_D_PIN_ASSIGNMENT_B_NORMAL,
DFP_D_PIN_ASSIGNMENT_B_FLIPPED,
DFP_D_PIN_ASSIGNMENT_C_NORMAL,
DFP_D_PIN_ASSIGNMENT_C_FLIPPED,
DFP_D_PIN_ASSIGNMENT_D_NORMAL,
DFP_D_PIN_ASSIGNMENT_D_FLIPPED,
DFP_D_PIN_ASSIGNMENT_E_NORMAL,
DFP_D_PIN_ASSIGNMENT_E_FLIPPED,
DFP_D_PIN_ASSIGNMENT_F_NORMAL,
DFP_D_PIN_ASSIGNMENT_F_FLIPPED,
UFP_D_PIN_ASSIGNMENT_A_NORMAL,
UFP_D_PIN_ASSIGNMENT_A_FLIPPED,
UFP_D_PIN_ASSIGNMENT_B_NORMAL,
UFP_D_PIN_ASSIGNMENT_B_FLIPPED,
UFP_D_PIN_ASSIGNMENT_C_NORMAL,
UFP_D_PIN_ASSIGNMENT_C_FLIPPED,
UFP_D_PIN_ASSIGNMENT_D_NORMAL,
UFP_D_PIN_ASSIGNMENT_D_FLIPPED,
UFP_D_PIN_ASSIGNMENT_E_NORMAL,
UFP_D_PIN_ASSIGNMENT_E_FLIPPED,
UFP_D_PIN_ASSIGNMENT_F_NORMAL,
UFP_D_PIN_ASSIGNMENT_F_FLIPPED
} TYPECSWITCH_Mode_t;
/** @defgroup TYPECSWITCH_Driver_structure USB Type-C Crossbar Switch Driver structure
* @{
*/
typedef struct
{
uint32_t (*Init)(uint16_t);
void (*DeInit)(uint16_t);
uint32_t (*PowerOn)(uint16_t);
uint32_t (*PowerOff)(uint16_t);
uint32_t (*SetMode)(uint16_t, TYPECSWITCH_Mode_t);
uint32_t (*IsSupportedMode)(TYPECSWITCH_Mode_t);
} TYPECSWITCH_Drv_t;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBTYPECSWITCH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
<head>
<meta charset="utf-8" />
<meta name="generator" content="pandoc" />
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
<title>Release Notes for CBTL08GP053 Component Drivers</title>
<style type="text/css">
code{white-space: pre-wrap;}
span.smallcaps{font-variant: small-caps;}
span.underline{text-decoration: underline;}
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</style>
<link rel="stylesheet" href="../../../../_htmresc/mini-st.css" />
<!--[if lt IE 9]>
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<![endif]-->
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<body>
<div class="row">
<div class="col-sm-12 col-lg-4">
<div class="card fluid">
<div class="sectione dark">
<center>
<h1 id="release-notes-for-cbtl08gp053-component-drivers"><small>Release Notes for</small> <mark>CBTL08GP053 Component Drivers</mark></h1>
<p>Copyright © 2017 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img src="../../../../_htmresc/st_logo.png" alt="ST logo" /></a>
</center>
</div>
</div>
<h1 id="license">License</h1>
<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
<h1 id="purpose">Purpose</h1>
<p>This directory contains the CBTL08GP053 component drivers.</p>
</div>
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
<input type="checkbox" id="collapse-section12" checked aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.0.1 / 23-July-2020</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>Fix minor mispelled words</li>
<li>Update Release Notes format</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.0.0 / 16-November-2017</label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li>First official release of CBTL08GP053 Component driver</li>
</ul>
</div>
</div>
</div>
</div>
<footer class="sticky">
For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a>
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</html>

391
USB-PD_Provider_1port/Drivers/BSP/Components/cbtl08gp053/cbtl08gp053.c Normal file
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/**
******************************************************************************
* @file cbtl08gp053.c
* @author MCD Application Team
* @brief This file provides a set of functions needed to manage the CBTL08GP053
* (Crossbar switch device for USB Type-C systems).
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "cbtl08gp053.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @defgroup CBTL08GP053
* @brief This file provides a set of functions needed to drive the
* CBTL08GP053 Crossbar switch device for USB Type-C systems.
* @{
*/
/** @defgroup CBTL08GP053_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup CBTL08GP053_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup CBTL08GP053_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CBTL08GP053_Private_Variables
* @{
*/
#ifdef DBG_BSP_MUX
CBTL08GP053_TypeDef CBTL08GP053 =
{
.SYS_CTRL = 0x00,
.OP1_CTRL = 0x00,
.OP2_CTRL = 0x00,
.OP3_CTRL = 0x00,
.OP4_CTRL = 0x00,
.OP5_CTRL = 0x00,
.CROSS5_CTRL = 0x01,
.SW_CTRL = 0x00,
.SW_CTRL = 0x00,
.REVISION = 0xA0
};
#endif /* DBG_BSP_MUX */
/* Type-C Crosspoint Switch Driver structure initialization */
TYPECSWITCH_Drv_t cbtl08gp053_drv = {
cbtl08gp053_Init,
cbtl08gp053_DeInit,
cbtl08gp053_PowerOn,
cbtl08gp053_PowerOff,
cbtl08gp053_SetMode,
cbtl08gp053_IsSupportedMode
};
/* Supported USB Type-C pin assignments */
static const uint32_t cbtl08gp053_SupportedModes =
( 1 << USB_NORMAL |
1 << USB_FLIPPED |
1 << DFP_D_PIN_ASSIGNMENT_C_NORMAL |
1 << DFP_D_PIN_ASSIGNMENT_C_FLIPPED |
1 << DFP_D_PIN_ASSIGNMENT_D_NORMAL |
1 << DFP_D_PIN_ASSIGNMENT_D_FLIPPED |
1 << DFP_D_PIN_ASSIGNMENT_E_NORMAL |
1 << DFP_D_PIN_ASSIGNMENT_E_FLIPPED |
1 << DFP_D_PIN_ASSIGNMENT_F_NORMAL |
1 << DFP_D_PIN_ASSIGNMENT_F_FLIPPED |
1 << UFP_D_PIN_ASSIGNMENT_C_NORMAL |
1 << UFP_D_PIN_ASSIGNMENT_C_FLIPPED |
1 << UFP_D_PIN_ASSIGNMENT_D_NORMAL |
1 << UFP_D_PIN_ASSIGNMENT_D_FLIPPED |
1 << UFP_D_PIN_ASSIGNMENT_E_NORMAL |
1 << UFP_D_PIN_ASSIGNMENT_E_FLIPPED );
/**
* @}
*/
/** @defgroup CBTL08GP053_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup CBTL08GP053_Private_Functions
* @{
*/
/**
* @brief Initialize the CBTL08GP053 and configure the needed hardware resources.
* @param Address CBTL08GP053 address on communication Bus.
* @retval 0: successful, else failed
*/
uint32_t cbtl08gp053_Init(uint16_t Address)
{
uint32_t err_count = 0;
/* Low level init */
err_count += MUX_IO_Init();
/* Restore CBTL08GP053 registers reset values */
MUX_IO_Write(Address, CBTL08GP053_REG_SYS_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x01);
MUX_IO_Write(Address, CBTL08GP053_REG_SW_CTRL, 0x00);
return err_count;
}
/**
* @brief Release the hardware resources required to use the CBTL08GP053.
* @param Address CBTL08GP053 address on communication Bus.
* @retval none
*/
void cbtl08gp053_DeInit(uint16_t Address)
{
/* Restore CBTL08GP053 registers reset values */
MUX_IO_Write(Address, CBTL08GP053_REG_SYS_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x01);
MUX_IO_Write(Address, CBTL08GP053_REG_SW_CTRL, 0x00);
/* Low level de-init */
MUX_IO_DeInit();
}
/**
* @brief Power on the CBTL08GP053.
* @param Address CBTL08GP053 address on communication Bus.
* @retval 0: successful, else failed
*/
uint32_t cbtl08gp053_PowerOn(uint16_t Address)
{
uint32_t err_count = 0;
/* Set SYS_CTRL.SWTICH_EN bit */
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_SYS_CTRL, CBTL08GP053_REG_SYS_CTRL_SWITCH_EN);
return err_count;
}
/**
* @brief Power down the CBTL08GP053.
* @param Address CBTL08GP053 address on communication Bus.
* @retval 0: successful, else failed
*/
uint32_t cbtl08gp053_PowerOff(uint16_t Address)
{
uint32_t err_count = 0;
/* Clear SYS_CTRL.SWTICH_EN bit */
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_SYS_CTRL, 0x00);
return err_count;
}
/**
* @brief Configure the CBTL08GP053 according to the requested USB Type-C
* connector pin assignment.
* @param Address CBTL08GP053 address on communication Bus.
* @param Mode USB Type-C connector pin assignment
* @retval 0: success, else error
*/
uint32_t cbtl08gp053_SetMode(uint16_t Address, TYPECSWITCH_Mode_t Mode)
{
uint32_t err_count = 0;
uint8_t sw_ctrl = (CBTL08GP053_REG_SW_X5_SET |
CBTL08GP053_REG_SW_OP1_SET |
CBTL08GP053_REG_SW_OP2_SET |
CBTL08GP053_REG_SW_OP3_SET |
CBTL08GP053_REG_SW_OP4_SET |
CBTL08GP053_REG_SW_OP5_SET);
/* Transition to safe mode prior updating cross switch configuration */
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x00);
/* Configure cross switch */
switch(Mode)
{
case USB_NORMAL:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP1);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP4);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x00);
break;
case USB_FLIPPED:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP1);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP4);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x00);
break;
case DFP_D_PIN_ASSIGNMENT_C_NORMAL:
case DFP_D_PIN_ASSIGNMENT_E_NORMAL:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP2);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP3);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP5);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP6);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_PASS);
break;
case DFP_D_PIN_ASSIGNMENT_C_FLIPPED:
case DFP_D_PIN_ASSIGNMENT_E_FLIPPED:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP3);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP2);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP6);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP5);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_CROSS);
break;
case DFP_D_PIN_ASSIGNMENT_D_NORMAL:
case DFP_D_PIN_ASSIGNMENT_F_NORMAL:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP1);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP3);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP4);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP6);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_PASS);
break;
case DFP_D_PIN_ASSIGNMENT_D_FLIPPED:
case DFP_D_PIN_ASSIGNMENT_F_FLIPPED:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP3);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP1);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP6);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP4);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_CROSS);
break;
case UFP_D_PIN_ASSIGNMENT_C_NORMAL:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP2);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP3);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP5);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP6);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_CROSS);
break;
case UFP_D_PIN_ASSIGNMENT_C_FLIPPED:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP3);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP2);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP6);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP5);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_PASS);
break;
case UFP_D_PIN_ASSIGNMENT_D_NORMAL:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP1);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP3);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP4);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP6);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_CROSS);
break;
case UFP_D_PIN_ASSIGNMENT_D_FLIPPED:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP3);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP1);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP6);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP4);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_PASS);
break;
case UFP_D_PIN_ASSIGNMENT_E_NORMAL:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP2);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP3);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP5);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP6);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_CROSS);
break;
case UFP_D_PIN_ASSIGNMENT_E_FLIPPED:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, CBTL08GP053_REG_OP1_CTRL_EN_IP3);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, CBTL08GP053_REG_OP2_CTRL_EN_IP2);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, CBTL08GP053_REG_OP3_CTRL_EN_IP6);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, CBTL08GP053_REG_OP4_CTRL_EN_IP5);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, CBTL08GP053_REG_OP5_CTRL_EN_IP7);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, CBTL08GP053_REG_CROSS5_PASS);
break;
default:
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP1_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP2_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP3_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP4_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_OP5_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_CROSS5_CTRL, 0x00);
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_SW_CTRL, sw_ctrl);
break;
}
/* Enable cross switch configuration */
err_count += MUX_IO_Write(Address, CBTL08GP053_REG_SW_CTRL, sw_ctrl);
return err_count;
}
/**
* @brief Indicate whether the requested USB Type-C connector pin assignment
* is supported by the CBTL08GP053.
* @param Mode USB Type-C connector pin assignment
* @retval 0: success, else error
*/
uint32_t cbtl08gp053_IsSupportedMode(TYPECSWITCH_Mode_t Mode)
{
return (((1 << Mode) & cbtl08gp053_SupportedModes ) == 0) ? 0 : 1;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file cbtl08gp053.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the CBTL08GP053
* (Crossbar switch device for USB Type-C systems).
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __CBTL08GP053_H
#define __CBTL08GP053_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
#include "../Common/usbtypecswitch.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup CBTL08GP053
* @{
*/
#ifdef DBG_BSP_MUX
typedef struct
{
uint8_t RESERVED1; /*!< Address offset: 0x00 */
uint8_t SYS_CTRL; /*!< Address offset: 0x01 */
uint8_t OP1_CTRL; /*!< Address offset: 0x02 */
uint8_t OP2_CTRL; /*!< Address offset: 0x03 */
uint8_t OP3_CTRL; /*!< Address offset: 0x04 */
uint8_t OP4_CTRL; /*!< Address offset: 0x05 */
uint8_t OP5_CTRL; /*!< Address offset: 0x06 */
uint8_t CROSS5_CTRL; /*!< Address offset: 0x07 */
uint8_t SW_CTRL; /*!< Address offset: 0x08 */
uint8_t REVISION; /*!< Address offset: 0x09 */
} CBTL08GP053_TypeDef;
extern CBTL08GP053_TypeDef CBTL08GP053;
#endif /* DBG_BSP_MUX */
/** @defgroup CBTL08GP053_Exported_Constants
* @{
*/
/******************************* Register Map ********************************/
#define CBTL08GP053_REG_SYS_CTRL 0x01 /*!< */
#define CBTL08GP053_REG_OP1_CTRL 0x02 /*!< */
#define CBTL08GP053_REG_OP2_CTRL 0x03 /*!< */
#define CBTL08GP053_REG_OP3_CTRL 0x04 /*!< */
#define CBTL08GP053_REG_OP4_CTRL 0x05 /*!< */
#define CBTL08GP053_REG_OP5_CTRL 0x06 /*!< */
#define CBTL08GP053_REG_CROSS5_CTRL 0x07 /*!< */
#define CBTL08GP053_REG_SW_CTRL 0x08 /*!< */
#define CBTL08GP053_REG_REVISION 0x09 /*!< */
/********************* Bit definition for SYS_CTRL register *****************/
#define CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Pos (7U)
#define CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Msk (0x1U << CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Pos) /*!< 0x80*/
#define CBTL08GP053_REG_SYS_CTRL_SWITCH_EN CBTL08GP053_REG_SYS_CTRL_SWITCH_EN_Msk /*!< */
/********************* Bit definition for OP1_CTRL register *****************/
#define CBTL08GP053_REG_OP1_CTRL_EN_IP1_Pos (0U)
#define CBTL08GP053_REG_OP1_CTRL_EN_IP1_Msk (0x1U << CBTL08GP053_REG_OP1_CTRL_EN_IP1_Pos) /*!< 0x01 */
#define CBTL08GP053_REG_OP1_CTRL_EN_IP1 CBTL08GP053_REG_OP1_CTRL_EN_IP1_Msk /*!< */
#define CBTL08GP053_REG_OP1_CTRL_EN_IP2_Pos (1U)
#define CBTL08GP053_REG_OP1_CTRL_EN_IP2_Msk (0x1U << CBTL08GP053_REG_OP1_CTRL_EN_IP2_Pos) /*!< 0x02 */
#define CBTL08GP053_REG_OP1_CTRL_EN_IP2 CBTL08GP053_REG_OP1_CTRL_EN_IP2_Msk /*!< */
#define CBTL08GP053_REG_OP1_CTRL_EN_IP3_Pos (2U)
#define CBTL08GP053_REG_OP1_CTRL_EN_IP3_Msk (0x1U << CBTL08GP053_REG_OP1_CTRL_EN_IP3_Pos) /*!< 0x04 */
#define CBTL08GP053_REG_OP1_CTRL_EN_IP3 CBTL08GP053_REG_OP1_CTRL_EN_IP3_Msk /*!< */
/********************* Bit definition for OP2_CTRL register *****************/
#define CBTL08GP053_REG_OP2_CTRL_EN_IP1_Pos (0U)
#define CBTL08GP053_REG_OP2_CTRL_EN_IP1_Msk (0x1U << CBTL08GP053_REG_OP2_CTRL_EN_IP1_Pos) /*!< 0x01 */
#define CBTL08GP053_REG_OP2_CTRL_EN_IP1 CBTL08GP053_REG_OP2_CTRL_EN_IP1_Msk /*!< */
#define CBTL08GP053_REG_OP2_CTRL_EN_IP2_Pos (1U)
#define CBTL08GP053_REG_OP2_CTRL_EN_IP2_Msk (0x1U << CBTL08GP053_REG_OP2_CTRL_EN_IP2_Pos) /*!< 0x02 */
#define CBTL08GP053_REG_OP2_CTRL_EN_IP2 CBTL08GP053_REG_OP2_CTRL_EN_IP2_Msk /*!< */
#define CBTL08GP053_REG_OP2_CTRL_EN_IP3_Pos (2U)
#define CBTL08GP053_REG_OP2_CTRL_EN_IP3_Msk (0x1U << CBTL08GP053_REG_OP2_CTRL_EN_IP3_Pos) /*!< 0x04 */
#define CBTL08GP053_REG_OP2_CTRL_EN_IP3 CBTL08GP053_REG_OP2_CTRL_EN_IP3_Msk /*!< */
/********************* Bit definition for OP3_CTRL register *****************/
#define CBTL08GP053_REG_OP3_CTRL_EN_IP4_Pos (3U)
#define CBTL08GP053_REG_OP3_CTRL_EN_IP4_Msk (0x1U << CBTL08GP053_REG_OP3_CTRL_EN_IP4_Pos) /*!< 0x08 */
#define CBTL08GP053_REG_OP3_CTRL_EN_IP4 CBTL08GP053_REG_OP3_CTRL_EN_IP4_Msk /*!< */
#define CBTL08GP053_REG_OP3_CTRL_EN_IP5_Pos (4U)
#define CBTL08GP053_REG_OP3_CTRL_EN_IP5_Msk (0x1U << CBTL08GP053_REG_OP3_CTRL_EN_IP5_Pos) /*!< 0x10 */
#define CBTL08GP053_REG_OP3_CTRL_EN_IP5 CBTL08GP053_REG_OP3_CTRL_EN_IP5_Msk /*!< */
#define CBTL08GP053_REG_OP3_CTRL_EN_IP6_Pos (5U)
#define CBTL08GP053_REG_OP3_CTRL_EN_IP6_Msk (0x1U << CBTL08GP053_REG_OP3_CTRL_EN_IP6_Pos) /*!< 0x20 */
#define CBTL08GP053_REG_OP3_CTRL_EN_IP6 CBTL08GP053_REG_OP3_CTRL_EN_IP6_Msk /*!< */
/********************* Bit definition for OP4_CTRL register *****************/
#define CBTL08GP053_REG_OP4_CTRL_EN_IP4_Pos (3U)
#define CBTL08GP053_REG_OP4_CTRL_EN_IP4_Msk (0x1U << CBTL08GP053_REG_OP4_CTRL_EN_IP4_Pos) /*!< 0x08 */
#define CBTL08GP053_REG_OP4_CTRL_EN_IP4 CBTL08GP053_REG_OP4_CTRL_EN_IP4_Msk /*!< */
#define CBTL08GP053_REG_OP4_CTRL_EN_IP5_Pos (4U)
#define CBTL08GP053_REG_OP4_CTRL_EN_IP5_Msk (0x1U << CBTL08GP053_REG_OP4_CTRL_EN_IP5_Pos) /*!< 0x10 */
#define CBTL08GP053_REG_OP4_CTRL_EN_IP5 CBTL08GP053_REG_OP4_CTRL_EN_IP5_Msk /*!< */
#define CBTL08GP053_REG_OP4_CTRL_EN_IP6_Pos (5U)
#define CBTL08GP053_REG_OP4_CTRL_EN_IP6_Msk (0x1U << CBTL08GP053_REG_OP4_CTRL_EN_IP6_Pos) /*!< 0x20 */
#define CBTL08GP053_REG_OP4_CTRL_EN_IP6 CBTL08GP053_REG_OP4_CTRL_EN_IP6_Msk /*!< */
/********************* Bit definition for OP5_CTRL register *****************/
#define CBTL08GP053_REG_OP5_CTRL_EN_IP7_Pos (6U)
#define CBTL08GP053_REG_OP5_CTRL_EN_IP7_Msk (0x1U << CBTL08GP053_REG_OP5_CTRL_EN_IP7_Pos) /*!< 0x40 */
#define CBTL08GP053_REG_OP5_CTRL_EN_IP7 CBTL08GP053_REG_OP5_CTRL_EN_IP7_Msk /*!< */
#define CBTL08GP053_REG_OP5_CTRL_EN_IP8_Pos (7U)
#define CBTL08GP053_REG_OP5_CTRL_EN_IP8_Msk (0x1U << CBTL08GP053_REG_OP5_CTRL_EN_IP8_Pos) /*!< 0x80 */
#define CBTL08GP053_REG_OP5_CTRL_EN_IP8 CBTL08GP053_REG_OP5_CTRL_EN_IP8_Msk /*!< */
/****************** Bit definition for CROSS5_CTRL register *****************/
#define CBTL08GP053_REG_CROSS5_PASS_Pos (0U)
#define CBTL08GP053_REG_CROSS5_PASS_Msk (0x1U << CBTL08GP053_REG_CROSS5_PASS_Pos) /*!< 0x01 */
#define CBTL08GP053_REG_CROSS5_PASS CBTL08GP053_REG_CROSS5_PASS_Msk /*!< */
#define CBTL08GP053_REG_CROSS5_CROSS_Pos (1U)
#define CBTL08GP053_REG_CROSS5_CROSS_Msk (0x1U << CBTL08GP053_REG_CROSS5_CROSS_Pos) /*!< 0x02 */
#define CBTL08GP053_REG_CROSS5_CROSS CBTL08GP053_REG_CROSS5_CROSS_Msk /*!< */
/******************* Bit definition for SW_CTRL register ********************/
#define CBTL08GP053_REG_SW_OP1_SET_Pos (0U)
#define CBTL08GP053_REG_SW_OP1_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP1_SET_Pos) /*!< 0x01 */
#define CBTL08GP053_REG_SW_OP1_SET CBTL08GP053_REG_SW_OP1_SET_Msk /*!< */
#define CBTL08GP053_REG_SW_OP2_SET_Pos (1U)
#define CBTL08GP053_REG_SW_OP2_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP2_SET_Pos) /*!< 0x02 */
#define CBTL08GP053_REG_SW_OP2_SET CBTL08GP053_REG_SW_OP2_SET_Msk /*!< */
#define CBTL08GP053_REG_SW_OP3_SET_Pos (2U)
#define CBTL08GP053_REG_SW_OP3_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP3_SET_Pos) /*!< 0x04 */
#define CBTL08GP053_REG_SW_OP3_SET CBTL08GP053_REG_SW_OP3_SET_Msk /*!< */
#define CBTL08GP053_REG_SW_OP4_SET_Pos (3U)
#define CBTL08GP053_REG_SW_OP4_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP4_SET_Pos) /*!< 0x08 */
#define CBTL08GP053_REG_SW_OP4_SET CBTL08GP053_REG_SW_OP4_SET_Msk /*!< */
#define CBTL08GP053_REG_SW_OP5_SET_Pos (4U)
#define CBTL08GP053_REG_SW_OP5_SET_Msk (0x1U << CBTL08GP053_REG_SW_OP5_SET_Pos) /*!< 0x10 */
#define CBTL08GP053_REG_SW_OP5_SET CBTL08GP053_REG_SW_OP5_SET_Msk /*!< */
#define CBTL08GP053_REG_SW_X5_SET_Pos (5U)
#define CBTL08GP053_REG_SW_X5_SET_Msk (0x1U << CBTL08GP053_REG_SW_X5_SET_Pos) /*!< 0x20 */
#define CBTL08GP053_REG_SW_X5_SET CBTL08GP053_REG_SW_X5_SET_Msk /*!< */
/******************** Bit definition for REVISION register ******************/
#define CBTL08GP053_REVISION_REV_ID_Pos (0U)
#define CBTL08GP053_REVISION_REV_ID_Msk (0xFFU << CBTL08GP053_REVISION_REV_ID_Pos) /*!< 0xFF */
#define CBTL08GP053_REVISION_REV_ID CBTL08GP053_REVISION_REV_ID_Msk /*!< */
/** @defgroup CBTL08GP053_DisplayPort_Alternate_Mode
* @{
*/
#define CBTL08GP053_DP_ALTMODE_DFP_D_C_E_NORMAL 0x00U
#define CBTL08GP053_DP_ALTMODE_DFP_D_C_E_FLIPPED 0x01U
#define CBTL08GP053_DP_ALTMODE_DFP_D_D_F_NORMAL 0x02U
#define CBTL08GP053_DP_ALTMODE_DFP_D_D_F_FLIPPED 0x03U
#define CBTL08GP053_DP_ALTMODE_UFP_D_C_NORMAL 0x04U
#define CBTL08GP053_DP_ALTMODE_UFP_D_C_FLIPPED 0x05U
#define CBTL08GP053_DP_ALTMODE_UFP_D_D_NORMAL 0x06U
#define CBTL08GP053_DP_ALTMODE_UFP_D_D_FLIPPED 0x07U
#define CBTL08GP053_DP_ALTMODE_UFP_D_E_NORMAL 0x08U
#define CBTL08GP053_DP_ALTMODE_UFP_D_E_FLIPPED 0x09U
/**
* @}
*/
/** @defgroup CBTL08GP053_DisplayPort_Standby_Mode
* @{
*/
#define CBTL08GP053_DP_STANDBYMODE_SAFE 0x00U
#define CBTL08GP053_DP_STANDBYMODE_USB3_NORMAL 0x01U
#define CBTL08GP053_DP_STANDBYMODE_USB3_FLIPPED 0x02U
/**
* @}
*/
/**
* @}
*/
#if defined(CBTL08GP053_DEBUG)
/** @defgroup CBTL08GP053_Exported_Structure CBTL08GP053 Exported Structure
* @{
*/
typedef union {
uint8_t Register;
struct {
uint8_t RESERVED :7;
uint8_t SWITCH_EN :1;
};
} CBTL08GP053_SysCtrlTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t IP1 :1;
uint8_t IP2 :1;
uint8_t IP3 :1;
uint8_t RESERVED :5;
};
} CBTL08GP053_Op1CtrlTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t IP1 :1;
uint8_t IP2 :1;
uint8_t IP3 :1;
uint8_t RESERVED :5;
};
} CBTL08GP053_Op2CtrlTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t RESERVED1 :3;
uint8_t IP4 :1;
uint8_t IP5 :1;
uint8_t IP6 :1;
uint8_t RESERVED2 :2;
};
} CBTL08GP053_Op3CtrlTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t RESERVED1 :3;
uint8_t IP4 :1;
uint8_t IP5 :1;
uint8_t IP6 :1;
uint8_t RESERVED2 :2;
};
} CBTL08GP053_Op4CtrlTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t RESERVED :6;
uint8_t IP7 :1;
uint8_t IP8 :1;
};
} CBTL08GP053_Op5CtrlTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t PASS :1;
uint8_t CROSS :1;
uint8_t RESERVED :6;
};
} CBTL08GP053_Cross5CtrlTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t OP1_SET :1;
uint8_t OP2_SET :1;
uint8_t OP3_SET :1;
uint8_t OP4_SET :1;
uint8_t OP5_SET :1;
uint8_t X5_SET :1;
uint8_t RESERVED :2;
};
} CBTL08GP053_SwCtrlTypeDef;
typedef struct
{
CBTL08GP053_SysCtrlTypeDef SysCtrl; /*!< SYS_CTRL register (0x01) */
CBTL08GP053_Op1CtrlTypeDef Op1Ctrl; /*!< OP1_CTRL Registers (0x02) */
CBTL08GP053_Op2CtrlTypeDef Op2Ctrl; /*!< OP2_CTRL Registers (0x03) */
CBTL08GP053_Op3CtrlTypeDef Op3Ctrl; /*!< OP3_CTRL Registers (0x04) */
CBTL08GP053_Op4CtrlTypeDef Op4Ctrl; /*!< OP4_CTRL Registers (0x05) */
CBTL08GP053_Op5CtrlTypeDef Op5Ctrl; /*!< OP5_CTRL Registers (0x06) */
CBTL08GP053_Cross5CtrlTypeDef Cross5Ctrl; /*!< CROSS5_CTRL Registers (0x07) */
CBTL08GP053_SwCtrlTypeDef SwCtrl; /*!< SW_CTRL Registers (0x08) */
uint8_t Revision; /*!< REVISION Registers (0x09) */
} CBTL08GP053_RegistersTypeDef;
/**
* @}
*/
#endif /* CBTL08GP053_DEBUG */
/** @defgroup CBTL08GP053_Exported_Functions
* @{
*/
/* USB Type-C Crosspoint Switch management functions */
uint32_t cbtl08gp053_Init(uint16_t Address);
void cbtl08gp053_DeInit(uint16_t Address);
uint32_t cbtl08gp053_PowerOn(uint16_t Address);
uint32_t cbtl08gp053_PowerOff(uint16_t Address);
uint32_t cbtl08gp053_SetMode(uint16_t Address, TYPECSWITCH_Mode_t Mode);
uint32_t cbtl08gp053_IsSupportedMode(TYPECSWITCH_Mode_t Mode);
/* MUX IO functions */
uint8_t MUX_IO_Init(void);
void MUX_IO_DeInit(void);
uint8_t MUX_IO_Write(uint16_t Addr, uint16_t Reg, uint8_t Data);
uint8_t MUX_IO_Read(uint16_t Addr, uint16_t Reg, uint8_t *pData);
uint32_t MUX_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials);
/**
* @}
*/
/** @defgroup CBTL08GP053_Exported_Variables
* @{
*/
/* Type-C Crosspoint Switch Driver */
extern TYPECSWITCH_Drv_t cbtl08gp053_drv;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CBTL08GP053_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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<div style="width: 1034px;" class="Section1"><span style="font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;"></span><small><a href="../../../../Release_Notes.html">Back to Release page</a></small>
<div id="header">
<h1 style="margin-bottom: 18pt; text-align: center;" align="center">Release
Notes for HX8347D Component Drivers</h1>
<p style="text-align: center;">Copyright 2014
STMicroelectronics</p>
<p style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;"><img style="border: 0px solid ; width: 112px; height: 83px;" alt="" id="_x0000_i1026" src="../../../../_htmresc/st_logo.png"></span></p>
</div>
<div id="license" class="topic1">
<h2>License</h2>
This software component is licensed by ST under BSD 3-Clause
license, the "License"; You may not use this component except in
compliance with
the License. You may obtain a copy of the License at:
<p style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank">https://opensource.org/licenses/BSD-3-Clause</a></p>
</div>
<br>
<div id="release_container" class="topic1">
<div class="topic2" id="identification">
<h3 style="width: 229px;">V1.1.2 / 11-October-2018</h3>
</div>
<div class="topic3" id="changes">
<h4><b><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span><u><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b><o:p style="font-family: Helvetica,Arial,sans-serif;"></o:p></h4>
<span style="font-size: 12pt; font-family: Helvetica,Arial,sans-serif;"></span><span style="font-size: 11pt; color: rgb(0, 32, 96); font-family: Helvetica,Arial,sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: Helvetica,Arial,sans-serif;"></span><span style="font-size: 10pt; font-family: Verdana;">Fix&nbsp;</span><small><span style="font-family: Verdana;" id="summary_container"><span id="short_desc_nonedit_display">HardFault issue in
hx8347d_DrawBitmap()</span></span></small><span style="font-size: 10pt; font-family: Helvetica,Arial,sans-serif;"></span>
<span style="font-size: 10pt; font-family: Helvetica,Arial,sans-serif;"></span></div>
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</div>
<div style="margin-left: 40px;"><button id="filter_hist" onclick="toggle_history()">Show
History</button><br>
</div>
<div id="history" class="topic1" hidden="">
<h2>Update History</h2>
<b><u><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></u></b><br>
<h3 style="width: 229px;">V1.1.1 / 24-November-2014</h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<span style="font-size: 10pt; font-family: Verdana;"></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
<ul style="list-style-type: square;">
<li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-family: Verdana; font-size: 10pt;">hx8347d.h:
change </span><span style="font-family: Verdana; font-size: 10pt;">"\" by</span><span style="font-family: Verdana; font-size: 10pt;"> "/"&nbsp;</span><span style="font-family: Verdana; font-size: 10pt;"></span><span style="font-family: Verdana; font-size: 10pt;">in the</span><span style="font-family: Verdana; font-size: 10pt;"> include path
to fix compilation issue with Linux</span></li>
</ul>
<h3 style="width: 229px;">V1.1.0 / 11-July-2014</h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<span style="font-size: 10pt; font-family: Verdana;"></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
<ul style="list-style-type: square;">
<li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-family: Verdana; font-size: 10pt;">Harmonize all
LCD controllers Link usage (change LCD_IO_WriteData() to
LCD_IO_WriteMultipleData())</span><span style="font-family: Verdana; font-size: 10pt;"></span></li>
</ul>
<h3 style="width: 229px;">V1.0.0 / 06-May-2014</h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<span style="font-size: 10pt; font-family: Verdana;"></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
<ul style="list-style-type: square;">
<li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">First
official release of<span>&nbsp;</span></span><span style="font-size: 10pt; font-family: Verdana;">HX8347D LCD
Component</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span>&nbsp;</span>driver</span></li>
</ul>
<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><br>
</div>
<div id="product_doc" class="topic1">
<hr>
<p style="text-align: center;">For complete
documentation on STM32 Microcontrollers<span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="color: black;"></span></span>,
visit:&nbsp;<a href="http://www.st.com/STM32" target="_blank">www.st.com/STM32</a></p>
<br>
</div>
</div>
</body></html>

485
USB-PD_Provider_1port/Drivers/BSP/Components/hx8347d/hx8347d.c Normal file
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/**
******************************************************************************
* @file hx8347d.c
* @author MCD Application Team
* @brief This file includes the LCD driver for HX8347D LCD.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "hx8347d.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup HX8347D
* @brief This file provides a set of functions needed to drive the
* HX8347D LCD.
* @{
*/
/** @defgroup HX8347D_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup HX8347D_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup HX8347D_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup HX8347D_Private_Variables
* @{
*/
LCD_DrvTypeDef hx8347d_drv =
{
hx8347d_Init,
hx8347d_ReadID,
hx8347d_DisplayOn,
hx8347d_DisplayOff,
hx8347d_SetCursor,
hx8347d_WritePixel,
hx8347d_ReadPixel,
hx8347d_SetDisplayWindow,
hx8347d_DrawHLine,
hx8347d_DrawVLine,
hx8347d_GetLcdPixelWidth,
hx8347d_GetLcdPixelHeight,
hx8347d_DrawBitmap,
};
static uint8_t Is_hx8347d_Initialized = 0;
static uint16_t ArrayRGB[320] = {0};
/**
* @}
*/
/** @defgroup HX8347D_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup HX8347D_Private_Functions
* @{
*/
/**
* @brief Initialise the HX8347D LCD Component.
* @param None
* @retval None
*/
void hx8347d_Init(void)
{
if(Is_hx8347d_Initialized == 0)
{
Is_hx8347d_Initialized = 1;
/* Initialise HX8347D low level bus layer --------------------------------*/
LCD_IO_Init();
/* Driving ability setting */
hx8347d_WriteReg(LCD_REG_234, 0x00);
hx8347d_WriteReg(LCD_REG_235, 0x20);
hx8347d_WriteReg(LCD_REG_236, 0x0C);
hx8347d_WriteReg(LCD_REG_237, 0xC4);
hx8347d_WriteReg(LCD_REG_232, 0x40);
hx8347d_WriteReg(LCD_REG_233, 0x38);
hx8347d_WriteReg(LCD_REG_241, 0x01);
hx8347d_WriteReg(LCD_REG_242, 0x10);
hx8347d_WriteReg(LCD_REG_39, 0xA3);
/* Adjust the Gamma Curve */
hx8347d_WriteReg(LCD_REG_64, 0x01);
hx8347d_WriteReg(LCD_REG_65, 0x00);
hx8347d_WriteReg(LCD_REG_66, 0x00);
hx8347d_WriteReg(LCD_REG_67, 0x10);
hx8347d_WriteReg(LCD_REG_68, 0x0E);
hx8347d_WriteReg(LCD_REG_69, 0x24);
hx8347d_WriteReg(LCD_REG_70, 0x04);
hx8347d_WriteReg(LCD_REG_71, 0x50);
hx8347d_WriteReg(LCD_REG_72, 0x02);
hx8347d_WriteReg(LCD_REG_73, 0x13);
hx8347d_WriteReg(LCD_REG_74, 0x19);
hx8347d_WriteReg(LCD_REG_75, 0x19);
hx8347d_WriteReg(LCD_REG_76, 0x16);
hx8347d_WriteReg(LCD_REG_80, 0x1B);
hx8347d_WriteReg(LCD_REG_81, 0x31);
hx8347d_WriteReg(LCD_REG_82, 0x2F);
hx8347d_WriteReg(LCD_REG_83, 0x3F);
hx8347d_WriteReg(LCD_REG_84, 0x3F);
hx8347d_WriteReg(LCD_REG_85, 0x3E);
hx8347d_WriteReg(LCD_REG_86, 0x2F);
hx8347d_WriteReg(LCD_REG_87, 0x7B);
hx8347d_WriteReg(LCD_REG_88, 0x09);
hx8347d_WriteReg(LCD_REG_89, 0x06);
hx8347d_WriteReg(LCD_REG_90, 0x06);
hx8347d_WriteReg(LCD_REG_91, 0x0C);
hx8347d_WriteReg(LCD_REG_92, 0x1D);
hx8347d_WriteReg(LCD_REG_93, 0xCC);
/* Power voltage setting */
hx8347d_WriteReg(LCD_REG_27, 0x1B);
hx8347d_WriteReg(LCD_REG_26, 0x01);
hx8347d_WriteReg(LCD_REG_36, 0x2F);
hx8347d_WriteReg(LCD_REG_37, 0x57);
/*****VCOM offset ****/
hx8347d_WriteReg(LCD_REG_35, 0x86);
/* Power on setting up flow */
hx8347d_WriteReg(LCD_REG_24, 0x36); /* Display frame rate = 70Hz RADJ = '0110' */
hx8347d_WriteReg(LCD_REG_25, 0x01); /* OSC_EN = 1 */
hx8347d_WriteReg(LCD_REG_28, 0x06); /* AP[2:0] = 111 */
hx8347d_WriteReg(LCD_REG_29, 0x06); /* AP[2:0] = 111 */
hx8347d_WriteReg(LCD_REG_31,0x90); /* GAS=1, VOMG=00, PON=1, DK=0, XDK=0, DVDH_TRI=0, STB=0*/
hx8347d_WriteReg(LCD_REG_39, 1); /* REF = 1 */
LCD_Delay(10);
/* 262k/65k color selection */
hx8347d_WriteReg(LCD_REG_23, 0x05); /* default 0x06 262k color, 0x05 65k color */
/* SET PANEL */
hx8347d_WriteReg(LCD_REG_54, 0x09); /* SS_PANEL = 1, GS_PANEL = 0,REV_PANEL = 0, BGR_PANEL = 1 */
/* Display ON flow */
hx8347d_WriteReg(LCD_REG_40, 0x38); /* GON=1, DTE=1, D=10 */
LCD_Delay(60);
hx8347d_WriteReg(LCD_REG_40, 0x3C); /* GON=1, DTE=1, D=11 */
/* Set GRAM Area - Partial Display Control */
hx8347d_WriteReg(LCD_REG_1, 0x00); /* DP_STB = 0, DP_STB_S = 0, SCROLL = 0, */
hx8347d_WriteReg(LCD_REG_2, 0x00); /* Column address start 2 */
hx8347d_WriteReg(LCD_REG_3, 0x00); /* Column address start 1 */
hx8347d_WriteReg(LCD_REG_4, 0x01); /* Column address end 2 */
hx8347d_WriteReg(LCD_REG_5, 0x3F); /* Column address end 1 */
hx8347d_WriteReg(LCD_REG_6, 0x00); /* Row address start 2 */
hx8347d_WriteReg(LCD_REG_7, 0x00); /* Row address start 2 */
hx8347d_WriteReg(LCD_REG_8, 0x00); /* Row address end 2 */
hx8347d_WriteReg(LCD_REG_9, 0xEF); /* Row address end 1 */
hx8347d_WriteReg(LCD_REG_22, 0xE0); /* Memory access control: MY = 1, MX = 0, MV = 1, ML = 0 */
}
/* Set the Cursor */
hx8347d_SetCursor(0, 0);
/* Prepare to write GRAM */
LCD_IO_WriteReg(LCD_REG_34);
}
/**
* @brief Enables the Display.
* @param None
* @retval None
*/
void hx8347d_DisplayOn(void)
{
/* Power On sequence ---------------------------------------------------------*/
hx8347d_WriteReg(LCD_REG_24, 0x36); /* Display frame rate = 70Hz RADJ = '0110' */
hx8347d_WriteReg(LCD_REG_25, 0x01); /* OSC_EN = 1 */
hx8347d_WriteReg(LCD_REG_28, 0x06); /* AP[2:0] = 111 */
hx8347d_WriteReg(LCD_REG_31,0x90); /* GAS=1, VOMG=00, PON=1, DK=0, XDK=0, DVDH_TRI=0, STB=0*/
LCD_Delay(10);
/* 262k/65k color selection */
hx8347d_WriteReg(LCD_REG_23, 0x05); /* default 0x06 262k color, 0x05 65k color */
/* SET PANEL */
hx8347d_WriteReg(LCD_REG_54, 0x09); /* SS_PANEL = 1, GS_PANEL = 0,REV_PANEL = 0, BGR_PANEL = 1 */
/* Display On */
hx8347d_WriteReg(LCD_REG_40, 0x38);
LCD_Delay(60);
hx8347d_WriteReg(LCD_REG_40, 0x3C);
}
/**
* @brief Disables the Display.
* @param None
* @retval None
*/
void hx8347d_DisplayOff(void)
{
/* Power Off sequence ---------------------------------------------------------*/
hx8347d_WriteReg(LCD_REG_23, 0x0000); /* default 0x06 262k color, 0x05 65k color */
hx8347d_WriteReg(LCD_REG_24, 0x0000); /* Display frame rate = 70Hz RADJ = '0110' */
hx8347d_WriteReg(LCD_REG_25, 0x0000); /* OSC_EN = 1 */
hx8347d_WriteReg(LCD_REG_28, 0x0000); /* AP[2:0] = 111 */
hx8347d_WriteReg(LCD_REG_31, 0x0000); /* GAS=1, VOMG=00, PON=1, DK=0, XDK=0, DVDH_TRI=0, STB=0*/
hx8347d_WriteReg(LCD_REG_54, 0x0000); /* SS_PANEL = 1, GS_PANEL = 0,REV_PANEL = 0, BGR_PANEL = 1 */
/* Display Off */
hx8347d_WriteReg(LCD_REG_40, 0x38);
LCD_Delay(60);
hx8347d_WriteReg(LCD_REG_40, 0x04);
}
/**
* @brief Get the LCD pixel Width.
* @param None
* @retval The Lcd Pixel Width
*/
uint16_t hx8347d_GetLcdPixelWidth(void)
{
return (uint16_t)HX8347D_LCD_PIXEL_WIDTH;
}
/**
* @brief Get the LCD pixel Height.
* @param None
* @retval The Lcd Pixel Height
*/
uint16_t hx8347d_GetLcdPixelHeight(void)
{
return (uint16_t)HX8347D_LCD_PIXEL_HEIGHT;
}
/**
* @brief Get the HX8347D ID.
* @param None
* @retval The HX8347D ID
*/
uint16_t hx8347d_ReadID(void)
{
if(Is_hx8347d_Initialized == 0)
{
hx8347d_Init();
Is_hx8347d_Initialized = 1;
}
return (hx8347d_ReadReg(0x00));
}
/**
* @brief Set Cursor position.
* @param Xpos: specifies the X position.
* @param Ypos: specifies the Y position.
* @retval None
*/
void hx8347d_SetCursor(uint16_t Xpos, uint16_t Ypos)
{
hx8347d_WriteReg(LCD_REG_6, 0x00);
hx8347d_WriteReg(LCD_REG_7, Xpos);
hx8347d_WriteReg(LCD_REG_2, Ypos >> 8);
hx8347d_WriteReg(LCD_REG_3, Ypos & 0xFF);
}
/**
* @brief Write pixel.
* @param Xpos: specifies the X position.
* @param Ypos: specifies the Y position.
* @param RGBCode: the RGB pixel color
* @retval None
*/
void hx8347d_WritePixel(uint16_t Xpos, uint16_t Ypos, uint16_t RGBCode)
{
/* Set Cursor */
hx8347d_SetCursor(Xpos, Ypos);
/* Prepare to write GRAM */
LCD_IO_WriteReg(LCD_REG_34);
/* Write 16-bit GRAM Reg */
LCD_IO_WriteMultipleData((uint8_t*)&RGBCode, 2);
}
/**
* @brief Read pixel.
* @param None
* @retval the RGB pixel color
*/
uint16_t hx8347d_ReadPixel(uint16_t Xpos, uint16_t Ypos)
{
/* Set Cursor */
hx8347d_SetCursor(Xpos, Ypos);
/* Dummy read */
LCD_IO_ReadData(LCD_REG_34);
/* Read 16-bit Reg */
return (LCD_IO_ReadData(LCD_REG_34));
}
/**
* @brief Writes to the selected LCD register.
* @param LCDReg: address of the selected register.
* @param LCDRegValue: value to write to the selected register.
* @retval None
*/
void hx8347d_WriteReg(uint8_t LCDReg, uint16_t LCDRegValue)
{
LCD_IO_WriteReg(LCDReg);
/* Write 16-bit GRAM Reg */
LCD_IO_WriteMultipleData((uint8_t*)&LCDRegValue, 2);
}
/**
* @brief Reads the selected LCD Register.
* @param LCDReg: address of the selected register.
* @retval LCD Register Value.
*/
uint16_t hx8347d_ReadReg(uint8_t LCDReg)
{
/* Read 16-bit Reg */
return (LCD_IO_ReadData(LCDReg));
}
/**
* @brief Sets a display window
* @param Xpos: specifies the X bottom left position.
* @param Ypos: specifies the Y bottom left position.
* @param Height: display window height.
* @param Width: display window width.
* @retval None
*/
void hx8347d_SetDisplayWindow(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
{
/* Horizontal GRAM Start Address */
hx8347d_WriteReg(LCD_REG_6, (Xpos) >> 8); /* SP */
hx8347d_WriteReg(LCD_REG_7, (Xpos) & 0xFF); /* SP */
/* Horizontal GRAM End Address */
hx8347d_WriteReg(LCD_REG_8, (Xpos + Height - 1) >> 8); /* EP */
hx8347d_WriteReg(LCD_REG_9, (Xpos + Height - 1) & 0xFF); /* EP */
/* Vertical GRAM Start Address */
hx8347d_WriteReg(LCD_REG_2, (Ypos) >> 8); /* SC */
hx8347d_WriteReg(LCD_REG_3, (Ypos) & 0xFF); /* SC */
/* Vertical GRAM End Address */
hx8347d_WriteReg(LCD_REG_4, (Ypos + Width - 1) >> 8); /* EC */
hx8347d_WriteReg(LCD_REG_5, (Ypos + Width - 1) & 0xFF); /* EC */
}
/**
* @brief Draw vertical line.
* @param RGBCode: Specifies the RGB color
* @param Xpos: specifies the X position.
* @param Ypos: specifies the Y position.
* @param Length: specifies the Line length.
* @retval None
*/
void hx8347d_DrawHLine(uint16_t RGBCode, uint16_t Xpos, uint16_t Ypos, uint16_t Length)
{
uint32_t i = 0;
/* Set Cursor */
hx8347d_SetCursor(Xpos, Ypos);
/* Prepare to write GRAM */
LCD_IO_WriteReg(LCD_REG_34);
/* Sent a complete line */
for(i = 0; i < Length; i++)
{
ArrayRGB[i] = RGBCode;
}
LCD_IO_WriteMultipleData((uint8_t*)&ArrayRGB[0], Length * 2);
}
/**
* @brief Draw vertical line.
* @param RGBCode: Specifies the RGB color
* @param Xpos: specifies the X position.
* @param Ypos: specifies the Y position.
* @param Length: specifies the Line length.
* @retval None
*/
void hx8347d_DrawVLine(uint16_t RGBCode, uint16_t Xpos, uint16_t Ypos, uint16_t Length)
{
uint16_t counter = 0;
/* Set Cursor */
hx8347d_SetCursor(Xpos, Ypos);
/* Prepare to write GRAM */
LCD_IO_WriteReg(LCD_REG_34);
/* Fill a complete vertical line */
for(counter = 0; counter < Length; counter++)
{
ArrayRGB[counter] = RGBCode;
}
/* Write 16-bit GRAM Reg */
LCD_IO_WriteMultipleData((uint8_t*)&ArrayRGB[0], Length * 2);
}
/**
* @brief Displays a bitmap picture loaded in the internal Flash.
* @param BmpAddress: Bmp picture address in the internal Flash.
* @retval None
*/
void hx8347d_DrawBitmap(uint16_t Xpos, uint16_t Ypos, uint8_t *pbmp)
{
uint32_t index = 0, size = 0;
/* Read bitmap size */
size = pbmp[2] + (pbmp[3] << 8) + (pbmp[4] << 16) + (pbmp[5] << 24);
/* Get bitmap data address offset */
index = pbmp[10] + (pbmp[11] << 8) + (pbmp[12] << 16) + (pbmp[13] << 24);
size = (size - index)/2;
pbmp += index;
/* Set GRAM write direction and BGR = 0 */
/* Memory access control: MY = 1, MX = 0, MV = 1, ML = 0 */
hx8347d_WriteReg(LCD_REG_22, 0xA0);
/* Set Cursor */
hx8347d_SetCursor(Xpos, Ypos);
/* Prepare to write GRAM */
LCD_IO_WriteReg(LCD_REG_34);
LCD_IO_WriteMultipleData((uint8_t*)pbmp, size*2);
/* Set GRAM write direction and BGR = 0 */
/* Memory access control: MY = 1, MX = 1, MV = 1, ML = 0 */
hx8347d_WriteReg(LCD_REG_22, 0xE0);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file hx8347d.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the hx8347d.c
* driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef HX8347D_H
#define HX8347D_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "../Common/lcd.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup HX8347D
* @{
*/
/** @defgroup HX8347D_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup HX8347D_Exported_Constants
* @{
*/
/**
* @brief HX8347D ID
*/
#define HX8347D_ID 0x0047
/**
* @brief HX8347D Size
*/
#define HX8347D_LCD_PIXEL_WIDTH ((uint16_t)320)
#define HX8347D_LCD_PIXEL_HEIGHT ((uint16_t)240)
/**
* @brief HX8347D Registers
*/
#define LCD_REG_0 0x00
#define LCD_REG_1 0x01
#define LCD_REG_2 0x02
#define LCD_REG_3 0x03
#define LCD_REG_4 0x04
#define LCD_REG_5 0x05
#define LCD_REG_6 0x06
#define LCD_REG_7 0x07
#define LCD_REG_8 0x08
#define LCD_REG_9 0x09
#define LCD_REG_10 0x0A
#define LCD_REG_12 0x0C
#define LCD_REG_13 0x0D
#define LCD_REG_14 0x0E
#define LCD_REG_15 0x0F
#define LCD_REG_16 0x10
#define LCD_REG_17 0x11
#define LCD_REG_18 0x12
#define LCD_REG_19 0x13
#define LCD_REG_20 0x14
#define LCD_REG_21 0x15
#define LCD_REG_22 0x16
#define LCD_REG_23 0x17
#define LCD_REG_24 0x18
#define LCD_REG_25 0x19
#define LCD_REG_26 0x1A
#define LCD_REG_27 0x1B
#define LCD_REG_28 0x1C
#define LCD_REG_29 0x1D
#define LCD_REG_30 0x1E
#define LCD_REG_31 0x1F
#define LCD_REG_32 0x20
#define LCD_REG_33 0x21
#define LCD_REG_34 0x22
#define LCD_REG_35 0x23
#define LCD_REG_36 0x24
#define LCD_REG_37 0x25
#define LCD_REG_39 0x27
#define LCD_REG_40 0x28
#define LCD_REG_41 0x29
#define LCD_REG_43 0x2B
#define LCD_REG_45 0x2D
#define LCD_REG_48 0x30
#define LCD_REG_49 0x31
#define LCD_REG_50 0x32
#define LCD_REG_51 0x33
#define LCD_REG_52 0x34
#define LCD_REG_53 0x35
#define LCD_REG_54 0x36
#define LCD_REG_55 0x37
#define LCD_REG_56 0x38
#define LCD_REG_57 0x39
#define LCD_REG_59 0x3B
#define LCD_REG_60 0x3C
#define LCD_REG_61 0x3D
#define LCD_REG_62 0x3E
#define LCD_REG_63 0x3F
#define LCD_REG_64 0x40
#define LCD_REG_65 0x41
#define LCD_REG_66 0x42
#define LCD_REG_67 0x43
#define LCD_REG_68 0x44
#define LCD_REG_69 0x45
#define LCD_REG_70 0x46
#define LCD_REG_71 0x47
#define LCD_REG_72 0x48
#define LCD_REG_73 0x49
#define LCD_REG_74 0x4A
#define LCD_REG_75 0x4B
#define LCD_REG_76 0x4C
#define LCD_REG_77 0x4D
#define LCD_REG_78 0x4E
#define LCD_REG_79 0x4F
#define LCD_REG_80 0x50
#define LCD_REG_81 0x51
#define LCD_REG_82 0x52
#define LCD_REG_83 0x53
#define LCD_REG_84 0x54
#define LCD_REG_85 0x55
#define LCD_REG_86 0x56
#define LCD_REG_87 0x57
#define LCD_REG_88 0x58
#define LCD_REG_89 0x59
#define LCD_REG_90 0x5A
#define LCD_REG_91 0x5B
#define LCD_REG_92 0x5C
#define LCD_REG_93 0x5D
#define LCD_REG_96 0x60
#define LCD_REG_97 0x61
#define LCD_REG_106 0x6A
#define LCD_REG_118 0x76
#define LCD_REG_128 0x80
#define LCD_REG_129 0x81
#define LCD_REG_130 0x82
#define LCD_REG_131 0x83
#define LCD_REG_132 0x84
#define LCD_REG_133 0x85
#define LCD_REG_134 0x86
#define LCD_REG_135 0x87
#define LCD_REG_136 0x88
#define LCD_REG_137 0x89
#define LCD_REG_139 0x8B
#define LCD_REG_140 0x8C
#define LCD_REG_141 0x8D
#define LCD_REG_143 0x8F
#define LCD_REG_144 0x90
#define LCD_REG_145 0x91
#define LCD_REG_146 0x92
#define LCD_REG_147 0x93
#define LCD_REG_148 0x94
#define LCD_REG_149 0x95
#define LCD_REG_150 0x96
#define LCD_REG_151 0x97
#define LCD_REG_152 0x98
#define LCD_REG_153 0x99
#define LCD_REG_154 0x9A
#define LCD_REG_157 0x9D
#define LCD_REG_192 0xC0
#define LCD_REG_193 0xC1
#define LCD_REG_227 0xE3
#define LCD_REG_229 0xE5
#define LCD_REG_231 0xE7
#define LCD_REG_239 0xEF
#define LCD_REG_232 0xE8
#define LCD_REG_233 0xE9
#define LCD_REG_234 0xEA
#define LCD_REG_235 0xEB
#define LCD_REG_236 0xEC
#define LCD_REG_237 0xED
#define LCD_REG_241 0xF1
#define LCD_REG_242 0xF2
/**
* @}
*/
/** @defgroup HX8347D_Exported_Functions
* @{
*/
void hx8347d_Init(void);
uint16_t hx8347d_ReadID(void);
void hx8347d_WriteReg(uint8_t LCDReg, uint16_t LCDRegValue);
uint16_t hx8347d_ReadReg(uint8_t LCDReg);
void hx8347d_DisplayOn(void);
void hx8347d_DisplayOff(void);
void hx8347d_SetCursor(uint16_t Xpos, uint16_t Ypos);
void hx8347d_WritePixel(uint16_t Xpos, uint16_t Ypos, uint16_t RGBCode);
uint16_t hx8347d_ReadPixel(uint16_t Xpos, uint16_t Ypos);
void hx8347d_DrawHLine(uint16_t RGBCode, uint16_t Xpos, uint16_t Ypos, uint16_t Length);
void hx8347d_DrawVLine(uint16_t RGBCode, uint16_t Xpos, uint16_t Ypos, uint16_t Length);
void hx8347d_DrawBitmap(uint16_t Xpos, uint16_t Ypos, uint8_t *pbmp);
void hx8347d_SetDisplayWindow(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
uint16_t hx8347d_GetLcdPixelWidth(void);
uint16_t hx8347d_GetLcdPixelHeight(void);
/* LCD driver structure */
extern LCD_DrvTypeDef hx8347d_drv;
/* LCD IO functions */
void LCD_IO_Init(void);
void LCD_IO_WriteMultipleData(uint8_t *pData, uint32_t Size);
void LCD_IO_WriteReg(uint8_t Reg);
uint16_t LCD_IO_ReadData(uint16_t Reg);
void LCD_Delay (uint32_t delay);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* HX8347D_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
<head>
<meta charset="utf-8" />
<meta name="generator" content="pandoc" />
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
<title>Release Notes for SN65DP141 Component Drivers</title>
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code{white-space: pre-wrap;}
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<div class="row">
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<div class="card fluid">
<div class="sectione dark">
<center>
<h1 id="release-notes-for-sn65dp141-component-drivers"><small>Release Notes for</small> <mark>SN65DP141 Component Drivers</mark></h1>
<p>Copyright © 2017 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img src="../../../../_htmresc/st_logo.png" alt="ST logo" /></a>
</center>
</div>
</div>
<h1 id="license">License</h1>
<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
<h1 id="purpose">Purpose</h1>
<p>This directory contains the SN65DP141 component drivers.</p>
</div>
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
<input type="checkbox" id="collapse-section13" checked aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.0.2 / 23-July-2020</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>Update release notes format</li>
<li>Correct misspelled words</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.0.1 / 10-October-2018</label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li>Fix compilation warnings detected by IAR V8.30.1</li>
</ul>
</div>
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<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.0.0 / 16-November-2017</label>
<div>
<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>First official release of SN65DP141 Component driver</li>
</ul>
</div>
</div>
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346
USB-PD_Provider_1port/Drivers/BSP/Components/sn65dp141/sn65dp141.c Normal file
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/**
******************************************************************************
* @file sn65dp141.c
* @author MCD Application Team
* @brief This file provides a set of functions needed to manage the SN65DP141
* DisplayPort Linear Redriver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "sn65dp141.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @defgroup SN65DP141
* @brief This file provides a set of functions needed to drive the
* SN65DP141 DisplayPort Linear Redriver.
* @{
*/
/** @defgroup SN65DP141_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup SN65DP141_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup SN65DP141_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SN65DP141_Private_Variables
* @{
*/
/* DisplayPort Linear Redriver Driver structure initialization */
DPREDRIVER_Drv_t sn65dp141_drv =
{
sn65dp141_Init,
sn65dp141_DeInit,
sn65dp141_PowerOn,
sn65dp141_PowerOff,
sn65dp141_SetEQGain,
sn65dp141_EnableChannel,
sn65dp141_DisableChannel
};
/**
* @}
*/
/** @defgroup SN65DP141_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup SN65DP141_Private_Functions
* @{
*/
/**
* @brief Initialize the SN65DP141 and configure the needed hardware resources.
* @param Address Device address on communication Bus.
* @retval None
*/
uint32_t sn65dp141_Init(uint16_t Address)
{
uint32_t err_count = 0;
/* Low level init */
err_count += MUX_IO_Init();
/* Restore SN65DP141 registers reset values */
err_count += MUX_IO_Write(Address, SN65DP141_REG_CFG, 0x00);
err_count += MUX_IO_Write(Address, SN65DP141_REG_CHEN, 0x00);
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH0_CFG, 0x00);
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH0_EN, 0x00);
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH1_CFG, 0x00);
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH1_EN, 0x00);
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH2_CFG, 0x00);
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH2_EN, 0x00);
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH3_CFG, 0x00);
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH3_EN, 0x00);
return err_count;
}
/**
* @brief Release the hardware resources required to use the SN65DP141
* @param Address SN65DP141 address on communication Bus.
* @retval none
*/
void sn65dp141_DeInit(uint16_t Address)
{
/* Restore SN65DP141 registers reset values */
MUX_IO_Write(Address, SN65DP141_REG_CFG, 0x00);
MUX_IO_Write(Address, SN65DP141_REG_CHEN, 0x00);
MUX_IO_Write(Address, SN65DP141_REG_CH0_CFG, 0x00);
MUX_IO_Write(Address, SN65DP141_REG_CH0_EN, 0x00);
MUX_IO_Write(Address, SN65DP141_REG_CH1_CFG, 0x00);
MUX_IO_Write(Address, SN65DP141_REG_CH1_EN, 0x00);
MUX_IO_Write(Address, SN65DP141_REG_CH2_CFG, 0x00);
MUX_IO_Write(Address, SN65DP141_REG_CH2_EN, 0x00);
MUX_IO_Write(Address, SN65DP141_REG_CH3_CFG, 0x00);
MUX_IO_Write(Address, SN65DP141_REG_CH3_EN, 0x00);
/* Low level de-init */
MUX_IO_DeInit();
}
/**
* @brief Power on the SN65DP141.
* @param Address SN65DP141 address on communication Bus.
* @retval 0: successful, else failed
*/
uint32_t sn65dp141_PowerOn(uint16_t Address)
{
uint32_t err_count = 0;
uint8_t cfg;
/* Read General Device Settings register*/
err_count += MUX_IO_Read(Address, SN65DP141_REG_CFG, &cfg);
/* Clear PWRDOWN bit of General Device Settings register */
cfg &= ~SN65DP141_REG_CFG_PWRDOWN;
err_count += MUX_IO_Write(Address, SN65DP141_REG_CFG, cfg);
return err_count;
}
/**
* @brief Power down the SN65DP141.
* @param Address SN65DP141 address on communication Bus.
* @retval 0: successful, else failed
*/
uint32_t sn65dp141_PowerOff(uint16_t Address)
{
uint32_t err_count = 0;
uint8_t cfg;
/* Read General Device Settings register*/
err_count += MUX_IO_Read(Address, SN65DP141_REG_CFG, &cfg);
/* Set PWRDOWN bit of General Device Settings register */
cfg |= SN65DP141_REG_CFG_PWRDOWN;
err_count += MUX_IO_Write(Address, SN65DP141_REG_CFG, cfg);
return err_count;
}
/**
* @brief Set the equalizer gain for a given channel.
* @param Address SN65DP141 address on communication Bus.
* @param ChannelId Channel identifier.
* This parameter can be take one of the following values:
* CHANNEL_DP0
* CHANNEL_DP1
* CHANNEL_DP2
* CHANNEL_DP3
* @param EQGain Equalizer gain.
* This parameter must be a value between 0x00 and 0x07.
* @retval 0: successful, else failed
*/
uint32_t sn65dp141_SetEQGain(uint16_t Address,
DPREDRIVER_ChannelId_t ChannelId,
uint8_t EQGain)
{
uint32_t err_count = 0;
uint8_t chctrl;
uint8_t cfg;
switch(ChannelId)
{
case CHANNEL_DP0:
cfg = SN65DP141_REG_CH0_CFG;
break;
case CHANNEL_DP1:
cfg = SN65DP141_REG_CH1_CFG;
break;
case CHANNEL_DP2:
cfg = SN65DP141_REG_CH2_CFG;
break;
case CHANNEL_DP3:
cfg = SN65DP141_REG_CH3_CFG;
break;
default:
cfg = SN65DP141_REG_CH0_CFG;
break;
}
/* Read Channel x Control Settings register */
err_count += MUX_IO_Read(Address, cfg, &chctrl);
/* Set the equalizer gain bit field (EQ setting) for concerned channel */
chctrl = (chctrl & (~(uint8_t)SN65DP141_REG_CHxCFG_EQ_SETTING_Msk)) | (EQGain << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos);
/* Enable Max gain for TX & RX */
chctrl |= SN65DP141_REG_CHxCFG_RX_GAIN_1 | SN65DP141_REG_CHxCFG_EQ_DC_GAIN | SN65DP141_REG_CHxCFG_TX_GAIN;
/* Update Channel x Control Settings register */
err_count += MUX_IO_Write(Address, cfg, chctrl);
return err_count;
}
/**
* @brief Enable a DP channel.
* @param Address SN65DP141 address on communication Bus.
* @param ChannelId Channel identifier.
* This parameter can be take one of the following values:
* CHANNEL_DP0
* CHANNEL_DP1
* CHANNEL_DP2
* CHANNEL_DP3
* @retval 0: successful, else failed
*/
uint32_t sn65dp141_EnableChannel(uint16_t Address,
DPREDRIVER_ChannelId_t ChannelId)
{
uint32_t err_count = 0;
uint8_t chen;
/* Read Channel Enable register */
err_count += MUX_IO_Read(Address, SN65DP141_REG_CHEN, &chen);
/* Clear LN_EN_CHx bit of Channel Enable register */
switch(ChannelId)
{
case CHANNEL_DP0:
chen &= ~SN65DP141_REG_CHEN_LN_EN_CH0;
break;
case CHANNEL_DP1:
chen &= ~SN65DP141_REG_CHEN_LN_EN_CH1;
break;
case CHANNEL_DP2:
chen &= ~SN65DP141_REG_CHEN_LN_EN_CH2;
break;
case CHANNEL_DP3:
chen &= ~SN65DP141_REG_CHEN_LN_EN_CH3;
break;
default:
/* Nothing to do */
break;
}
err_count += MUX_IO_Write(Address, SN65DP141_REG_CHEN, chen);
return err_count;
}
/**
* @brief Disable a DP channel.
* @param Address SN65DP141 address on communication Bus.
* @param ChannelId Channel identifier.
* This parameter can be take one of the following values:
* CHANNEL_DP0
* CHANNEL_DP1
* CHANNEL_DP2
* CHANNEL_DP3
* @retval 0: successful, else failed
*/
uint32_t sn65dp141_DisableChannel(uint16_t Address,
DPREDRIVER_ChannelId_t ChannelId)
{
uint32_t err_count = 0;
uint8_t chen;
/* Read Channel Enable register */
err_count += MUX_IO_Read(Address, SN65DP141_REG_CHEN, &chen);
/* Set LN_EN_CHx bit of Channel Enable register */
switch(ChannelId)
{
case CHANNEL_DP0:
chen |= SN65DP141_REG_CHEN_LN_EN_CH0;
break;
case CHANNEL_DP1:
chen |= SN65DP141_REG_CHEN_LN_EN_CH1;
break;
case CHANNEL_DP2:
chen |= SN65DP141_REG_CHEN_LN_EN_CH2;
break;
case CHANNEL_DP3:
chen |= SN65DP141_REG_CHEN_LN_EN_CH3;
break;
default:
/* Nothing to do */
break;
}
err_count += MUX_IO_Write(Address, SN65DP141_REG_CHEN, chen);
return err_count;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file sn65dp141.h
* @author MCD Application Team
* @brief Header for sn65dp141.h module
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef SN65DP141_H
#define SN65DP141_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
#include "../Common/dpredriver.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup SN65DP141
* @{
*/
/** @defgroup SN65DP141_Exported_Constants
* @{
*/
/******************************* Register Map ********************************/
#define SN65DP141_REG_CFG 0x00 /*!< General Device Settings register */
#define SN65DP141_REG_CHEN 0x01 /*!< Channel Enable register */
#define SN65DP141_REG_CH0_CFG 0x02 /*!< Channel 0 Control Settings register */
#define SN65DP141_REG_CH0_EN 0x03 /*!< Channel 0 Enable Settings register */
#define SN65DP141_REG_CH1_CFG 0x05 /*!< Channel 1 Control Settings register */
#define SN65DP141_REG_CH1_EN 0x06 /*!< Channel 1 Enable Settings register */
#define SN65DP141_REG_CH2_CFG 0x08 /*!< Channel 2 Control Settings register */
#define SN65DP141_REG_CH2_EN 0x09 /*!< Channel 2 Enable Settings register */
#define SN65DP141_REG_CH3_CFG 0x0B /*!< Channel 3 Control Settings register */
#define SN65DP141_REG_CH3_EN 0x0C /*!< Channel 3 Enable Settings register */
/*********** Bit definition for General Device Settings register *************/
#define SN65DP141_REG_CFG_EQ_MODE_Pos (1U)
#define SN65DP141_REG_CFG_EQ_MODE_Msk (0x1U << SN65DP141_REG_CFG_EQ_MODE_Pos) /*!< 0x04*/
#define SN65DP141_REG_CFG_EQ_MODE SN65DP141_REG_CFG_EQ_MODE_Msk /*!< EQ mode (Cable mode v.s. Trace mode) */
#define SN65DP141_REG_CFG_SYNC_ALL_Pos (3U)
#define SN65DP141_REG_CFG_SYNC_ALL_Msk (0x1U << SN65DP141_REG_CFG_SYNC_ALL_Pos) /*!< 0x08*/
#define SN65DP141_REG_CFG_SYNC_ALL SN65DP141_REG_CFG_SYNC_ALL_Msk /*!< All settings from channel 1 will be used on all channels */
#define SN65DP141_REG_CFG_SYNC_23_Pos (4U)
#define SN65DP141_REG_CFG_SYNC_23_Msk (0x1U << SN65DP141_REG_CFG_SYNC23_Pos) /*!< 0x10*/
#define SN65DP141_REG_CFG_SYNC_23 SN65DP141_REG_CFG_SYNC_23_Msk /*!< All settings from channel 2 will be used for channel 2 and 3 */
#define SN65DP141_REG_CFG_SYNC_01_Pos (5U)
#define SN65DP141_REG_CFG_SYNC_01_Msk (0x1U << SN65DP141_REG_CFG_SYNC01_Pos) /*!< 0x20*/
#define SN65DP141_REG_CFG_SYNC_01 SN65DP141_REG_CFG_SYNC_01_Msk /*!< All settings from channel 1 will be used for channel 0 and 1 */
#define SN65DP141_REG_CFG_PWRDOWN_Pos (6U)
#define SN65DP141_REG_CFG_PWRDOWN_Msk (0x1U << SN65DP141_REG_CFG_PWRDOWN_Pos) /*!< 0x40*/
#define SN65DP141_REG_CFG_PWRDOWN SN65DP141_REG_CFG_PWRDOWN_Msk /*!< Power down the device */
#define SN65DP141_REG_CFG_SW_GPIO_Pos (7U)
#define SN65DP141_REG_CFG_SW_GPIO_Msk (0x1U << SN65DP141_REG_CFG_SW_GPIO_Pos) /*!< 0x80*/
#define SN65DP141_REG_CFG_SW_GPIO SN65DP141_REG_CFG_SW_GPIO_Msk /*!< Switching logic is controlled by GPIO or I2C */
/*********** Bit definition for Channel Enable register *************/
#define SN65DP141_REG_CHEN_LN_EN_CH0_Pos (0U)
#define SN65DP141_REG_CHEN_LN_EN_CH0_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH0_Pos) /*!< 0x01 */
#define SN65DP141_REG_CHEN_LN_EN_CH0 SN65DP141_REG_CHEN_LN_EN_CH0_Msk /*!< Channel 0 enable */
#define SN65DP141_REG_CHEN_LN_EN_CH1_Pos (1U)
#define SN65DP141_REG_CHEN_LN_EN_CH1_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH1_Pos) /*!< 0x02 */
#define SN65DP141_REG_CHEN_LN_EN_CH1 SN65DP141_REG_CHEN_LN_EN_CH1_Msk /*!< Channel 1 enable */
#define SN65DP141_REG_CHEN_LN_EN_CH2_Pos (2U)
#define SN65DP141_REG_CHEN_LN_EN_CH2_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH2_Pos) /*!< 0x04 */
#define SN65DP141_REG_CHEN_LN_EN_CH2 SN65DP141_REG_CHEN_LN_EN_CH2_Msk /*!< Channel 2 enable */
#define SN65DP141_REG_CHEN_LN_EN_CH3_Pos (3U)
#define SN65DP141_REG_CHEN_LN_EN_CH3_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH3_Pos) /*!< 0x08 */
#define SN65DP141_REG_CHEN_LN_EN_CH3 SN65DP141_REG_CHEN_LN_EN_CH3_Msk /*!< Channel 3 enable */
/*********** Bit definition for Channel x Control Settings register *************/
#define SN65DP141_REG_CHxCFG_RX_GAIN_Pos (0U)
#define SN65DP141_REG_CHxCFG_RX_GAIN_Msk (0x3U << SN65DP141_REG_CHxCFG_RX_GAIN_Pos) /*!< 0x03 */
#define SN65DP141_REG_CHxCFG_RX_GAIN SN65DP141_REG_CHxCFG_RX_GAIN_Msk /*!< Channel[x] RX_GAIN control */
#define SN65DP141_REG_CHxCFG_RX_GAIN_0 (0x1U << SN65DP141_REG_CHxCFG_RX_GAIN_Pos) /*!< 0x01 */
#define SN65DP141_REG_CHxCFG_RX_GAIN_1 (0x2U << SN65DP141_REG_CHxCFG_RX_GAIN_Pos) /*!< 0x02 */
#define SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Pos (2U)
#define SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Msk (0x1U << SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Pos) /*!< 0x04 */
#define SN65DP141_REG_CHxCFG_EQ_DC_GAIN SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Msk /*!< Channel[x] EQ DC gain */
#define SN65DP141_REG_CHxCFG_TX_GAIN_Pos (3U)
#define SN65DP141_REG_CHxCFG_TX_GAIN_Msk (0x1U << SN65DP141_REG_CHxCFG_TX_GAIN_Pos) /*!< 0x08 */
#define SN65DP141_REG_CHxCFG_TX_GAIN SN65DP141_REG_CHxCFG_TX_GAIN_Msk /*!< Channel[x] TX_DC_GAIN control */
#define SN65DP141_REG_CHxCFG_EQ_SETTING_Pos (4U)
#define SN65DP141_REG_CHxCFG_EQ_SETTING_Msk (0x7U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x70 */
#define SN65DP141_REG_CHxCFG_EQ_SETTING SN65DP141_REG_CHxCFG_EQ_SETTING_Msk /*!< Channel[x] TX_DC_GAIN control */
#define SN65DP141_REG_CHxCFG_EQ_SETTING_0 (0x1U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x10 */
#define SN65DP141_REG_CHxCFG_EQ_SETTING_1 (0x2U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x20 */
#define SN65DP141_REG_CHxCFG_EQ_SETTING_2 (0x4U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x40 */
/*********** Bit definition for Channel x Enable Settings register *************/
#define SN65DP141_REG_CHxCTL_DRV_EN_Pos (0U)
#define SN65DP141_REG_CHxCTL_DRV_EN_Msk (0x1U << SN65DP141_REG_CHxCTL_DRV_EN_Pos) /*!< 0x01 */
#define SN65DP141_REG_CHxCTL_DRV_EN SN65DP141_REG_CHxCTL_DRV_EN_Msk /*!< Channel[0] driver stage enable */
#define SN65DP141_REG_CHxCTL_EQ_EN_Pos (1U)
#define SN65DP141_REG_CHxCTL_EQ_EN_Msk (0x1U << SN65DP141_REG_CHxCTL_EQ_EN_Pos) /*!< 0x02 */
#define SN65DP141_REG_CHxCTL_EQ_EN SN65DP141_REG_CHxCTL_EQ_EN_Msk /*!< Channel[0] EQ stage enable */
#define SN65DP141_REG_CHxCTL_DRV_PEAK_Pos (2U)
#define SN65DP141_REG_CHxCTL_DRV_PEAK_Msk (0x1U << SN65DP141_REG_CHxCTL_DRV_PEAK_Pos) /*!< 0x04 */
#define SN65DP141_REG_CHxCTL_DRV_PEAK SN65DP141_REG_CHxCTL_DRV_PEAK_Msk /*!< Channel[0] driver peaking */
/** @defgroup SN65DP141_Channel_Identifier
* @{
*/
#define SN65DP141_CHANNEL_1 0x00U
#define SN65DP141_CHANNEL_2 0x01U
#define SN65DP141_CHANNEL_3 0x04U
#define SN65DP141_CHANNEL_4 0x08U
#define SN65DP141_CHANNEL_ALL 0x0FU
/**
* @}
*/
/** @defgroup SN65DP141_EQ_Mode
* @{
*/
#define SN65DP141_EQ_MODE_CABLE 0x00U
#define SN65DP141_EQ_MODE_TRACE SN65DP141_REG_CFG_EQ_MODE
/**
* @}
*/
/** @defgroup SN65DP141_Channel_Tracking
* @{
*/
#define SN65DP141_CHANNEL_TRACKING_NONE 0x00U
#define SN65DP141_CHANNEL_TRACKING_01 SN65DP141_REG_CFG_SYNC_01
#define SN65DP141_CHANNEL_TRACKING_23 SN65DP141_REG_CFG_SYNC_23
#define SN65DP141_CHANNEL_TRACKING_ALL SN65DP141_REG_CFG_SYNC_ALL
/**
* @}
*/
/** @defgroup SN65DP141_EQGAIN SN65DP141 Equalizer Gain
* @{
*/
#define SN65DP141_EQGAIN_0 0x0U
#define SN65DP141_EQGAIN_1 0x1U
#define SN65DP141_EQGAIN_2 0x2U
#define SN65DP141_EQGAIN_3 0x3U
#define SN65DP141_EQGAIN_4 0x4U
#define SN65DP141_EQGAIN_5 0x5U
#define SN65DP141_EQGAIN_6 0x6U
#define SN65DP141_EQGAIN_7 0x7U
/**
* @}
*/
/** @defgroup SN65DP141_Channel_RXGAIN
* @{
*/
#define SN65DP141_CHANNEL_RXGAIN_LOW 0x00U
#define SN65DP141_CHANNEL_RXGAIN_HIZ SN65DP141_REG_CHxCFG_RX_GAIN_0
#define SN65DP141_CHANNEL_RXGAIN_HIGH SN65DP141_REG_CHxCFG_RX_GAIN_1
/**
* @}
*/
/** @defgroup SN65DP141_Channel_EQDCGAIN
* @{
*/
#define SN65DP141_CHANNEL_EQDCGAIN_MINUS6DB 0x00U
#define SN65DP141_CHANNEL_EQDCGAIN_0DB SN65DP141_REG_CHxCFG_EQ_DC_GAIN
/**
* @}
*/
/** @defgroup SN65DP141_Channel_TXGAIN
* @{
*/
#define SN65DP141_CHANNEL_RXGAIN_0DB 0x00U
#define SN65DP141_CHANNEL_RXGAIN_6DB SN65DP141_REG_CHxCFG_TX_GAIN
/**
* @}
*/
/**
* @}
*/
#if defined(SN65DP141_DEBUG)
/** @defgroup SN65DP141_Exported_Structure SN65DP141 Exported Structure
* @{
*/
typedef union {
uint8_t Register;
struct {
uint8_t RESERVED :2;
uint8_t EQ_MODE :1;
uint8_t SYNC_ALL :1;
uint8_t SYNC_23 :1;
uint8_t SYNC_01 :1;
uint8_t PWRDOWN :1;
uint8_t SW_GPIO :1;
};
} SN65DP141_GeneralTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t LN_EN_CH0 :1;
uint8_t LN_EN_CH1 :1;
uint8_t LN_EN_CH2 :1;
uint8_t LN_EN_CH3 :1;
uint8_t RESERVED :4;
};
} SN65DP141_ChannelEnableTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t RX_GAIN_0 :1;
uint8_t RX_GAIN_1 :1;
uint8_t EQ_DC_GAIN :1;
uint8_t TX_GAIN :1;
uint8_t EQ_Setting_0 :1;
uint8_t EQ_Setting_1 :1;
uint8_t EQ_Setting_2 :1;
uint8_t RESERVED :1;
};
} SN65DP141_Channel0CtrlTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t RSVDRV_EN :1;
uint8_t EQ_EN :1;
uint8_t DRV_PEAK :1;
uint8_t RESERVED :5;
};
} SN65DP141_Channel0EnableTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t RX_GAIN_0 :1;
uint8_t RX_GAIN_1 :1;
uint8_t EQ_DC_GAIN :1;
uint8_t TX_GAIN :1;
uint8_t EQ_Setting_0 :1;
uint8_t EQ_Setting_1 :1;
uint8_t EQ_Setting_2 :1;
uint8_t RESERVED :1;
};
} SN65DP141_Channel1CtrlTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t RSVDRV_EN :1;
uint8_t EQ_EN :1;
uint8_t DRV_PEAK :1;
uint8_t RESERVED :5;
};
} SN65DP141_Channel1EnableTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t RX_GAIN_0 :1;
uint8_t RX_GAIN_1 :1;
uint8_t EQ_DC_GAIN :1;
uint8_t TX_GAIN :1;
uint8_t EQ_Setting_0 :1;
uint8_t EQ_Setting_1 :1;
uint8_t EQ_Setting_2 :1;
uint8_t RESERVED :1;
};
} SN65DP141_Channel2CtrlTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t RSVDRV_EN :1;
uint8_t EQ_EN :1;
uint8_t DRV_PEAK :1;
uint8_t RESERVED :5;
};
} SN65DP141_Channel2EnableTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t RX_GAIN_0 :1;
uint8_t RX_GAIN_1 :1;
uint8_t EQ_DC_GAIN :1;
uint8_t TX_GAIN :1;
uint8_t EQ_Setting_0 :1;
uint8_t EQ_Setting_1 :1;
uint8_t EQ_Setting_2 :1;
uint8_t RESERVED :1;
};
} SN65DP141_Channel3CtrlTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t RSVDRV_EN :1;
uint8_t EQ_EN :1;
uint8_t DRV_PEAK :1;
uint8_t RESERVED :5;
};
} SN65DP141_Channel3EnableTypeDef;
typedef struct
{
SN65DP141_GeneralTypeDef General; /*!< 0x00 (General Device Settings) */
SN65DP141_ChannelEnableTypeDef ChannelEnable; /*!< 0x01 (Channel Enable) */
SN65DP141_Channel0CtrlTypeDef Channel0Ctrl; /*!< 0x02 (Channel 0 Control Settings) */
SN65DP141_Channel0EnableTypeDef Channel0Enable; /*!< 0x03 (Channel 0 Enable Settings) */
SN65DP141_Channel1CtrlTypeDef Channel1Ctrl; /*!< 0x05 (Channel 1 Control Settings) */
SN65DP141_Channel1EnableTypeDef Channel1Enable; /*!< 0x06 (Channel 1 Enable Settings) */
SN65DP141_Channel2CtrlTypeDef Channel2Ctrl; /*!< 0x08 (Channel 2 Control Settings) */
SN65DP141_Channel2EnableTypeDef Channel2Enable; /*!< 0x09 (Channel 2 Enable Settings) */
SN65DP141_Channel3CtrlTypeDef Channel3Ctrl; /*!< 0x0B (Channel 3 Control Settings) */
SN65DP141_Channel3EnableTypeDef Channel3Enable; /*!< 0x0C (Channel 3 Enable Settings) */
} SN65DP141_RegistersTypeDef;
/**
* @}
*/
#endif /* SN65DP141_DEBUG */
/** @defgroup SN65DP141_Exported_Functions
* @{
*/
uint32_t sn65dp141_Init(uint16_t Address);
void sn65dp141_DeInit(uint16_t Address);
uint32_t sn65dp141_PowerOn(uint16_t Address);
uint32_t sn65dp141_PowerOff(uint16_t Address);
uint32_t sn65dp141_SetEQGain(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId, uint8_t EQGain);
uint32_t sn65dp141_EnableChannel(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId);
uint32_t sn65dp141_DisableChannel(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId);
/* MUX IO functions */
uint8_t MUX_IO_Init(void);
void MUX_IO_DeInit(void);
uint8_t MUX_IO_Write(uint16_t Addr, uint16_t Reg, uint8_t Data);
uint8_t MUX_IO_Read(uint16_t Addr, uint16_t Reg, uint8_t *pData);
uint32_t MUX_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials);
/**
* @}
*/
/** @defgroup SN65DP141_Exported_Variables
* @{
*/
/* DisplayPort Linear Redriver Driver structure */
extern DPREDRIVER_Drv_t sn65dp141_drv;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* SN65DP141_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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<div style="width: 1034px;" class="Section1"><span style="font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;"></span><small><a href="../../../../Release_Notes.html">Back to Release page</a></small>
<div id="header">
<h1 style="margin-bottom: 18pt; text-align: center;" align="center">Release
Notes for&nbsp;<span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">STLM75
Component Drivers</span></h1>
<p style="text-align: center;">Copyright 2014
STMicroelectronics</p>
<p style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;"><img style="border: 0px solid ; width: 112px; height: 83px;" alt="" id="_x0000_i1026" src="../../../../_htmresc/st_logo.png"></span></p>
</div>
<div id="license" class="topic1">
<h2>License</h2>
This software component is licensed by ST under BSD 3-Clause
license, the "License"; You may not use this component except in
compliance with
the License. You may obtain a copy of the License at:
<p style="text-align: center;"><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank">https://opensource.org/licenses/BSD-3-Clause</a></p>
</div>
<br>
<div id="release_container" class="topic1">
<div class="topic2" id="identification">
<h3 style="width: 220px;">V2.0.2 / 17-December-2018</h3>
</div>
<div class="topic3" id="changes">
<p class="MsoNormal" style="margin-top: 4.5pt; margin-right: 0cm; margin-bottom: 4.5pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square">
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Fix "Back to
Release page" link</span></li>
</ul>
</div>
<br>
</div>
<div style="margin-left: 40px;"><button id="filter_hist" onclick="toggle_history()">Show
History</button><br>
</div>
<div id="history" class="topic1" hidden="">
<h2>Update History</h2>
<b><u><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>
</span></u></b>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 223px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.1
/ 25-October-2018 <o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<span style="font-size: 10pt; font-family: Verdana;"></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
<ul style="list-style-type: square;">
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Fix
compilation warning in STLM75_Init() with IAR V8.30.1</span></li>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Reformat
the BSD 3-Clause license declaration in the files header (replace
license terms by a web reference to OSI website where those terms lie)</span></li>
</ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 223px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0
/ 11-September-2017 <o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<span style="font-size: 10pt; font-family: Verdana;"></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
<ul style="list-style-type: square;">
<li><span style="font-family: Verdana; font-size: 10pt;">Update
STLM75_ReadTemp return float instead of uint16_t</span><span style="font-family: Verdana; font-size: 10pt;"></span></li>
<li><span style="font-family: Verdana; font-size: 10pt;">Remove
date &amp; version from header</span></li>
</ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 223px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1
/ 24-November-2014 <o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<span style="font-size: 10pt; font-family: Verdana;"></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
<ul style="list-style-type: square;">
<li><span style="font-family: Verdana; font-size: 10pt;">stlm75.h:
change&nbsp;</span><span style="font-family: Verdana; font-size: 10pt;">"\"
by&nbsp;</span><span style="font-family: Verdana; font-size: 10pt;">"/" in the
include path to fix compilation issue under Linux</span></li>
</ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
/ 06-May-2014 <o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<span style="font-size: 10pt; font-family: Verdana;"></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
<ul style="list-style-type: square;">
<li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">First
official release of STLM75 Temperature Sensor Component driver</span></li>
</ul>
<span style="font-size: 10pt; font-family: Verdana;"></span>
<ul>
</ul>
</div>
<div id="product_doc" class="topic1">
<hr>
<p style="text-align: center;">For complete
documentation on STM32 Microcontrollers<span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="color: black;"></span></span>,
visit:&nbsp;<a href="http://www.st.com/STM32" target="_blank">www.st.com/STM32</a></p>
<br>
</div>
</div>
</body></html>

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/**
******************************************************************************
* @file stlm75.c
* @author MCD Application Team
* @brief This file provides a set of functions needed to manage the STLM75
* Temperature Sensor.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2014 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stlm75.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @defgroup STLM75
* @brief This file provides a set of functions needed to drive the
* STLM75 Temperature Sensor.
* @{
*/
/** @defgroup STLM75_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup STLM75_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup STLM75_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup STLM75_Private_Variables
* @{
*/
TSENSOR_DrvTypeDef Stlm75Drv =
{
STLM75_Init,
STLM75_IsReady,
STLM75_ReadStatus,
STLM75_ReadTemp,
};
/**
* @}
*/
/** @defgroup STLM75_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup STLM75_Private_Functions
* @{
*/
/**
* @brief Set STLM75 Initialization.
* @param DeviceAddr : Device ID address.
* @param pInitStruct: pointer to a STLM75_InitTypeDef structure
* that contains the configuration setting for the STLM75.
* @retval None
*/
void STLM75_Init(uint16_t DeviceAddr, TSENSOR_InitTypeDef *pInitStruct)
{
uint8_t confreg = 0;
uint16_t tempreg = 0;
/* Set the Configuration Register */
confreg = (uint8_t)(pInitStruct->AlertMode | pInitStruct->ConversionMode);
TSENSOR_IO_Write(DeviceAddr, &confreg, LM75_REG_CONF, 1);
/* Set the Temperature Registers */
/* Keep the sign bit and shift the temperature value (as given value is integer, the 0.5 digit is not set) */
tempreg = (((pInitStruct->TemperatureLimitHigh & 0x7F) << 8) | (pInitStruct->TemperatureLimitHigh & 0x80));
TSENSOR_IO_Write(DeviceAddr, (uint8_t*)(&tempreg), LM75_REG_TOS, 2);
tempreg = (((pInitStruct->TemperatureLimitLow & 0x7F) << 8) | (pInitStruct->TemperatureLimitLow & 0x80));
TSENSOR_IO_Write(DeviceAddr, (uint8_t*)(&tempreg), LM75_REG_THYS, 2);
}
/**
* @brief Check if STLM75 sensor is ready or not
* @param DeviceAddr : Device ID address.
* @param Trials: Number of trials
* @retval READY or NOT
*/
uint8_t STLM75_IsReady(uint16_t DeviceAddr, uint32_t Trials)
{
/* Configure the low level interface ---------------------------------------*/
TSENSOR_IO_Init();
/* Check is Temperature Sensor is Ready to use */
return TSENSOR_IO_IsDeviceReady(DeviceAddr, Trials);
}
/**
* @brief Read The Temperature Sensor Status
* @param DeviceAddr : Device ID address.
* @retval Status
*/
uint8_t STLM75_ReadStatus(uint16_t DeviceAddr)
{
uint8_t tmp = 0;
/* Read Status register */
TSENSOR_IO_Read(DeviceAddr, &tmp, LM75_REG_CONF, 1);
/* Return Temperature Sensor Status */
return (uint8_t)(tmp);
}
/**
* @brief Read temperature value of STLM75
* @param DeviceAddr: Device ID address
* @retval temperature value
*/
float STLM75_ReadTemp(uint16_t DeviceAddr)
{
uint16_t tempreg = 0;
uint16_t tmp = 0;
/* Read Temperature registers */
TSENSOR_IO_Read(DeviceAddr, (uint8_t*)(&tempreg), LM75_REG_TEMP, 2);
tmp = ((tempreg & 0x00FF) << 8) | ((tempreg & 0xFF00) >> 8);
tempreg = (((tmp & 0x7F80) >> 7) | (tmp & 0x8000));
/* Return Temperature value */
return (float)tempreg;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stlm75.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the stlm75.c
* temperature sensor driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2014 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STLM75_H
#define __STLM75_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "../Common/tsensor.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup STLM75
* @{
*/
/** @defgroup STLM75_Exported_Constants
* @{
*/
/******************************************************************************/
/*************************** START REGISTER MAPPING **************************/
/******************************************************************************/
/***************************** Read Access Only *******************************/
#define LM75_REG_TEMP 0x00 /*!< Temperature Register of LM75 */
/***************************** Read/Write Access ******************************/
#define LM75_REG_CONF 0x01 /*!< Configuration Register of LM75 */
#define LM75_REG_THYS 0x02 /*!< Temperature Register of LM75 */
#define LM75_REG_TOS 0x03 /*!< Over-temp Shutdown threshold Register of LM75 */
/******************************************************************************/
/**************************** END REGISTER MAPPING ***************************/
/******************************************************************************/
/** @defgroup Conversion_Mode_Selection
* @{
*/
#define STLM75_CONTINUOUS_MODE ((uint8_t)0x00)
#define STLM75_ONE_SHOT_MODE ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup Operation_Mode
* @{
*/
#define STLM75_COMPARATOR_MODE ((uint8_t)0x00)
#define STLM75_INTERRUPT_MODE ((uint8_t)0x02)
/**
* @}
*/
/**
* @}
*/
/** @defgroup STLM75_Exported_Functions
* @{
*/
/* Sensor Configuration Functions */
void STLM75_Init(uint16_t DeviceAddr, TSENSOR_InitTypeDef *pInitStruct);
uint8_t STLM75_IsReady(uint16_t DeviceAddr, uint32_t Trials);
/* Sensor Request Functions */
uint8_t STLM75_ReadStatus(uint16_t DeviceAddr);
float STLM75_ReadTemp(uint16_t DeviceAddr);
/* Temperature Sensor driver structure */
extern TSENSOR_DrvTypeDef Stlm75Drv;
/* Temperature Sensor IO functions */
void TSENSOR_IO_Init(void);
void TSENSOR_IO_Write(uint16_t DevAddress, uint8_t* pBuffer, uint8_t WriteAddr, uint16_t Length);
void TSENSOR_IO_Read(uint16_t DevAddress, uint8_t* pBuffer, uint8_t ReadAddr, uint16_t Length);
uint16_t TSENSOR_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STTS751_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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<title>Release Notes for TUSB546 Component Drivers</title>
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<h1 id="release-notes-for-tusb546-component-drivers"><small>Release Notes for</small> <mark>TUSB546 Component Drivers</mark></h1>
<p>Copyright © 2017 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img src="../../../../_htmresc/st_logo.png" alt="ST logo" /></a>
</center>
</div>
</div>
<h1 id="license">License</h1>
<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
<h1 id="purpose">Purpose</h1>
<p>This directory contains the TUSB546 component drivers.</p>
</div>
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.0.3 / 23-July-2020</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>Correct misspelled words</li>
<li>Update Release Notes format</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.0.2 / 10-October-2018</label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li>Fix compilation warnings detected by IAR V8.30.1</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.0.1 / 16-March-2018</label>
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<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Correct compilation warnings detected by SW4STM32 gcc compiler</li>
</ul>
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<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 16-November-2017</label>
<div>
<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>First official release of TUSB546 Component drivers</li>
</ul>
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USB-PD_Provider_1port/Drivers/BSP/Components/tusb546/tusb546.c Normal file
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/**
******************************************************************************
* @file tusb546.c
* @author MCD Application Team
* @brief This file provides a set of functions needed to manage the TUSB546
* (USB Type-C DP ALT Mode Linear Redriver Crosspoint Switch).
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "tusb546.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @defgroup TUSB546
* @brief This file provides a set of functions needed to drive the
* TUSB546 USB Type-C DP ALT Mode Linear Redriver Crosspoint Switch.
* @{
*/
/** @defgroup TUSB546_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup TUSB546_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup TUSB546_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup TUSB546_Private_Variables
* @{
*/
/* Type-C Crosspoint Switch Driver structure initialization */
TYPECSWITCH_Drv_t tusb546_drv_CrossSwitch =
{
tusb546_CrossSwitch_Init,
tusb546_CrossSwitch_DeInit,
tusb546_CrossSwitch_PowerOn,
tusb546_CrossSwitch_PowerOff,
tusb546_CrossSwitch_SetMode,
tusb546_CrossSwitch_IsSupportedMode
};
/* DisplayPort Linear Redriver driver structure initialization*/
DPREDRIVER_Drv_t tusb546_drv_LinearRedriver =
{
tusb546_DPRedriver_Init,
tusb546_DPRedriver_DeInit,
tusb546_DPRedriver_PowerOn,
tusb546_DPRedriver_PowerOff,
tusb546_DPRedriver_SetEQGain,
tusb546_DPRedriver_EnableChannel,
tusb546_DPRedriver_DisableChannel
};
/* Supported USB Type-C pin assignments */
static const uint32_t tusb546_SupportedModes =
( 1 << USB_NORMAL |
1 << USB_FLIPPED |
1 << DFP_D_PIN_ASSIGNMENT_C_NORMAL |
1 << DFP_D_PIN_ASSIGNMENT_C_FLIPPED |
1 << DFP_D_PIN_ASSIGNMENT_D_NORMAL |
1 << DFP_D_PIN_ASSIGNMENT_D_FLIPPED |
1 << DFP_D_PIN_ASSIGNMENT_E_NORMAL |
1 << DFP_D_PIN_ASSIGNMENT_E_FLIPPED |
1 << DFP_D_PIN_ASSIGNMENT_F_NORMAL |
1 << DFP_D_PIN_ASSIGNMENT_F_FLIPPED );
static uint8_t tusb546_IsInitialized_CrossSwitch = 0;
static uint8_t tusb546_IsInitialized_DPRedriver = 0;
/**
* @}
*/
/** @defgroup TUSB546_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup TUSB546_Private_Functions
* @{
*/
/**
* @brief Initialize the TUSB546 and configure the needed hardware resources
* (Type-C cross switch part).
* @param Address TUSB546 address on communication Bus.
* @retval 0: successful, else failed
*/
uint32_t tusb546_CrossSwitch_Init(uint16_t Address)
{
uint32_t err_count = 0;
tusb546_IsInitialized_CrossSwitch = 1;
if (!tusb546_IsInitialized_DPRedriver)
{
/* Low level init */
err_count += MUX_IO_Init();
/* Restore TUSB546 registers reset values */
err_count += MUX_IO_Write(Address, TUSB546_REG_CTRL, 0x01);
err_count += MUX_IO_Write(Address, TUSB546_REG_DP_CTRL1, 0x00);
err_count += MUX_IO_Write(Address, TUSB546_REG_DP_CTRL2, 0x00);
err_count += MUX_IO_Write(Address, TUSB546_REG_DP_CTRL4, 0x00);
err_count += MUX_IO_Write(Address, TUSB546_REG_USB3_CTRL1, 0x00);
err_count += MUX_IO_Write(Address, TUSB546_REG_USB3_CTRL2, 0x00);
err_count += MUX_IO_Write(Address, TUSB546_REG_USB3_CTRL3, 0x00);
}
return err_count;
}
/**
* @brief Release the hardware resources required to use the TUSB546
* (Type-C cross switch part).
* @param Address TUSB546 address on communication Bus.
* @retval none
*/
void tusb546_CrossSwitch_DeInit(uint16_t Address)
{
tusb546_IsInitialized_CrossSwitch = 0;
if ((!tusb546_IsInitialized_CrossSwitch) &&
(!tusb546_IsInitialized_DPRedriver))
{
/* Restore TUSB546 registers reset values */
MUX_IO_Write(Address, TUSB546_REG_CTRL, 0x01);
MUX_IO_Write(Address, TUSB546_REG_DP_CTRL1, 0x00);
MUX_IO_Write(Address, TUSB546_REG_DP_CTRL2, 0x00);
MUX_IO_Write(Address, TUSB546_REG_DP_CTRL4, 0x00);
MUX_IO_Write(Address, TUSB546_REG_USB3_CTRL1, 0x00);
MUX_IO_Write(Address, TUSB546_REG_USB3_CTRL2, 0x00);
MUX_IO_Write(Address, TUSB546_REG_USB3_CTRL3, 0x00);
/* Low level de-init */
MUX_IO_DeInit();
}
}
/**
* @brief Power on the TUSB546 (Type-C cross switch part).
* @param Address TUSB546 address on communication Bus.
* @retval 0: successful, else failed
*/
uint32_t tusb546_CrossSwitch_PowerOn(uint16_t Address)
{
uint32_t err_count = 0;
/* Enable USB3x port */
err_count += MUX_IO_Write(Address, TUSB546_REG_CTRL, TUSB546_REG_CTRL_CTLSEL_0);
return err_count;
}
/**
* @brief Power down the TUSB546 (Type-C cross switch part).
* @param Address TUSB546 address on communication Bus.
* @retval 0: successful, else failed
*/
uint32_t tusb546_CrossSwitch_PowerOff(uint16_t Address)
{
uint32_t err_count = 0;
/* All RX and TX for USB3 and DisplayPort are disabled */
err_count += MUX_IO_Write(Address, TUSB546_REG_CTRL, 0);
return err_count;
}
/**
* @brief Configure the TUSB546 according to the requested USB Type-C
* connector pin assignment.
* @param Address TUSB546 address on communication Bus.
* @param Mode USB Type-C connector pin assignment
* @retval 0: success, else error
*/
uint32_t tusb546_CrossSwitch_SetMode(uint16_t Address, TYPECSWITCH_Mode_t Mode)
{
uint32_t err_count = 0;
uint8_t flipsel;
uint8_t ctlsel;
uint8_t ctlreg;
switch(Mode)
{
case USB_NORMAL:
flipsel = 0;
ctlsel = TUSB546_REG_CTRL_CTLSEL_0;
break;
case USB_FLIPPED:
flipsel = TUSB546_REG_CTRL_FLIPSEL;
ctlsel = TUSB546_REG_CTRL_CTLSEL_0;
break;
case DFP_D_PIN_ASSIGNMENT_C_NORMAL:
case DFP_D_PIN_ASSIGNMENT_E_NORMAL:
flipsel = 0;
ctlsel = TUSB546_REG_CTRL_CTLSEL_1;
break;
case DFP_D_PIN_ASSIGNMENT_C_FLIPPED:
case DFP_D_PIN_ASSIGNMENT_E_FLIPPED:
flipsel = TUSB546_REG_CTRL_FLIPSEL;
ctlsel = TUSB546_REG_CTRL_CTLSEL_1;
break;
case DFP_D_PIN_ASSIGNMENT_D_NORMAL:
case DFP_D_PIN_ASSIGNMENT_F_NORMAL:
flipsel = 0;
ctlsel = TUSB546_REG_CTRL_CTLSEL;
break;
case DFP_D_PIN_ASSIGNMENT_D_FLIPPED:
case DFP_D_PIN_ASSIGNMENT_F_FLIPPED:
flipsel = TUSB546_REG_CTRL_FLIPSEL;
ctlsel = TUSB546_REG_CTRL_CTLSEL;
break;
default:
flipsel = 0;
ctlsel = 0;
break;
}
/* Get actual device configuration */
err_count += MUX_IO_Read(Address, TUSB546_REG_CTRL, &ctlreg);
ctlreg = (ctlreg & ~(uint8_t)(TUSB546_REG_CTRL_FLIPSEL | TUSB546_REG_CTRL_CTLSEL)) | (flipsel | ctlsel);
/* Update device configuration */
err_count += MUX_IO_Write(Address, TUSB546_REG_CTRL, ctlreg);
return err_count;
}
/**
* @brief Indicate whether the requested USB Type-C connector pin assignment
* is supported by the TUSB546.
* @param Mode USB Type-C connector pin assignment
* @retval 1: Mode supported, else Mode not supported
*/
uint32_t tusb546_CrossSwitch_IsSupportedMode(TYPECSWITCH_Mode_t Mode)
{
return (((1 << Mode) & tusb546_SupportedModes ) == 0) ? 0 : 1;
}
/**
* @brief Initialize the TUSB546 and configure the needed hardware resources
* (DisplayPort linear redriver part).
* @param Address TUSB546 address on communication Bus.
* @retval 0: successful, else failed
*/
uint32_t tusb546_DPRedriver_Init(uint16_t Address)
{
uint32_t err_count = 0;
tusb546_IsInitialized_DPRedriver = 1;
if (!tusb546_IsInitialized_CrossSwitch)
{
/* Low level init */
err_count += MUX_IO_Init();
}
return err_count;
}
/**
* @brief Release the hardware resources required to use the TUSB546
* (DisplayPort linear redriver part).
* @param Address TUSB546 address on communication Bus.
* @retval none
*/
void tusb546_DPRedriver_DeInit(uint16_t Address)
{
tusb546_IsInitialized_DPRedriver = 0;
if ((!tusb546_IsInitialized_CrossSwitch) &&
(!tusb546_IsInitialized_DPRedriver))
{
/* Restore TUSB546 registers reset values */
MUX_IO_Write(Address, TUSB546_REG_CTRL, 0x01);
MUX_IO_Write(Address, TUSB546_REG_DP_CTRL1, 0x00);
MUX_IO_Write(Address, TUSB546_REG_DP_CTRL2, 0x00);
MUX_IO_Write(Address, TUSB546_REG_DP_CTRL4, 0x00);
MUX_IO_Write(Address, TUSB546_REG_USB3_CTRL1, 0x00);
MUX_IO_Write(Address, TUSB546_REG_USB3_CTRL2, 0x00);
MUX_IO_Write(Address, TUSB546_REG_USB3_CTRL3, 0x00);
/* Low level de-init */
MUX_IO_DeInit();
}
}
/**
* @brief Power on the TUSB546 (DisplayPort linear redriver part).
* @param Address TUSB546 address on communication Bus.
* @retval 0: successful, else failed
*/
uint32_t tusb546_DPRedriver_PowerOn(uint16_t Address)
{
return 0;
}
/**
* @brief Power down the TUSB546 (DisplayPort linear redriver part).
* @param Address TUSB546 address on communication Bus.
* @retval 0: successful, else failed
*/
uint32_t tusb546_DPRedriver_PowerOff(uint16_t Address)
{
return 0;
}
/**
* @brief Set the equalizer gain for a given channel.
* @param Address TUSB546 address on communication Bus.
* @param ChannelId Channel identifier.
* This parameter can be take one of the following values:
* CHANNEL_DP0
* CHANNEL_DP1
* CHANNEL_DP2
* CHANNEL_DP3
* CHANNEL_RX1
* CHANNEL_RX2
* CHANNEL_SSTX
* @param EQGain Equalizer gain.
* This parameter must be a value between 0x00 and 0x0F.
* @retval 0: successful, else failed
*/
uint32_t tusb546_DPRedriver_SetEQGain(uint16_t Address,
DPREDRIVER_ChannelId_t ChannelId,
uint8_t EQGain)
{
uint32_t err_count = 0;
uint8_t eqsel = 0;
uint8_t reg_offset = 0;
uint8_t ctlreg;
uint8_t mask = 0;
switch(ChannelId)
{
case CHANNEL_DP0:
reg_offset = TUSB546_REG_DP_CTRL1;
mask = TUSB546_REG_DP_CTRL1_DP0EQ_SEL_Msk;
eqsel = EQGain;
break;
case CHANNEL_DP1:
reg_offset = TUSB546_REG_DP_CTRL1;
mask = TUSB546_REG_DP_CTRL1_DP1EQ_SEL_Msk;
eqsel = (EQGain << TUSB546_REG_DP_CTRL1_DP1EQ_SEL_Pos);
break;
case CHANNEL_DP2:
reg_offset = TUSB546_REG_DP_CTRL2;
mask = TUSB546_REG_DP_CTRL2_DP2EQ_SEL_Msk;
eqsel = EQGain;
break;
case CHANNEL_DP3:
reg_offset = TUSB546_REG_DP_CTRL2;
mask = TUSB546_REG_DP_CTRL2_DP3EQ_SEL_Msk;
eqsel = (EQGain << TUSB546_REG_DP_CTRL2_DP3EQ_SEL_Pos);
break;
case CHANNEL_RX1:
reg_offset = TUSB546_REG_USB3_CTRL1;
mask = TUSB546_REG_USB3_CTRL1_EQ1_SEL_Msk;
eqsel = EQGain;
break;
case CHANNEL_RX2:
reg_offset = TUSB546_REG_USB3_CTRL1;
mask = TUSB546_REG_USB3_CTRL1_EQ2_SEL_Msk;
eqsel = (EQGain << TUSB546_REG_USB3_CTRL1_EQ2_SEL_Pos);
break;
case CHANNEL_SSTX:
reg_offset = TUSB546_REG_USB3_CTRL2;
mask = TUSB546_USB3_CTRL2_SSEQ_SEL_Msk;
eqsel = EQGain;
break;
}
if (reg_offset != 0)
{
/* Set EQ_OVERRIDE to use EQ settings from registers instead of value sample from pins */
err_count += MUX_IO_Write(Address, TUSB546_REG_CTRL, TUSB546_REG_CTRL_EQ_OVERRIDE);
/* Get actual EQ configuration */
err_count += MUX_IO_Read(Address, reg_offset, &ctlreg);
ctlreg = (ctlreg & ~(mask)) | eqsel;
/* Update EQ configuration */
err_count += MUX_IO_Write(Address, reg_offset, ctlreg);
}
return err_count;
}
/**
* @brief Enable a DP channel.
* @param Address TUSB546 address on communication Bus.
* @param ChannelId Channel identifier.
* This parameter can be take one of the following values:
* CHANNEL_DP0
* CHANNEL_DP1
* CHANNEL_DP2
* CHANNEL_DP3
* @retval 0: successful, else failed
*/
uint32_t tusb546_DPRedriver_EnableChannel(uint16_t Address,
DPREDRIVER_ChannelId_t ChannelId)
{
uint32_t err_count = 0;
uint8_t ctlreg;
err_count += MUX_IO_Read(Address, TUSB546_REG_DP_CTRL4, &ctlreg);
switch(ChannelId)
{
case CHANNEL_DP0:
ctlreg &= ~TUSB546_REG_DP_CTRL4_DP0_DISABLE;
break;
case CHANNEL_DP1:
ctlreg &= ~TUSB546_REG_DP_CTRL4_DP1_DISABLE;
break;
case CHANNEL_DP2:
ctlreg &= ~TUSB546_REG_DP_CTRL4_DP2_DISABLE;
break;
case CHANNEL_DP3:
ctlreg &= ~TUSB546_REG_DP_CTRL4_DP3_DISABLE;
break;
default:
/* Nothing to do */
break;
}
/* Enable the DP line */
err_count += MUX_IO_Write(Address, TUSB546_REG_DP_CTRL4, ctlreg);
return err_count;
}
/**
* @brief Disable a DP channel.
* @param Address TUSB546 address on communication Bus.
* @param ChannelId Channel identifier.
* This parameter can be take one of the following values:
* CHANNEL_DP0
* CHANNEL_DP1
* CHANNEL_DP2
* CHANNEL_DP3
* @retval 0: successful, else failed
*/
uint32_t tusb546_DPRedriver_DisableChannel(uint16_t Address,
DPREDRIVER_ChannelId_t ChannelId)
{
uint32_t err_count = 0;
uint8_t ctlreg;
err_count += MUX_IO_Read(Address, TUSB546_REG_DP_CTRL4, &ctlreg);
switch(ChannelId)
{
case CHANNEL_DP0:
ctlreg |= TUSB546_REG_DP_CTRL4_DP0_DISABLE;
break;
case CHANNEL_DP1:
ctlreg |= TUSB546_REG_DP_CTRL4_DP1_DISABLE;
break;
case CHANNEL_DP2:
ctlreg |= TUSB546_REG_DP_CTRL4_DP2_DISABLE;
break;
case CHANNEL_DP3:
ctlreg |= TUSB546_REG_DP_CTRL4_DP3_DISABLE;
break;
default:
/* Nothing to do */
break;
}
/* Disable the DP line */
err_count += MUX_IO_Write(Address, TUSB546_REG_DP_CTRL4, ctlreg);
return err_count;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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USB-PD_Provider_1port/Drivers/BSP/Components/tusb546/tusb546.h Normal file
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/**
******************************************************************************
* @file tusb546.h
* @author MCD Application Team
* @brief Header for tusb546.h module
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef TUSB546_H
#define TUSB546_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
#include "../Common/usbtypecswitch.h"
#include "../Common/dpredriver.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup TUSB546
* @{
*/
/** @defgroup TUSB546_Exported_Constants
* @{
*/
/******************************* Register Map ********************************/
#define TUSB546_REG_CTRL 0x0A /*!< */
#define TUSB546_REG_DP_CTRL1 0x10 /*!< */
#define TUSB546_REG_DP_CTRL2 0x11 /*!< */
#define TUSB546_REG_DP_CTRL3 0x12 /*!< */
#define TUSB546_REG_DP_CTRL4 0x13 /*!< */
#define TUSB546_REG_USB3_CTRL1 0x20 /*!< */
#define TUSB546_REG_USB3_CTRL2 0x21 /*!< */
#define TUSB546_REG_USB3_CTRL3 0x22 /*!< */
/*********************** Bit definition for CTRL register *******************/
#define TUSB546_REG_CTRL_CTLSEL_Pos (0U)
#define TUSB546_REG_CTRL_CTLSEL_Msk (0x3U << TUSB546_REG_CTRL_CTLSEL_Pos) /*!< 0x03*/
#define TUSB546_REG_CTRL_CTLSEL TUSB546_REG_CTRL_CTLSEL_Msk /*!< DP Alt mode and USB 3.1 Switch Control */
#define TUSB546_REG_CTRL_CTLSEL_0 (0x1 << TUSB546_REG_CTRL_CTLSEL_Pos) /*!< 0x01 */
#define TUSB546_REG_CTRL_CTLSEL_1 (0x2 << TUSB546_REG_CTRL_CTLSEL_Pos) /*!< 0x02 */
#define TUSB546_REG_CTRL_FLIPSEL_Pos (2U)
#define TUSB546_REG_CTRL_FLIPSEL_Msk (0x1U << TUSB546_REG_CTRL_FLIPSEL_Pos) /*!< 0x04*/
#define TUSB546_REG_CTRL_FLIPSEL TUSB546_REG_CTRL_FLIPSEL_Msk /*!< Flip Control */
#define TUSB546_REG_CTRL_HPDIN_OVERRIDE_Pos (3U)
#define TUSB546_REG_CTRL_HPDIN_OVERRIDE_Msk (0x1U << TUSB546_REG_CTRL_HPDIN_OVERRIDE_Pos) /*!< 0x08*/
#define TUSB546_REG_CTRL_HPDIN_OVERRIDE TUSB546_REG_CTRL_HPDIN_OVERRIDE_Msk /*!< HPDIN control */
#define TUSB546_REG_CTRL_EQ_OVERRIDE_Pos (4U)
#define TUSB546_REG_CTRL_EQ_OVERRIDE_Msk (0x1U << TUSB546_REG_CTRL_EQ_OVERRIDE_Pos) /*!< 0x10*/
#define TUSB546_REG_CTRL_EQ_OVERRIDE TUSB546_REG_CTRL_EQ_OVERRIDE_Msk /*!< EQ settings control */
#define TUSB546_REG_CTRL_SWAP_HPDIN_Pos (5U)
#define TUSB546_REG_CTRL_SWAP_HPDIN_Msk (0x1U << TUSB546_REG_CTRL_SWAP_HPDIN_Pos) /*!< 0x20*/
#define TUSB546_REG_CTRL_SWAP_HPDIN TUSB546_REG_CTRL_SWAP_HPDIN_Msk /*!< HPDIN pin control */
/********************* Bit definition for DP_CTRL1 register *****************/
#define TUSB546_REG_DP_CTRL1_DP0EQ_SEL_Pos (0U)
#define TUSB546_REG_DP_CTRL1_DP0EQ_SEL_Msk (0xFU << TUSB546_REG_DP_CTRL1_DP0EQ_SEL_Pos) /*!< 0x0F */
#define TUSB546_REG_DP_CTRL1_DP0EQ_SEL TUSB546_REG_DP_CTRL1_DP0EQ_SEL_Msk /*!< Field selects between 0 to 14dB of EQ for DP lane 0 */
#define TUSB546_REG_DP_CTRL1_DP0EQ_SEL_0 (0x1 << TUSB546_REG_DP_CTRL1_DP0EQ_SEL_Pos) /*!< 0x01 */
#define TUSB546_REG_DP_CTRL1_DP0EQ_SEL_1 (0x2 << TUSB546_REG_DP_CTRL1_DP0EQ_SEL_Pos) /*!< 0x02 */
#define TUSB546_REG_DP_CTRL1_DP0EQ_SEL_2 (0x4 << TUSB546_REG_DP_CTRL1_DP0EQ_SEL_Pos) /*!< 0x04 */
#define TUSB546_REG_DP_CTRL1_DP0EQ_SEL_4 (0x8 << TUSB546_REG_DP_CTRL1_DP0EQ_SEL_Pos) /*!< 0x08 */
#define TUSB546_REG_DP_CTRL1_DP1EQ_SEL_Pos (4U)
#define TUSB546_REG_DP_CTRL1_DP1EQ_SEL_Msk (0xFU << TUSB546_REG_DP_CTRL1_DP1EQ_SEL_Pos) /*!< 0xF0*/
#define TUSB546_REG_DP_CTRL1_DP1EQ_SEL TUSB546_REG_DP_CTRL1_DP1EQ_SEL_Msk /*!< Field selects between 0 to 14dB of EQ for DP lane 1 */
#define TUSB546_REG_DP_CTRL1_DP1EQ_SEL_0 (0x1 << TUSB546_REG_DP_CTRL1_DP1EQ_SEL_Pos) /*!< 0x10 */
#define TUSB546_REG_DP_CTRL1_DP1EQ_SEL_1 (0x2 << TUSB546_REG_DP_CTRL1_DP1EQ_SEL_Pos) /*!< 0x20 */
#define TUSB546_REG_DP_CTRL1_DP1EQ_SEL_2 (0x4 << TUSB546_REG_DP_CTRL1_DP1EQ_SEL_Pos) /*!< 0x40 */
#define TUSB546_REG_DP_CTRL1_DP1EQ_SEL_4 (0x8 << TUSB546_REG_DP_CTRL1_DP1EQ_SEL_Pos) /*!< 0x80 */
/********************* Bit definition for DP_CTRL2 register *****************/
#define TUSB546_REG_DP_CTRL2_DP2EQ_SEL_Pos (0U)
#define TUSB546_REG_DP_CTRL2_DP2EQ_SEL_Msk (0xFU << TUSB546_REG_DP_CTRL2_DP2EQ_SEL_Pos) /*!< 0x0F */
#define TUSB546_REG_DP_CTRL2_DP2EQ_SEL TUSB546_REG_DP_CTRL2_DP2EQ_SEL_Msk /*!< Field selects between 0 to 14dB of EQ for DP lane 2 */
#define TUSB546_REG_DP_CTRL1_DP2EQ_SEL_0 (0x1 << TUSB546_REG_DP_CTRL2_DP2EQ_SEL_Pos) /*!< 0x01 */
#define TUSB546_REG_DP_CTRL1_DP2EQ_SEL_1 (0x2 << TUSB546_REG_DP_CTRL2_DP2EQ_SEL_Pos) /*!< 0x02 */
#define TUSB546_REG_DP_CTRL1_DP2EQ_SEL_2 (0x4 << TUSB546_REG_DP_CTRL2_DP2EQ_SEL_Pos) /*!< 0x04 */
#define TUSB546_REG_DP_CTRL1_DP2EQ_SEL_4 (0x8 << TUSB546_REG_DP_CTRL2_DP2EQ_SEL_Pos) /*!< 0x08 */
#define TUSB546_REG_DP_CTRL2_DP3EQ_SEL_Pos (4U)
#define TUSB546_REG_DP_CTRL2_DP3EQ_SEL_Msk (0xFU << TUSB546_REG_DP_CTRL2_DP3EQ_SEL_Pos) /*!< 0xF0*/
#define TUSB546_REG_DP_CTRL2_DP3EQ_SEL TUSB546_REG_DP_CTRL2_DP3EQ_SEL_Msk /*!< Field selects between 0 to 14dB of EQ for DP lane 3 */
#define TUSB546_REG_DP_CTRL1_DP3EQ_SEL_0 (0x1 << TUSB546_REG_DP_CTRL2_DP3EQ_SEL_Pos) /*!< 0x10 */
#define TUSB546_REG_DP_CTRL1_DP3EQ_SEL_1 (0x2 << TUSB546_REG_DP_CTRL2_DP3EQ_SEL_Pos) /*!< 0x20 */
#define TUSB546_REG_DP_CTRL1_DP3EQ_SEL_2 (0x4 << TUSB546_REG_DP_CTRL2_DP3EQ_SEL_Pos) /*!< 0x40 */
#define TUSB546_REG_DP_CTRL1_DP3EQ_SEL_4 (0x8 << TUSB546_REG_DP_CTRL2_DP3EQ_SEL_Pos) /*!< 0x80 */
/********************* Bit definition for DP_CTRL3 register *****************/
#define TUSB546_REG_DP_CTRL3_LANE_COUNT_SET_Pos (0U)
#define TUSB546_REG_DP_CTRL3_LANE_COUNT_SET_Msk (0x1FU << TUSB546_REG_DP_CTRL3_LANE_COUNT_SET_Pos) /*!< 0x1F */
#define TUSB546_REG_DP_CTRL3_LANE_COUNT_SET TUSB546_REG_DP_CTRL3_LANE_COUNT_SET_Msk /*!< */
#define TUSB546_REG_DP_CTRL3_SET_POWER_STATE_Pos (5U)
#define TUSB546_REG_DP_CTRL3_SET_POWER_STATE_Msk (0x3U << TUSB546_REG_DP_CTRL3_SET_POWER_STATE5_Pos) /*!< 0x60 */
#define TUSB546_REG_DP_CTRL3_SET_POWER_STATE TUSB546_REG_DP_CTRL3_SET_POWER_STATE5_Msk /*!< */
#define TUSB546_REG_DP_CTRL3_SET_POWER_STATE_0 (0x1 << TUSB546_REG_DP_CTRL3_SET_POWER_STATE_Pos) /*!< 0x20 */
#define TUSB546_REG_DP_CTRL3_SET_POWER_STATE_1 (0x2 << TUSB546_REG_DP_CTRL3_SET_POWER_STATE_Pos) /*!< 0x40 */
/********************* Bit definition for DP_CTRL4 register *****************/
#define TUSB546_REG_DP_CTRL4_DP0_DISABLE_Pos (0U)
#define TUSB546_REG_DP_CTRL4_DP0_DISABLE_Msk (0x1U << TUSB546_REG_DP_CTRL4_DP0_DISABLE_Pos) /*!< 0x01 */
#define TUSB546_REG_DP_CTRL4_DP0_DISABLE TUSB546_REG_DP_CTRL4_DP0_DISABLE_Msk /*!< DP Lane 0 disable */
#define TUSB546_REG_DP_CTRL4_DP1_DISABLE_Pos (1U)
#define TUSB546_REG_DP_CTRL4_DP1_DISABLE_Msk (0x1U << TUSB546_REG_DP_CTRL4_DP1_DISABLE_Pos) /*!< 0x02 */
#define TUSB546_REG_DP_CTRL4_DP1_DISABLE TUSB546_REG_DP_CTRL4_DP1_DISABLE_Msk /*!< DP Lane 1 disable */
#define TUSB546_REG_DP_CTRL4_DP2_DISABLE_Pos (2U)
#define TUSB546_REG_DP_CTRL4_DP2_DISABLE_Msk (0x1U << TUSB546_REG_DP_CTRL4_DP2_DISABLE_Pos) /*!< 0x04 */
#define TUSB546_REG_DP_CTRL4_DP2_DISABLE TUSB546_REG_DP_CTRL4_DP2_DISABLE_Msk /*!< DP Lane 2 disable */
#define TUSB546_REG_DP_CTRL4_DP3_DISABLE_Pos (3U)
#define TUSB546_REG_DP_CTRL4_DP3_DISABLE_Msk (0x1U << TUSB546_REG_DP_CTRL4_DP3_DISABLE_Pos) /*!< 0x08 */
#define TUSB546_REG_DP_CTRL4_DP3_DISABLE TUSB546_REG_DP_CTRL4_DP3_DISABLE_Msk /*!< DP Lane 3 disable */
#define TUSB546_REG_DP_CTRL4_AUX_SBU_OVR_Pos (4U)
#define TUSB546_REG_DP_CTRL4_AUX_SBU_OVR_Msk (0x3U << TUSB546_REG_DP_CTRL4_AUX_SBU_OVR_Pos) /*!< 0x30 */
#define TUSB546_REG_DP_CTRL4_AUX_SBU_OVR TUSB546_REG_DP_CTRL4_AUX_SBU_OVR_Msk /*!< AUX to SBU config */
#define TUSB546_REG_DP_CTRL4_AUX_SBU_OVR_0 (0x1 << TUSB546_REG_DP_CTRL4_AUX_SBU_OVR_Pos) /*!< 0x10 */
#define TUSB546_REG_DP_CTRL4_AUX_SBU_OVR_1 (0x2 << TUSB546_REG_DP_CTRL4_AUX_SBU_OVR_Pos) /*!< 0x20 */
#define TUSB546_REG_DP_CTRL4_SNOOP_DISABLE_Pos (7U)
#define TUSB546_REG_DP_CTRL4_SNOOP_DISABLE_Msk (0x1U << TUSB546_REG_DP_CTRL4_SNOOP_DISABLE_Pos) /*!< 0x80 */
#define TUSB546_REG_DP_CTRL4_SNOOP_DISABLE TUSB546_REG_DP_CTRL4_SNOOP_DISABLE_Msk /*!< AUX snoop disable */
/******************** Bit definition for USB3_CTRL1 register ****************/
#define TUSB546_REG_USB3_CTRL1_EQ1_SEL_Pos (0U)
#define TUSB546_REG_USB3_CTRL1_EQ1_SEL_Msk (0xFU << TUSB546_REG_USB3_CTRL1_EQ1_SEL_Pos) /*!< 0x0F */
#define TUSB546_REG_USB3_CTRL1_EQ1_SEL TUSB546_REG_USB3_CTRL1_EQ1_SEL_Msk /*!< Field selects between 0 to 11 dB of EQ for USB3.1 RX1 receiver */
#define TUSB546_REG_USB3_CTRL1_EQ1_SEL_0 (0x1 << TUSB546_REG_USB3_CTRL1_EQ1_SEL_Pos) /*!< 0x01 */
#define TUSB546_REG_USB3_CTRL1_EQ1_SEL_1 (0x2 << TUSB546_REG_USB3_CTRL1_EQ1_SEL_Pos) /*!< 0x02 */
#define TUSB546_REG_USB3_CTRL1_EQ1_SEL_2 (0x4 << TUSB546_REG_USB3_CTRL1_EQ1_SEL_Pos) /*!< 0x04 */
#define TUSB546_REG_USB3_CTRL1_EQ1_SEL_4 (0x8 << TUSB546_REG_USB3_CTRL1_EQ1_SEL_Pos) /*!< 0x08 */
#define TUSB546_REG_USB3_CTRL1_EQ2_SEL_Pos (4U)
#define TUSB546_REG_USB3_CTRL1_EQ2_SEL_Msk (0xFU << TUSB546_REG_USB3_CTRL1_EQ2_SEL_Pos) /*!< 0xF0 */
#define TUSB546_REG_USB3_CTRL1_EQ2_SEL TUSB546_REG_USB3_CTRL1_EQ2_SEL_Msk /*!< Field selects between 0 to 11 dB of EQ for USB3.1 RX2 receiver */
#define TUSB546_REG_USB3_CTRL1_EQ2_SEL_0 (0x1 << TUSB546_REG_USB3_CTRL1_EQ2_SEL_Pos) /*!< 0x10 */
#define TUSB546_REG_USB3_CTRL1_EQ2_SEL_1 (0x2 << TUSB546_REG_USB3_CTRL1_EQ2_SEL_Pos) /*!< 0x20 */
#define TUSB546_REG_USB3_CTRL1_EQ2_SEL_2 (0x4 << TUSB546_REG_USB3_CTRL1_EQ2_SEL_Pos) /*!< 0x40 */
#define TUSB546_REG_USB3_CTRL1_EQ2_SEL_4 (0x8 << TUSB546_REG_USB3_CTRL1_EQ2_SEL_Pos) /*!< 0x80 */
/******************** Bit definition for USB3_CTRL2 register ****************/
#define TUSB546_USB3_CTRL2_SSEQ_SEL_Pos (0U)
#define TUSB546_USB3_CTRL2_SSEQ_SEL_Msk (0xFU << TUSB546_USB3_CTRL2_SSEQ_SEL_Pos) /*!< 0x0F */
#define TUSB546_USB3_CTRL2_SSEQ_SEL TUSB546_USB3_CTRL2_SSEQ_SEL_Msk /*!< Field selects between 0 to 9 dB of EQ for USB3.1 SSTXP/N receiver */
#define TUSB546_USB3_CTRL2_SSEQ_SEL_0 (0x1 << TUSB546_USB3_CTRL2_SSEQ_SEL_Pos) /*!< 0x01 */
#define TUSB546_USB3_CTRL2_SSEQ_SEL_1 (0x2 << TUSB546_USB3_CTRL2_SSEQ_SEL_Pos) /*!< 0x02 */
#define TUSB546_USB3_CTRL2_SSEQ_SEL_2 (0x4 << TUSB546_USB3_CTRL2_SSEQ_SEL_Pos) /*!< 0x04 */
#define TUSB546_USB3_CTRL2_SSEQ_SEL_4 (0x8 << TUSB546_USB3_CTRL2_SSEQ_SEL_Pos) /*!< 0x08 */
/******************** Bit definition for USB3_CTRL3 register ****************/
#define TUSB546_REG_USB3_CTRL3_COMPLIANCE_Pos (0U)
#define TUSB546_REG_USB3_CTRL3_COMPLIANCE_Msk (0x3U << TUSB546_REG_USB3_CTRL3_COMPLIANCE_Pos) /*!< 0x03 */
#define TUSB546_REG_USB3_CTRL3_COMPLIANCE TUSB546_REG_USB3_CTRL3_COMPLIANCE_Msk /*!< Compliance mode */
#define TUSB546_REG_USB3_CTRL3_COMPLIANCE_0 (0x1 << TUSB546_REG_USB3_CTRL3_COMPLIANCE_Pos) /*!< 0x01 */
#define TUSB546_REG_USB3_CTRL3_COMPLIANCE_1 (0x2 << TUSB546_REG_USB3_CTRL3_COMPLIANCE_Pos) /*!< 0x02 */
#define TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL_Pos (2U)
#define TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL_Msk (0x3U << TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL_Pos) /*!< 0x0C */
#define TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL_Msk /*!< Rx.Detect interval for the Downstream facing port */
#define TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL_0 (0x1 << TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL_Pos) /*!< 0x04 */
#define TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL_1 (0x2 << TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL_Pos) /*!< 0x08 */
#define TUSB546_REG_USB3_CTRL3_DISABLE_U2U3_RXDET_Pos (4U)
#define TUSB546_REG_USB3_CTRL3_DISABLE_U2U3_RXDET_Msk (0x1U << TUSB546_REG_USB3_CTRL3_DISABLE_U2U3_RXDET_Pos) /*!< 0x10 */
#define TUSB546_REG_USB3_CTRL3_DISABLE_U2U3_RXDET TUSB546_REG_USB3_CTRL3_DISABLE_U2U3_RXDET_Msk /*!< Rx.Detect in U2/U3 disabled */
#define TUSB546_REG_USB3_CTRL3_U2U3_LFPS_DEBOUNCE_Pos (5U)
#define TUSB546_REG_USB3_CTRL3_U2U3_LFPS_DEBOUNCE_Msk (0x1U << TUSB546_REG_USB3_CTRL3_U2U3_LFPS_DEBOUNCE_Pos) /*!< 0x20 */
#define TUSB546_REG_USB3_CTRL3_U2U3_LFPS_DEBOUNCE TUSB546_REG_USB3_CTRL3_U2U3_LFPS_DEBOUNCE_Msk /*!< Debounce of LFPS before U2/U3 exit enabled */
#define TUSB546_REG_USB3_CTRL3_LFPS_EQ_Pos (6U)
#define TUSB546_REG_USB3_CTRL3_LFPS_EQ_Msk (0x1U << TUSB546_REG_USB3_CTRL3_LFPS_EQ_Pos) /*!< 0x40 */
#define TUSB546_REG_USB3_CTRL3_LFPS_EQ TUSB546_REG_USB3_CTRL3_LFPS_EQ_Msk /*!< EQ settings control */
#define TUSB546_REG_USB3_CM_ACTIVE_EQ_Pos (7U)
#define TUSB546_REG_USB3_CM_ACTIVE_EQ_Msk (0x1U << TUSB546_REG_USB3_CM_ACTIVE_EQ_Pos) /*!< 0x80 */
#define TUSB546_REG_USB3_CM_ACTIVE_EQ TUSB546_REG_USB3_CM_ACTIVE_EQ_Msk /*!< USB 3.1 compliance mode */
/** @defgroup TUSB546_MODE TUSB546 functioning mode
* @{
*/
#define TUSB546_MODE_DISABLED 0x0U
#define TUSB546_MODE_USB3_ONLY TUSB546_REG_CTRL_CTLSEL_0
#define TUSB546_MODE_FOUR_DPLANES TUSB546_REG_CTRL_CTLSEL_1
#define TUSB546_MODE_TWO_DPLANES_USB3 TUSB546_REG_CTRL_CTLSEL
/**
* @}
*/
/** @defgroup TUSB546_ORIENTATION TUSB546 Type-C Cable Orientation
* @{
*/
#define TUSB546_ORIENTATION_NORMAL 0x0U
#define TUSB546_ORIENTATION_FLIPPED TUSB546_REG_CTRL_FLIPSEL
/**
* @}
*/
/** @defgroup TUSB546_DPLANE DP Lane Identifier
* @{
*/
#define TUSB546_DPLANE_0 0x0U
#define TUSB546_DPLANE_1 0x2U
#define TUSB546_DPLANE_2 0x4U
#define TUSB546_DPLANE_3 0x8U
#define TUSB546_DPLANE_ALL 0xFU
/**
* @}
*/
/** @defgroup TUSB546_USBSIGNAL TUSB546 USB 3.1 signal identifier
* @{
*/
#define TUSB546_USBSIGNAL_RX1 0x0U
#define TUSB546_USBSIGNAL_RX2 0x1U
#define TUSB546_USBSIGNAL_SSTX 0x2U
/**
* @}
*/
/** @defgroup TUSB546_EQGAIN TUSB546 Equalizer Gain
* @{
.------------------------.-------------------------.-------------------------.------------------------.
| Equalization setting # | USB3.1 DFP EQ Gain (dB) | USB3.1 UFP EQ Gain (dB) | DISPLAYPORT LANES (dB) |
'------------------------'-------------------------'-------------------------'------------------------'
| 0 | 0.2 | -1.6 | 1.0 |
| 1 | 1.2 | -0.5 | 3.3 |
| 2 | 2.2 | 0.5 | 4.9 |
| 3 | 3.3 | 1.6 | 6.5 |
| 4 | 4.2 | 2.4 | 7.5 |
| 5 | 5.1 | 3.4 | 8.6 |
| 6 | 5.9 | 4.1 | 9.5 |
| 7 | 6.7 | 4.9 | 10.4 |
| 8 | 7.4 | 5.7 | 11.1 |
| 9 | 8.1 | 6.4 | 11.7 |
| 10 | 8.7 | 6.9 | 12.3 |
| 11 | 9.3 | 7.5 | 12.8 |
| 12 | 9.7 | 8.0 | 13.2 |
| 13 | 10.2 | 8.5 | 13.6 |
| 14 | 10.6 | 8.9 | 14.0 |
| 15 | 11.1 | 9.4 | 14.4 |
'------------------------'-------------------------'-------------------------'------------------------'
*/
#define TUSB546_EQGAIN_0 0x0U
#define TUSB546_EQGAIN_1 0x1U
#define TUSB546_EQGAIN_2 0x2U
#define TUSB546_EQGAIN_3 0x3U
#define TUSB546_EQGAIN_4 0x4U
#define TUSB546_EQGAIN_5 0x5U
#define TUSB546_EQGAIN_6 0x6U
#define TUSB546_EQGAIN_7 0x7U
#define TUSB546_EQGAIN_8 0x8U
#define TUSB546_EQGAIN_9 0x9U
#define TUSB546_EQGAIN_10 0xAU
#define TUSB546_EQGAIN_11 0xBU
#define TUSB546_EQGAIN_12 0xCU
#define TUSB546_EQGAIN_13 0xDU
#define TUSB546_EQGAIN_14 0xEU
#define TUSB546_EQGAIN_15 0xFU
/**
* @}
*/
/** @defgroup TUSB546_DPCDREG TUSB546 Display Port Configuration Data (DPCD) register identifier
* @{
*/
#define TUSB546_DPCDREG_LANE_COUNT_SET 0x0U
#define TUSB546_DPCDREG_SET_POWER 0x1U
/**
* @}
*/
/** @defgroup TUSB546_AUXTOSBU TUSB546 AUXp or AUXn to SBU1 or SBU2 connect/disconnect override
* @{
*/
#define TUSB546_AUXTOSBU_DEFAULT 0x0U
#define TUSB546_AUXTOSBU_OVERRIDE 0x1U
#define TUSB546_AUXTOSBU_OPEN 0x2U
/**
* @}
*/
/** @defgroup TUSB546_USB3_COMPLIANCEMODE USB 3.1 Compliance mode
* @{
*/
#define TUSB546_USB3_COMPLIANCEMODE_FSM 0x0U
#define TUSB546_USB3_COMPLIANCEMODE_DFP TUSB546_REG_USB3_CTRL3_COMPLIANCE_0
#define TUSB546_USB3_COMPLIANCEMODE_UFP TUSB546_REG_USB3_CTRL3_COMPLIANCE_1
#define TUSB546_USB3_COMPLIANCEMODE_DISABLED TUSB546_REG_USB3_CTRL3_COMPLIANCE
/**
* @}
*/
/** @defgroup TUSB546_RXDET_INTERVAL USB 3.1 Rx.Detect interval for the Downstream facing port (TX1P/N and TX2P/N)
* @{
*/
#define TUSB546_RXDET_INTERVAL_8MS 0x0U
#define TUSB546_RXDET_INTERVAL_12MS TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL_0
#define TUSB546_RXDET_INTERVAL_48MS TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL_1
#define TUSB546_RXDET_INTERVAL_96MS TUSB546_REG_USB3_CTRL3_DFP_RXDET_INTERVAL
/**
* @}
*/
/**
* @}
*/
#if defined(TUSB546_DEBUG)
/** @defgroup TUSB546_Exported_Structure TUSB546 Exported Structure
* @{
*/
typedef union {
uint8_t Register;
struct {
uint8_t CTLSEL:2;
uint8_t FLIPSEL:1;
uint8_t HPDIN_OVRRIDE:1;
uint8_t EQ_OVERRIDE:1;
uint8_t SWAP_HPDIN :1;
uint8_t Reserved:2;
};
} TUSB546_GeneralRegTypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t DP0EQ_SEL:4;
uint8_t DP1EQ_SEL:4;
};
} TUSB546_DPCtrlStatusReg10TypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t DP2EQ_SEL:4;
uint8_t DP3EQ_SEL:4;
};
} TUSB546_DPCtrlStatusReg11TypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t LANE_COUNT_SET :5;
uint8_t SET_POWER_STATE :2;
uint8_t Reserved :1;
};
} TUSB546_DPCtrlStatusReg12TypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t DP0_DISABLE :1;
uint8_t DP1_DISABLE :1;
uint8_t DP2_DISABLE :1;
uint8_t DP3_DISABLE :1;
uint8_t AUX_SBU_OVR :2;
uint8_t Reserved :1;
uint8_t AUX_SNOOP_DISABLE :1;
};
} TUSB546_DPCtrlStatusReg13TypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t Reserved :8;
};
} TUSB546_USBCtrlStatusReg20TypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t Reserved :8;
};
} TUSB546_USBCtrlStatusReg21TypeDef;
typedef union {
uint8_t Register;
struct {
uint8_t Reserved :8;
};
} TUSB546_USBCtrlStatusReg22TypeDef;
typedef struct
{
TUSB546_GeneralRegTypeDef General; /*!< General Registers (0x0A) */
TUSB546_DPCtrlStatusReg10TypeDef DPCtrlStatus10; /*!< DisplayPort Control/Status Registers (0x10)*/
TUSB546_DPCtrlStatusReg11TypeDef DPCtrlStatus11; /*!< DisplayPort Control/Status Registers (0x11)*/
TUSB546_DPCtrlStatusReg12TypeDef DPCtrlStatus12; /*!< DisplayPort Control/Status Registers (0x12) */
TUSB546_DPCtrlStatusReg13TypeDef DPCtrlStatus13; /*!< DisplayPort Control/Status Registers (0x13) */
TUSB546_USBCtrlStatusReg20TypeDef USBCtrlStatus20;/*!< USB3.1 Control/Status Registers (0x20) */
TUSB546_USBCtrlStatusReg21TypeDef USBCtrlStatus21;/*!< USB3.1 Control/Status Registers (0x21) */
TUSB546_USBCtrlStatusReg22TypeDef USBCtrlStatus22;/*!< USB3.1 Control/Status Registers (0x22) */
} TUSB546_RegistersTypeDef;
/**
* @}
*/
#endif /* TUSB546_DEBUG */
/** @defgroup TUSB546_Exported_Functions
* @{
*/
/* USB Type-C cross switch management functions */
uint32_t tusb546_CrossSwitch_Init(uint16_t Address);
void tusb546_CrossSwitch_DeInit(uint16_t Address);
uint32_t tusb546_CrossSwitch_PowerOn(uint16_t Address);
uint32_t tusb546_CrossSwitch_PowerOff(uint16_t Address);
uint32_t tusb546_CrossSwitch_SetMode(uint16_t Address, TYPECSWITCH_Mode_t Mode);
uint32_t tusb546_CrossSwitch_IsSupportedMode(TYPECSWITCH_Mode_t Mode);
/* DisplayPort Linear Redriver management functions */
uint32_t tusb546_DPRedriver_Init(uint16_t Address);
void tusb546_DPRedriver_DeInit(uint16_t Address);
uint32_t tusb546_DPRedriver_PowerOn(uint16_t Address);
uint32_t tusb546_DPRedriver_PowerOff(uint16_t Address);
uint32_t tusb546_DPRedriver_SetEQGain(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId, uint8_t EQGain);
uint32_t tusb546_DPRedriver_EnableChannel(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId);
uint32_t tusb546_DPRedriver_DisableChannel(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId);
/* MUX IO functions */
uint8_t MUX_IO_Init(void);
void MUX_IO_DeInit(void);
uint8_t MUX_IO_Write(uint16_t Addr, uint16_t Reg, uint8_t Data);
uint8_t MUX_IO_Read(uint16_t Addr, uint16_t Reg, uint8_t *pData);
uint32_t MUX_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials);
/**
* @}
*/
/** @defgroup TUSB546_Exported_Variables
* @{
*/
/* USB Type-C crossbar switch driver structure */
extern TYPECSWITCH_Drv_t tusb546_drv_CrossSwitch;
/* Displayport Linear Redriver driver structure */
extern DPREDRIVER_Drv_t tusb546_drv_LinearRedriver;
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* TUSB546_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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# Copyright (c) 2020 STMicroelectronics
This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this software except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).

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<h1 id="release-notes-for-stm32g0c1e-ev-board-drivers">Release Notes for <mark>STM32G0C1E-EV Board drivers</mark></h1>
<p>Copyright © 2020 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
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<h1 id="license">License</h1>
<p>This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:</p>
<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
<h1 id="purpose">Purpose</h1>
<p>This driver provides a set of functions to manage:</p>
<ul>
<li>LEDs, Buttons, SD card, temperature sensor, LCD, MUX and PWR on STM32G0C1E-EV board from STMicroelectronics</li>
</ul>
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<h1 id="update-history">Update History</h1>
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<input type="checkbox" id="collapse-section1" checked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0.RC1 / 13-October-2020</label>
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<h2 id="main-changes">Main Changes</h2>
<h3 id="first-release">First release</h3>
<h2 id="contents">Contents</h2>
<p>First official release of STM32G0C1E-EV board drivers for STM32Cube G0 FW package.</p>
<h2 id="supported-devices-and-boards">Supported Devices and Boards</h2>
<ul>
<li>STM32G0C1xx/B1xx devices</li>
<li>STM32G0C1E-EV mother board (<strong>MB1581B</strong>)</li>
<li>“Legacy” daughter board (MB1351A)</li>
<li>USBPD daughter board (MB1352C)</li>
</ul>
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<p>For complete documentation on STM32G0xx, visit: [<a href="http://www.st.com/stm32g0">www.st.com/stm32g0</a>]</p>
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/**
******************************************************************************
* @file stm32g0c1e_eval.h
* @author MCD Application Team
* @brief This file contains definitions for STM32G0C1E-EV's Leds, push-buttons
* and COM port hardware resources.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0C1E_EVAL_H
#define STM32G0C1E_EVAL_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup BSP
* @{
*/
/** @defgroup STM32G0C1E_EVAL STM32G0C1E EVAL
* @{
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal.h"
#include <stdio.h>
/** @defgroup STM32G0C1E_EVAL_Common STM32G0C1E EVAL Common
* @{
*/
/** @defgroup STM32G0C1E_EVAL_Private_Constants Private Constants
* @{
*/
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_Private_Variables Private Variables
* @{
*/
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_Exported_Types Exported Types
* @{
*/
/**
* @brief LED Types Definition
*/
typedef enum
{
LED1 = 0,
LED2 = 1,
LED3 = 2,
LED4 = 3,
/* Color led aliases */
LED_GREEN = LED1,
LED_ORANGE = LED2,
LED_RED = LED3,
LED_BLUE = LED4
} Led_TypeDef;
/**
* @brief BUTTON Types Definition
*/
typedef enum
{
BUTTON_TAMPER = 0
} Button_TypeDef;
typedef enum
{
BUTTON_MODE_GPIO = 0,
BUTTON_MODE_EXTI = 1
} ButtonMode_TypeDef;
/**
* @brief JOYSTICK Types Definition
*/
typedef enum
{
JOY_SEL = 0,
JOY_DOWN = 1,
JOY_LEFT = 2,
JOY_RIGHT = 3,
JOY_UP = 4,
JOY_NONE = 5
} JOYState_TypeDef;
typedef enum
{
JOY_MODE_GPIO = 0,
JOY_MODE_EXTI = 1
} JOYMode_TypeDef;
/**
* @brief COM Types Definition
*/
typedef enum
{
COM1 = 0
} COM_TypeDef;
/**
* @brief Daughter Board (DB) Types Definition
*/
typedef enum
{
DB_ID_NONE = 0,
DB_ID_LEGACY,
DB_ID_UCPD_AB,
DB_ID_UCPD_C
} DBId_TypeDef;
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_Exported_Constants Exported Constants
* @{
*/
/**
* @brief Define for STM32G0C1E_EVAL board
*/
#define EVAL_BOARD_REVISION ((uint8_t *)"REV. B")
/** @defgroup STM32G0C1E_EV_LED STM32G0C1E-EV LED
* @{
*/
#define LEDn 4
#define LED1_PIN GPIO_PIN_5 /* PD.05 */
#define LED1_GPIO_PORT GPIOD
#define LED1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
#define LED1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
#define LED2_PIN GPIO_PIN_6 /* PD.06 */
#define LED2_GPIO_PORT GPIOD
#define LED2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
#define LED2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
#define LED3_PIN GPIO_PIN_8 /* PD.08 */
#define LED3_GPIO_PORT GPIOD
#define LED3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
#define LED3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
#define LED4_PIN GPIO_PIN_9 /* PD.09 */
#define LED4_GPIO_PORT GPIOD
#define LED4_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
#define LED4_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
#define LEDx_GPIO_CLK_ENABLE(__LED__) do { if((__LED__) == LED1) LED1_GPIO_CLK_ENABLE(); else \
if((__LED__) == LED2) LED2_GPIO_CLK_ENABLE(); else \
if((__LED__) == LED3) LED3_GPIO_CLK_ENABLE(); else \
if((__LED__) == LED4) LED4_GPIO_CLK_ENABLE();} while(0)
#define LEDx_GPIO_CLK_DISABLE(__LED__) (((__LED__) == LED1) ? LED1_GPIO_CLK_DISABLE() :\
((__LED__) == LED2) ? LED2_GPIO_CLK_DISABLE() :\
((__LED__) == LED3) ? LED3_GPIO_CLK_DISABLE() :\
((__LED__) == LED4) ? LED4_GPIO_CLK_DISABLE() : 0 )
/**
* @}
*/
/** @defgroup STM32G0C1E_EV_BUTTON STM32G0C1E-EV BUTTON
* @{
*/
#define JOYn 5
#define BUTTONn 1
/**
* @brief Tamper push-button
*/
#define TAMPER_BUTTON_PIN GPIO_PIN_13 /* PC.13 */
#define TAMPER_BUTTON_GPIO_PORT GPIOC
#define TAMPER_BUTTON_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define TAMPER_BUTTON_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
#define TAMPER_BUTTON_EXTI_IRQn EXTI4_15_IRQn
#define TAMPERx_GPIO_CLK_ENABLE(__BUTTON__) do { if((__BUTTON__) == BUTTON_TAMPER) TAMPER_BUTTON_GPIO_CLK_ENABLE();} while(0)
#define TAMPERx_GPIO_CLK_DISABLE(__BUTTON__) (((__BUTTON__) == BUTTON_TAMPER) ? TAMPER_BUTTON_GPIO_CLK_DISABLE(): 0 )
/**
* @brief Joystick Right push-button
*/
#define RIGHT_JOY_PIN GPIO_PIN_7 /* PC.07 */
#define RIGHT_JOY_GPIO_PORT GPIOC
#define RIGHT_JOY_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define RIGHT_JOY_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
#define RIGHT_JOY_EXTI_IRQn EXTI4_15_IRQn
/**
* @brief Joystick Left push-button
*/
#define LEFT_JOY_PIN GPIO_PIN_8 /* PC.08 */
#define LEFT_JOY_EXTI_IRQn EXTI4_15_IRQn
#define LEFT_JOY_GPIO_PORT GPIOC
#define LEFT_JOY_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define LEFT_JOY_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
/**
* @brief Joystick Up push-button
*/
#define UP_JOY_PIN GPIO_PIN_2 /* PC.02 */
#define UP_JOY_GPIO_PORT GPIOC
#define UP_JOY_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define UP_JOY_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
#define UP_JOY_EXTI_IRQn EXTI2_3_IRQn
/**
* @brief Joystick Down push-button
*/
#define DOWN_JOY_PIN GPIO_PIN_3 /* PC.03 */
#define DOWN_JOY_EXTI_IRQn EXTI2_3_IRQn
#define DOWN_JOY_GPIO_PORT GPIOC
#define DOWN_JOY_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define DOWN_JOY_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
/**
* @brief Joystick Sel push-button
*/
#define SEL_JOY_PIN GPIO_PIN_0 /* PA.00 */
#define SEL_JOY_GPIO_PORT GPIOA
#define SEL_JOY_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define SEL_JOY_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define SEL_JOY_EXTI_IRQn EXTI0_1_IRQn
#define JOYx_GPIO_CLK_ENABLE(__JOY__) do { if((__JOY__) == JOY_SEL) SEL_JOY_GPIO_CLK_ENABLE(); else \
if((__JOY__) == JOY_DOWN) DOWN_JOY_GPIO_CLK_ENABLE(); else \
if((__JOY__) == JOY_LEFT) LEFT_JOY_GPIO_CLK_ENABLE(); else \
if((__JOY__) == JOY_RIGHT) RIGHT_JOY_GPIO_CLK_ENABLE(); else \
if((__JOY__) == JOY_UP) UP_JOY_GPIO_CLK_ENABLE();} while(0)
#define JOYx_GPIO_CLK_DISABLE(__JOY__) (((__JOY__) == JOY_SEL) ? SEL_JOY_GPIO_CLK_DISABLE() :\
((__JOY__) == JOY_DOWN) ? DOWN_JOY_GPIO_CLK_DISABLE() :\
((__JOY__) == JOY_LEFT) ? LEFT_JOY_GPIO_CLK_DISABLE() :\
((__JOY__) == JOY_RIGHT) ? RIGHT_JOY_GPIO_CLK_DISABLE() :\
((__JOY__) == JOY_UP) ? UP_JOY_GPIO_CLK_DISABLE() : 0 )
/**
* @}
*/
/** @defgroup STM32G0C1E_EV_COM STM32G0C1E-EV COM
* @{
*/
#define COMn 1
/**
* @brief Definition for COM port1, connected to USART1
*/
#define EVAL_COM1 USART1
#define EVAL_COM1_CLK_ENABLE() __HAL_RCC_USART1_CLK_ENABLE()
#define EVAL_COM1_CLK_DISABLE() __HAL_RCC_USART1_CLK_DISABLE()
#define EVAL_COM1_TX_PIN GPIO_PIN_4 /* PC.04 */
#define EVAL_COM1_TX_GPIO_PORT GPIOC
#define EVAL_COM1_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define EVAL_COM1_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
#define EVAL_COM1_TX_AF GPIO_AF1_USART1
#define EVAL_COM1_RX_PIN GPIO_PIN_5 /* PC.05 */
#define EVAL_COM1_RX_GPIO_PORT GPIOC
#define EVAL_COM1_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define EVAL_COM1_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
#define EVAL_COM1_RX_AF GPIO_AF1_USART1
#define EVAL_COM1_CTS_PIN GPIO_PIN_11 /* PA.11 */
#define EVAL_COM1_CTS_GPIO_PORT GPIOA
#define EVAL_COM1_CTS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define EVAL_COM1_CTS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define EVAL_COM1_CTS_AF GPIO_AF1_USART1
#define EVAL_COM1_RTS_PIN GPIO_PIN_12 /* PA.12 */
#define EVAL_COM1_RTS_GPIO_PORT GPIOA
#define EVAL_COM1_RTS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define EVAL_COM1_RTS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define EVAL_COM1_RTS_AF GPIO_AF1_USART1
#define EVAL_COM1_IRQn USART1_IRQn
#define COMx_CLK_ENABLE(__COM__) do { if((__COM__) == COM1) EVAL_COM1_CLK_ENABLE();} while(0)
#define COMx_CLK_DISABLE(__COM__) (((__COM__) == COM1) ? EVAL_COM1_CLK_DISABLE() : 0)
#define COMx_TX_GPIO_CLK_ENABLE(__COM__) do { if((__COM__) == COM1) EVAL_COM1_TX_GPIO_CLK_ENABLE();} while(0)
#define COMx_TX_GPIO_CLK_DISABLE(__COM__) (((__COM__) == COM1) ? EVAL_COM1_TX_GPIO_CLK_DISABLE() : 0)
#define COMx_RX_GPIO_CLK_ENABLE(__COM__) do { if((__COM__) == COM1) EVAL_COM1_RX_GPIO_CLK_ENABLE();} while(0)
#define COMx_RX_GPIO_CLK_DISABLE(__COM__) (((__COM__) == COM1) ? EVAL_COM1_RX_GPIO_CLK_DISABLE() : 0)
#define COMx_CTS_GPIO_CLK_ENABLE(__COM__) do { if((__COM__) == COM1) EVAL_COM1_CTS_GPIO_CLK_ENABLE();} while(0)
#define COMx_CTS_GPIO_CLK_DISABLE(__COM__) (((__COM__) == COM1) ? EVAL_COM1_CTS_GPIO_CLK_DISABLE() : 0)
#define COMx_RTS_GPIO_CLK_ENABLE(__COM__) do { if((__COM__) == COM1) EVAL_COM1_RTS_GPIO_CLK_ENABLE();} while(0)
#define COMx_RTS_GPIO_CLK_DISABLE(__COM__) (((__COM__) == COM1) ? EVAL_COM1_RTS_GPIO_CLK_DISABLE() : 0)
#if defined(HAL_I2C_MODULE_ENABLED)
/*##################### I2Cx ###################################*/
/* User can use this section to tailor I2Cx instance used and associated resources */
/* Definition for I2C1 Pins */
#define EVAL_I2C1 I2C1
#define EVAL_I2C1_CLK_ENABLE() __HAL_RCC_I2C1_CLK_ENABLE()
#define EVAL_I2C1_CLK_DISABLE() __HAL_RCC_I2C1_CLK_DISABLE()
#define EVAL_I2C1_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
#define EVAL_I2C1_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
#define EVAL_I2C1_SCL_PIN GPIO_PIN_6 /* PB.6 */
#define EVAL_I2C1_SDA_PIN GPIO_PIN_7 /* PB.7 */
#define EVAL_I2C1_GPIO_PORT GPIOB /* GPIOB */
#define EVAL_I2C1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define EVAL_I2C1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
#define EVAL_I2C1_SCL_SDA_AF GPIO_AF6_I2C1
/* Definition for I2C2 Pins */
#define EVAL_I2C2 I2C2
#define EVAL_I2C2_CLK_ENABLE() __HAL_RCC_I2C2_CLK_ENABLE()
#define EVAL_I2C2_CLK_DISABLE() __HAL_RCC_I2C2_CLK_DISABLE()
#define EVAL_I2C2_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
#define EVAL_I2C2_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
#define EVAL_I2C2_SCL_PIN GPIO_PIN_13 /* PB.13 */
#define EVAL_I2C2_SDA_PIN GPIO_PIN_14 /* PB.14 */
#define EVAL_I2C2_GPIO_PORT GPIOB /* GPIOB */
#define EVAL_I2C2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define EVAL_I2C2_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
#define EVAL_I2C2_AF GPIO_AF6_I2C2
/* Definition for I2C2 NVIC */
#define EVAL_I2C2_IRQn I2C2_IRQn
/* Maximum Timeout values for flags waiting loops. These timeouts are not based
on accurate values, they just guarantee that the application will not remain
stuck if the I2C communication is corrupted.
You may modify these timeout values depending on CPU frequency and application
conditions (interrupts routines ...). */
#define EVAL_I2C1_TIMEOUT_MAX 1000
#define EVAL_I2C2_TIMEOUT_MAX 1000
/* I2C TIMING is calculated in case of the I2C Clock source is the SYSCLK = 48 MHz */
/* Set TIMING to 0x00E0D3FF to reach 100 KHz speed (Rise time = 50ns, Fall time = 10ns) */
#define I2C2_TIMING 0x00E0D3FF
#define I2C1_TIMING 0x00E0D3FF
/* MUX 1 - USB Type-C Crossbar Switch I2C address (0b1000100x) */
#define MUX_1_TYPEC_SWITCH_I2C_ADDRESS 0x88U
/* MUX 1 - DisplayPort Linear Redriver I2C address (0b1000100x) */
#define MUX_1_DP_REDRIVER_I2C_ADDRESS 0x88U
/* MUX 2 - USB Type-C Crossbar Switch I2C address (0b0110000x) */
#define MUX_2_TYPEC_SWITCH_I2C_ADDRESS 0x60U
/* MUX 2 - DisplayPort Linear Redriver I2C address (0b0000000x) */
#define MUX_2_DP_REDRIVER_I2C_ADDRESS 0x00U
#endif /* HAL_I2C_MODULE_ENABLED */
#if defined(HAL_SPI_MODULE_ENABLED)
/**
* @brief Definition for SPI Interface pins (SPI1 used)
*/
#define EVAL_SPIx SPI1
#define EVAL_SPIx_CLK_ENABLE() __HAL_RCC_SPI1_CLK_ENABLE()
#define EVAL_SPIx_CLK_DISABLE() __HAL_RCC_SPI1_CLK_DISABLE()
#define EVAL_SPIx_FORCE_RESET() __HAL_RCC_SPI1_FORCE_RESET()
#define EVAL_SPIx_RELEASE_RESET() __HAL_RCC_SPI1_RELEASE_RESET()
#define EVAL_SPIx_SCK_PIN GPIO_PIN_3 /* PB.03 */
#define EVAL_SPIx_SCK_GPIO_PORT GPIOB /* GPIOB */
#define EVAL_SPIx_SCK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define EVAL_SPIx_SCK_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
#define EVAL_SPIx_SCK_AF GPIO_AF0_SPI1
#define EVAL_SPIx_MISO_PIN GPIO_PIN_4 /* PB.04 */
#define EVAL_SPIx_MISO_GPIO_PORT GPIOB /* GPIOB */
#define EVAL_SPIx_MISO_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define EVAL_SPIx_MISO_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
#define EVAL_SPIx_MISO_AF GPIO_AF0_SPI1
#define EVAL_SPIx_MOSI_PIN GPIO_PIN_7 /* PA.07 */
#define EVAL_SPIx_MOSI_GPIO_PORT GPIOA /* GPIOA */
#define EVAL_SPIx_MOSI_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define EVAL_SPIx_MOSI_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
#define EVAL_SPIx_MOSI_AF GPIO_AF0_SPI1
#define EVAL_SPIx_MOSI_DIR_PIN GPIO_PIN_12 /* PC.12 */
#define EVAL_SPIx_MOSI_DIR_GPIO_PORT GPIOC /* GPIOC */
#define EVAL_SPIx_MOSI_DIR_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define EVAL_SPIx_MOSI_DIR_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
/* Maximum Timeout values for flags waiting loops. These timeouts are not based
on accurate values, they just guarantee that the application will not remain
stuck if the SPI communication is corrupted.
You may modify these timeout values depending on CPU frequency and application
conditions (interrupts routines ...). */
#define EVAL_SPIx_TIMEOUT_MAX 1000
#endif /* HAL_SPI_MODULE_ENABLED */
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_COMPONENT STM32G0C1E_EVAL COMPONENT
* @{
*/
/*##################### LCD ###################################*/
/* Chip Select macro definition */
#define LCD_CS_LOW() HAL_GPIO_WritePin(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, GPIO_PIN_RESET)
#define LCD_CS_HIGH() HAL_GPIO_WritePin(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, GPIO_PIN_SET)
/**
* @brief LCD Control pins
*/
#define LCD_NCS_PIN GPIO_PIN_8 /* PB. 08*/
#define LCD_NCS_GPIO_PORT GPIOB /* GPIOB */
#define LCD_NCS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define LCD_NCS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
/*##################### SD ###################################*/
/* Chip Select macro definition */
#define SD_CS_LOW() HAL_GPIO_WritePin(SD_CS_GPIO_PORT, SD_CS_PIN, GPIO_PIN_RESET)
#define SD_CS_HIGH() HAL_GPIO_WritePin(SD_CS_GPIO_PORT, SD_CS_PIN, GPIO_PIN_SET)
/**
* @brief SD card Control pin
*/
#define SD_CS_PIN GPIO_PIN_1 /* PD.01 */
#define SD_CS_GPIO_PORT GPIOD /* GPIOD */
#define SD_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
#define SD_CS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
/**
* @brief SD Detect Interface pins
*/
#define SD_DETECT_PIN GPIO_PIN_9 /* PC.09 */
#define SD_DETECT_GPIO_PORT GPIOC /* GPIOC */
#define SD_DETECT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define SD_DETECT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
#define SD_DETECT_EXTI_IRQn EXTI4_15_IRQn
/*##################### HDMI-CEC ###################################*/
/**
* @brief I2C HDMI CEC Interface pins
*/
#define HDMI_CEC_HPD_SINK_PIN GPIO_PIN_2 /* PD.02 */
#define HDMI_CEC_HPD_SINK_GPIO_PORT GPIOD
#define HDMI_CEC_HPD_SINK_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
#define HDMI_CEC_HPD_SINK_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
#define HDMI_CEC_HPD_SOURCE_PIN GPIO_PIN_6 /* PC.06 */
#define HDMI_CEC_HPD_SOURCE_GPIO_PORT GPIOC
#define HDMI_CEC_HPD_SOURCE_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define HDMI_CEC_HPD_SOURCE_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
#define HDMI_CEC_LINE_PIN GPIO_PIN_10 /* PB.10 */
#define HDMI_CEC_LINE_GPIO_PORT GPIOB
#define HDMI_CEC_LINE_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define HDMI_CEC_LINE_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
#define HDMI_CEC_LINE_AF GPIO_AF0_CEC
#define HDMI_CEC_IRQn CEC_IRQn
/* HDMI-CEC hardware I2C address */
#define HDMI_CEC_I2C_ADDRESS 0xA0
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_DB STM32G0C1E_EVAL DAUGHTER BOARD
* @{
*/
#if defined(HAL_ADC_MODULE_ENABLED)
/**
* @brief Daughter Board detection pin
*/
#define DB_DETECT_PIN GPIO_PIN_11 /* PB.11 */
#define DB_DETECT_GPIO_PORT GPIOB /* GPIOB */
#define DB_DETECT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define DB_DETECT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
#define DB_ADC ADC1
#define DB_ADC_CLK_ENABLE() __HAL_RCC_ADC_CLK_ENABLE();
#define DB_ADC_CLK_DISABLE() __HAL_RCC_ADC_CLK_DISABLE();
#define DB_ADC_CHANNEL ADC_CHANNEL_15
#endif /* HAL_ADC_MODULE_ENABLED*/
/**
* @}
*/
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_Exported_Functions Exported Functions
* @{
*/
uint32_t BSP_GetVersion(void);
#if defined(_GUI_INTERFACE)
const uint8_t* BSP_GetHWBoardVersionName(void);
const uint8_t* BSP_GetPDTypeName(void);
#endif /* _GUI_INTERFACE */
void BSP_LED_Init(Led_TypeDef Led);
void BSP_LED_DeInit(Led_TypeDef Led);
void BSP_LED_On(Led_TypeDef Led);
void BSP_LED_Off(Led_TypeDef Led);
void BSP_LED_Toggle(Led_TypeDef Led);
void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
uint32_t BSP_PB_GetState(Button_TypeDef Button);
uint8_t BSP_JOY_Init(JOYMode_TypeDef Joy_Mode);
void BSP_JOY_DeInit(void);
JOYState_TypeDef BSP_JOY_GetState(void);
#if defined(HAL_UART_MODULE_ENABLED)
void BSP_COM_Init(COM_TypeDef COM, UART_HandleTypeDef* huart);
#endif /* HAL_UART_MODULE_ENABLED */
#if defined(HAL_ADC_MODULE_ENABLED)
uint8_t BSP_DB_GetId(DBId_TypeDef *pDaughterBoardId);
#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0C1E_EVAL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0c1e_eval_lcd.c
* @author MCD Application Team
* @brief This file includes the driver for Liquid Crystal Display modules
* mounted on STM32G0C1E-EV evaluation board.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) This driver is used to drive indirectly an LCD TFT.
(#) This driver supports AM240320LGTNQW00H (HX8347D) LCD mounted on MB895 daughter board
(#) The HX8347D components driver MUST be included with this driver.
(#) Initialization steps:
(++) Initialize the LCD using the LCD_Init() function.
(#) Display on LCD
(++) Clear the whole LCD using the LCD_Clear() function or only one specified
string line using the LCD_ClearStringLine() function.
(++) Display a character on the specified line and column using the LCD_DisplayChar()
function or a complete string line using the LCD_DisplayStringAtLine() function.
(++) Display a string line on the specified position (x,y in pixel) and align mode
using the LCD_DisplayStringAtLine() function.
(++) Draw and fill a basic shapes (dot, line, rectangle, circle, ellipse, .. bitmap)
on LCD using a set of functions.
@endverbatim
*/
/*----------------------------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g0c1e_eval_lcd.h"
#include "../../../Utilities/Fonts/fonts.h"
#include "../../../Utilities/Fonts/font24.c"
#include "../../../Utilities/Fonts/font20.c"
#include "../../../Utilities/Fonts/font16.c"
#include "../../../Utilities/Fonts/font12.c"
#include "../../../Utilities/Fonts/font8.c"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM32G0C1E_EVAL
* @{
*/
/** @addtogroup STM32G0C1E_EVAL_LCD
* @{
*/
/** @defgroup STM32G0C1E_EVAL_LCD_Private_Constants Private Constants
* @{
*/
#define POLY_X(Z) ((int32_t)((pPoints + (Z))->X))
#define POLY_Y(Z) ((int32_t)((pPoints + (Z))->Y))
#define MAX_HEIGHT_FONT 17
#define MAX_WIDTH_FONT 24
#define OFFSET_BITMAP 54
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_LCD_Private_Macros Private Macros
* @{
*/
#define ABS(X) ((X) > 0 ? (X) : -(X))
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_LCD_Private_Variables Private Variables
* @{
*/
LCD_DrawPropTypeDef DrawProp;
static LCD_DrvTypeDef *lcd_drv;
/* Max size of bitmap will based on a font24 (17x24) */
static uint8_t bitmap[MAX_HEIGHT_FONT*MAX_WIDTH_FONT*2+OFFSET_BITMAP] = {0};
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_LCD_Private_Functions Private Functions
* @{
*/
static void LCD_DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *pChar);
static void LCD_SetDisplayWindow(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
/**
* @}
*/
/** @addtogroup STM32G0C1E_EVAL_LCD_Exported_Functions
* @{
*/
/**
* @brief Initializes the LCD.
* @retval LCD state
*/
uint8_t BSP_LCD_Init(void)
{
/* Default value for draw propriety */
DrawProp.BackColor = 0xFFFF;
DrawProp.pFont = &LCD_DEFAULT_FONT;
DrawProp.TextColor = 0x0000;
/*HX8347D_ID connected*/
lcd_drv = &hx8347d_drv;
/* LCD Init */
lcd_drv->Init();
/* Initialize the font */
BSP_LCD_SetFont(&LCD_DEFAULT_FONT);
return LCD_OK;
}
/**
* @brief Gets the LCD X size.
* @retval Used LCD X size
*/
uint32_t BSP_LCD_GetXSize(void)
{
return(lcd_drv->GetLcdPixelWidth());
}
/**
* @brief Gets the LCD Y size.
* @retval Used LCD Y size
*/
uint32_t BSP_LCD_GetYSize(void)
{
return(lcd_drv->GetLcdPixelHeight());
}
/**
* @brief Gets the LCD text color.
* @retval Used text color.
*/
uint16_t BSP_LCD_GetTextColor(void)
{
return DrawProp.TextColor;
}
/**
* @brief Gets the LCD background color.
* @retval Used background color
*/
uint16_t BSP_LCD_GetBackColor(void)
{
return DrawProp.BackColor;
}
/**
* @brief Sets the LCD text color.
* @param Color: Text color code RGB(5-6-5)
* @retval None
*/
void BSP_LCD_SetTextColor(uint16_t Color)
{
DrawProp.TextColor = Color;
}
/**
* @brief Sets the LCD background color.
* @param Color: Background color code RGB(5-6-5)
* @retval None
*/
void BSP_LCD_SetBackColor(uint16_t Color)
{
DrawProp.BackColor = Color;
}
/**
* @brief Sets the LCD text font.
* @param pFonts: Font to be used
* @retval None
*/
void BSP_LCD_SetFont(sFONT *pFonts)
{
DrawProp.pFont = pFonts;
}
/**
* @brief Gets the LCD text font.
* @retval Used font
*/
sFONT *BSP_LCD_GetFont(void)
{
return DrawProp.pFont;
}
/**
* @brief Clears the whole LCD.
* @param Color: Color of the background
* @retval None
*/
void BSP_LCD_Clear(uint16_t Color)
{
uint32_t counter = 0;
uint32_t color_backup = DrawProp.TextColor;
DrawProp.TextColor = Color;
for(counter = 0; counter < BSP_LCD_GetYSize(); counter++)
{
BSP_LCD_DrawHLine(0, counter, BSP_LCD_GetXSize());
}
DrawProp.TextColor = color_backup;
BSP_LCD_SetTextColor(DrawProp.TextColor);
}
/**
* @brief Clears the selected line.
* @param Line: Line to be cleared
* This parameter can be one of the following values:
* @arg 0..9: if the Current fonts is Font16x24
* @arg 0..19: if the Current fonts is Font12x12 or Font8x12
* @arg 0..29: if the Current fonts is Font8x8
* @retval None
*/
void BSP_LCD_ClearStringLine(uint16_t Line)
{
uint32_t colorbackup = DrawProp.TextColor;
DrawProp.TextColor = DrawProp.BackColor;;
/* Draw a rectangle with background color */
BSP_LCD_FillRect(0, (Line * DrawProp.pFont->Height), BSP_LCD_GetXSize(), DrawProp.pFont->Height);
DrawProp.TextColor = colorbackup;
BSP_LCD_SetTextColor(DrawProp.TextColor);
}
/**
* @brief Displays one character.
* @param Xpos: Start column address
* @param Ypos: Line where to display the character shape.
* @param Ascii: Character ascii code
* This parameter must be a number between Min_Data = 0x20 and Max_Data = 0x7E
* @retval None
*/
void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii)
{
LCD_DrawChar(Ypos, Xpos, &DrawProp.pFont->table[(Ascii-' ') *\
DrawProp.pFont->Height * ((DrawProp.pFont->Width + 7) / 8)]);
}
/**
* @brief Displays characters on the LCD.
* @param Xpos: X position (in pixel)
* @param Ypos: Y position (in pixel)
* @param pText: Pointer to string to display on LCD
* @param Mode: Display mode
* This parameter can be one of the following values:
* @arg CENTER_MODE
* @arg RIGHT_MODE
* @arg LEFT_MODE
* @retval None
*/
void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *pText, Line_ModeTypdef Mode)
{
uint16_t refcolumn = 1, counter = 0;
uint32_t size = 0, ysize = 0;
uint8_t *ptr = pText;
/* Get the text size */
while (*ptr++) size ++ ;
/* Characters number per line */
ysize = (BSP_LCD_GetXSize()/DrawProp.pFont->Width);
switch (Mode)
{
case CENTER_MODE:
{
refcolumn = Xpos + ((ysize - size)* DrawProp.pFont->Width) / 2;
break;
}
case LEFT_MODE:
{
refcolumn = Xpos;
break;
}
case RIGHT_MODE:
{
refcolumn = Xpos + ((ysize - size)*DrawProp.pFont->Width);
break;
}
default:
{
refcolumn = Xpos;
break;
}
}
/* Send the string character by character on lCD */
while ((*pText != 0) & (((BSP_LCD_GetXSize() - (counter*DrawProp.pFont->Width)) & 0xFFFF) >= DrawProp.pFont->Width))
{
/* Display one character on LCD */
BSP_LCD_DisplayChar(refcolumn, Ypos, *pText);
/* Decrement the column position by 16 */
refcolumn += DrawProp.pFont->Width;
/* Point on the next character */
pText++;
counter++;
}
}
/**
* @brief Displays a character on the LCD.
* @param Line: Line where to display the character shape
* This parameter can be one of the following values:
* @arg 0..9: if the Current fonts is Font16x24
* @arg 0..19: if the Current fonts is Font12x12 or Font8x12
* @arg 0..29: if the Current fonts is Font8x8
* @param pText: Pointer to string to display on LCD
* @retval None
*/
void BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *pText)
{
BSP_LCD_DisplayStringAt(0, LINE(Line),pText, LEFT_MODE);
}
/**
* @brief Reads an LCD pixel.
* @param Xpos: X position
* @param Ypos: Y position
* @retval RGB pixel color
*/
uint16_t BSP_LCD_ReadPixel(uint16_t Xpos, uint16_t Ypos)
{
uint16_t ret = 0;
if(lcd_drv->ReadPixel != NULL)
{
ret = lcd_drv->ReadPixel(Xpos, Ypos);
}
return ret;
}
/**
* @brief Draws an horizontal line.
* @param Xpos: X position
* @param Ypos: Y position
* @param Length: Line length
* @retval None
*/
void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length)
{
uint32_t index = 0;
if(lcd_drv->DrawHLine != NULL)
{
lcd_drv->DrawHLine(DrawProp.TextColor, Ypos, Xpos, Length);
}
else
{
for(index = 0; index < Length; index++)
{
BSP_LCD_DrawPixel((Ypos + index), Xpos, DrawProp.TextColor);
}
}
}
/**
* @brief Draws a vertical line.
* @param Xpos: X position
* @param Ypos: Y position
* @param Length: Line length
* @retval None
*/
void BSP_LCD_DrawVLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length)
{
uint32_t index = 0;
if(lcd_drv->DrawVLine != NULL)
{
LCD_SetDisplayWindow(Ypos, Xpos, 1, Length);
lcd_drv->DrawVLine(DrawProp.TextColor, Ypos, Xpos, Length);
LCD_SetDisplayWindow(0, 0, BSP_LCD_GetXSize(), BSP_LCD_GetYSize());
}
else
{
for(index = 0; index < Length; index++)
{
BSP_LCD_DrawPixel(Ypos, Xpos + index, DrawProp.TextColor);
}
}
}
/**
* @brief Draws an uni-line (between two points).
* @param X1: Point 1 X position
* @param Y1: Point 1 Y position
* @param X2: Point 2 X position
* @param Y2: Point 2 Y position
* @retval None
*/
void BSP_LCD_DrawLine(uint16_t X1, uint16_t Y1, uint16_t X2, uint16_t Y2)
{
int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,
yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,
curpixel = 0;
deltax = ABS(Y2 - Y1); /* The difference between the x's */
deltay = ABS(X2 - X1); /* The difference between the y's */
x = Y1; /* Start x off at the first pixel */
y = X1; /* Start y off at the first pixel */
if (Y2 >= Y1) /* The x-values are increasing */
{
xinc1 = 1;
xinc2 = 1;
}
else /* The x-values are decreasing */
{
xinc1 = -1;
xinc2 = -1;
}
if (X2 >= X1) /* The y-values are increasing */
{
yinc1 = 1;
yinc2 = 1;
}
else /* The y-values are decreasing */
{
yinc1 = -1;
yinc2 = -1;
}
if (deltax >= deltay) /* There is at least one x-value for every y-value */
{
xinc1 = 0; /* Don't change the x when numerator >= denominator */
yinc2 = 0; /* Don't change the y for every iteration */
den = deltax;
num = deltax / 2;
numadd = deltay;
numpixels = deltax; /* There are more x-values than y-values */
}
else /* There is at least one y-value for every x-value */
{
xinc2 = 0; /* Don't change the x for every iteration */
yinc1 = 0; /* Don't change the y when numerator >= denominator */
den = deltay;
num = deltay / 2;
numadd = deltax;
numpixels = deltay; /* There are more y-values than x-values */
}
for (curpixel = 0; curpixel <= numpixels; curpixel++)
{
BSP_LCD_DrawPixel(x, y, DrawProp.TextColor); /* Draw the current pixel */
num += numadd; /* Increase the numerator by the top of the fraction */
if (num >= den) /* Check if numerator >= denominator */
{
num -= den; /* Calculate the new numerator value */
x += xinc1; /* Change the x as appropriate */
y += yinc1; /* Change the y as appropriate */
}
x += xinc2; /* Change the x as appropriate */
y += yinc2; /* Change the y as appropriate */
}
}
/**
* @brief Draws a rectangle.
* @param Xpos: X position
* @param Ypos: Y position
* @param Width: Rectangle width
* @param Height: Rectangle height
* @retval None
*/
void BSP_LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
{
/* Draw horizontal lines */
BSP_LCD_DrawHLine(Xpos, Ypos, Width);
BSP_LCD_DrawHLine(Xpos, (Ypos+ Height), Width);
/* Draw vertical lines */
BSP_LCD_DrawVLine(Xpos, Ypos, Height);
BSP_LCD_DrawVLine((Xpos + Width), Ypos, Height);
}
/**
* @brief Draws a circle.
* @param Xpos: X position
* @param Ypos: Y position
* @param Radius: Circle radius
* @retval None
*/
void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
{
int32_t decision; /* Decision Variable */
uint32_t curx; /* Current X Value */
uint32_t cury; /* Current Y Value */
decision = 3 - (Radius << 1);
curx = 0;
cury = Radius;
while (curx <= cury)
{
BSP_LCD_DrawPixel((Ypos + curx), (Xpos - cury), DrawProp.TextColor);
BSP_LCD_DrawPixel((Ypos - curx), (Xpos - cury), DrawProp.TextColor);
BSP_LCD_DrawPixel((Ypos + cury), (Xpos - curx), DrawProp.TextColor);
BSP_LCD_DrawPixel((Ypos - cury), (Xpos - curx), DrawProp.TextColor);
BSP_LCD_DrawPixel((Ypos + curx), (Xpos + cury), DrawProp.TextColor);
BSP_LCD_DrawPixel((Ypos - curx), (Xpos + cury), DrawProp.TextColor);
BSP_LCD_DrawPixel((Ypos + cury), (Xpos + curx), DrawProp.TextColor);
BSP_LCD_DrawPixel((Ypos - cury), (Xpos + curx), DrawProp.TextColor);
/* Initialize the font */
BSP_LCD_SetFont(&LCD_DEFAULT_FONT);
if (decision < 0)
{
decision += (curx << 2) + 6;
}
else
{
decision += ((curx - cury) << 2) + 10;
cury--;
}
curx++;
}
}
/**
* @brief Draws an poly-line (between many points).
* @param pPoints: Pointer to the points array
* @param PointCount: Number of points
* @retval None
*/
void BSP_LCD_DrawPolygon(pPoint pPoints, uint16_t PointCount)
{
int16_t x = 0, y = 0;
if(PointCount < 2)
{
return;
}
BSP_LCD_DrawLine(pPoints->X, pPoints->Y, (pPoints+PointCount-1)->X, (pPoints+PointCount-1)->Y);
while(--PointCount)
{
x = pPoints->X;
y = pPoints->Y;
pPoints++;
BSP_LCD_DrawLine(x, y, pPoints->X, pPoints->Y);
}
}
/**
* @brief Draws an ellipse on LCD.
* @param Xpos: X position
* @param Ypos: Y position
* @param XRadius: Ellipse X radius
* @param YRadius: Ellipse Y radius
* @retval None
*/
void BSP_LCD_DrawEllipse(int Xpos, int Ypos, int XRadius, int YRadius)
{
int x = 0, y = -XRadius, err = 2-2*YRadius, e2;
float k = 0, rad1 = 0, rad2 = 0;
rad1 = YRadius;
rad2 = XRadius;
k = (float)(rad2/rad1);
do {
BSP_LCD_DrawPixel((Ypos-(uint16_t)(x/k)), (Xpos+y), DrawProp.TextColor);
BSP_LCD_DrawPixel((Ypos+(uint16_t)(x/k)), (Xpos+y), DrawProp.TextColor);
BSP_LCD_DrawPixel((Ypos+(uint16_t)(x/k)), (Xpos-y), DrawProp.TextColor);
BSP_LCD_DrawPixel((Ypos-(uint16_t)(x/k)), (Xpos-y), DrawProp.TextColor);
e2 = err;
if (e2 <= x) {
err += ++x*2+1;
if (-y == x && e2 <= y) e2 = 0;
}
if (e2 > y) err += ++y*2+1;
}
while (y <= 0);
}
/**
* @brief Draws a bitmap picture loaded in the internal Flash (32 bpp).
* @param Xpos: Bmp X position in the LCD
* @param Ypos: Bmp Y position in the LCD
* @param pBmp: Pointer to Bmp picture address in the internal Flash
* @retval None
*/
void BSP_LCD_DrawBitmap(uint16_t Xpos, uint16_t Ypos, uint8_t *pBmp)
{
uint32_t height = 0, width = 0;
/* Read bitmap width */
width = pBmp[18] + (pBmp[19] << 8) + (pBmp[20] << 16) + (pBmp[21] << 24);
/* Read bitmap height */
height = pBmp[22] + (pBmp[23] << 8) + (pBmp[24] << 16) + (pBmp[25] << 24);
/* Remap Ypos, hx8347d works with inverted X in case of bitmap */
/* X = 0, cursor is on Bottom corner */
if(lcd_drv == &hx8347d_drv)
{
Ypos = BSP_LCD_GetYSize() - Ypos - height;
}
LCD_SetDisplayWindow(Ypos, Xpos, width, height);
if(lcd_drv->DrawBitmap != NULL)
{
lcd_drv->DrawBitmap(Ypos, Xpos, pBmp);
}
LCD_SetDisplayWindow(0, 0, BSP_LCD_GetXSize(), BSP_LCD_GetYSize());
}
/**
* @brief Draws a full rectangle.
* @param Xpos: X position
* @param Ypos: Y position
* @param Width: Rectangle width
* @param Height: Rectangle height
* @retval None
*/
void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
{
BSP_LCD_SetTextColor(DrawProp.TextColor);
do
{
BSP_LCD_DrawHLine(Xpos, Ypos++, Width);
}
while(Height--);
}
/**
* @brief Draws a full circle.
* @param Xpos: X position
* @param Ypos: Y position
* @param Radius: Circle radius
* @retval None
*/
void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
{
int32_t decision; /* Decision Variable */
uint32_t curx; /* Current X Value */
uint32_t cury; /* Current Y Value */
decision = 3 - (Radius << 1);
curx = 0;
cury = Radius;
BSP_LCD_SetTextColor(DrawProp.TextColor);
while (curx <= cury)
{
if(cury > 0)
{
BSP_LCD_DrawVLine(Xpos + curx, Ypos - cury, 2*cury);
BSP_LCD_DrawVLine(Xpos - curx, Ypos - cury, 2*cury);
}
if(curx > 0)
{
BSP_LCD_DrawVLine(Xpos - cury, Ypos - curx, 2*curx);
BSP_LCD_DrawVLine(Xpos + cury, Ypos - curx, 2*curx);
}
if (decision < 0)
{
decision += (curx << 2) + 6;
}
else
{
decision += ((curx - cury) << 2) + 10;
cury--;
}
curx++;
}
BSP_LCD_SetTextColor(DrawProp.TextColor);
BSP_LCD_DrawCircle(Xpos, Ypos, Radius);
}
/**
* @brief Draws a full ellipse.
* @param Xpos: X position
* @param Ypos: Y position
* @param XRadius: Ellipse X radius
* @param YRadius: Ellipse Y radius
* @retval None
*/
void BSP_LCD_FillEllipse(int Xpos, int Ypos, int XRadius, int YRadius)
{
int x = 0, y = -XRadius, err = 2-2*YRadius, e2;
float k = 0, rad1 = 0, rad2 = 0;
rad1 = YRadius;
rad2 = XRadius;
k = (float)(rad2/rad1);
do
{
BSP_LCD_DrawVLine((Xpos+y), (Ypos-(uint16_t)(x/k)), (2*(uint16_t)(x/k) + 1));
BSP_LCD_DrawVLine((Xpos-y), (Ypos-(uint16_t)(x/k)), (2*(uint16_t)(x/k) + 1));
e2 = err;
if (e2 <= x)
{
err += ++x*2+1;
if (-y == x && e2 <= y) e2 = 0;
}
if (e2 > y) err += ++y*2+1;
}
while (y <= 0);
}
/**
* @brief Enables the display.
* @retval None
*/
void BSP_LCD_DisplayOn(void)
{
lcd_drv->DisplayOn();
}
/**
* @brief Disables the display.
* @retval None
*/
void BSP_LCD_DisplayOff(void)
{
lcd_drv->DisplayOff();
}
/**
* @brief Draws a pixel on LCD.
* @param Xpos: X position
* @param Ypos: Y position
* @param RGBCode: Pixel color in RGB mode (5-6-5)
* @retval None
*/
void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint16_t RGBCode)
{
if(lcd_drv->WritePixel != NULL)
{
lcd_drv->WritePixel(Xpos, Ypos, RGBCode);
}
}
/**
* @}
*/
/******************************************************************************
Static Function
*******************************************************************************/
/** @addtogroup STM32G0C1E_EVAL_LCD_Private_Functions
* @{
*/
/**
* @brief Draws a character on LCD.
* @param Xpos: Line where to display the character shape
* @param Ypos: Start column address
* @param pChar: Pointer to the character data
* @retval None
*/
static void LCD_DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *pChar)
{
uint32_t counterh = 0, counterw = 0, index = 0;
uint16_t height = 0, width = 0;
uint8_t offset = 0;
uint8_t *pchar = NULL;
uint32_t line = 0;
height = DrawProp.pFont->Height;
width = DrawProp.pFont->Width;
/* Fill bitmap header*/
*(uint16_t *) (bitmap + 2) = (uint16_t)(height*width*2+OFFSET_BITMAP);
*(uint16_t *) (bitmap + 4) = (uint16_t)((height*width*2+OFFSET_BITMAP)>>16);
*(uint16_t *) (bitmap + 10) = OFFSET_BITMAP;
*(uint16_t *) (bitmap + 18) = (uint16_t)(width);
*(uint16_t *) (bitmap + 20) = (uint16_t)((width)>>16);
*(uint16_t *) (bitmap + 22) = (uint16_t)(height);
*(uint16_t *) (bitmap + 24) = (uint16_t)((height)>>16);
offset = 8 *((width + 7)/8) - width ;
for(counterh = 0; counterh < height; counterh++)
{
pchar = ((uint8_t *)pChar + (width + 7)/8 * counterh);
if(((width + 7)/8) == 3)
{
line = (pchar[0]<< 16) | (pchar[1]<< 8) | pchar[2];
}
if(((width + 7)/8) == 2)
{
line = (pchar[0]<< 8) | pchar[1];
}
if(((width + 7)/8) == 1)
{
line = pchar[0];
}
for (counterw = 0; counterw < width; counterw++)
{
/* Image in the bitmap is written from the bottom to the top */
/* Need to invert image in the bitmap */
index = (((height-counterh-1)*width)+(counterw))*2+OFFSET_BITMAP;
if(line & (1 << (width- counterw + offset- 1)))
{
bitmap[index] = (uint8_t)DrawProp.TextColor;
bitmap[index+1] = (uint8_t)(DrawProp.TextColor >> 8);
}
else
{
bitmap[index] = (uint8_t)DrawProp.BackColor;
bitmap[index+1] = (uint8_t)(DrawProp.BackColor >> 8);
}
}
}
BSP_LCD_DrawBitmap(Ypos, Xpos, bitmap);
}
/**
* @brief Sets display window.
* @param Xpos: LCD X position
* @param Ypos: LCD Y position
* @param Width: LCD window width
* @param Height: LCD window height
* @retval None
*/
static void LCD_SetDisplayWindow(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
{
if(lcd_drv->SetDisplayWindow != NULL)
{
lcd_drv->SetDisplayWindow(Xpos, Ypos, Width, Height);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file STM32G0C1E_EVAL_lcd.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the
* STM32G0C1E_EVAL_lcd.c driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0C1E_EVAL_LCD_H
#define STM32G0C1E_EVAL_LCD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0c1e_eval.h"
/* Include LCD component Driver */
#include "../Components/hx8347d/hx8347d.h"
#include "../../../Utilities/Fonts/fonts.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM32G0C1E_EVAL
* @{
*/
/** @defgroup STM32G0C1E_EVAL_LCD STM32G0C1E_EVAL LCD
* @{
*/
/** @defgroup STM32G0C1E_EVAL_LCD_Exported_Types Exported Types
* @{
*/
typedef struct
{
uint32_t TextColor;
uint32_t BackColor;
sFONT *pFont;
} LCD_DrawPropTypeDef;
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_LCD_Exported_Constants Exported Constants
* @{
*/
/**
* @brief LCD status structure definition
*/
#define LCD_OK 0x00
#define LCD_ERROR 0x01
#define LCD_TIMEOUT 0x02
typedef struct
{
int16_t X;
int16_t Y;
} Point, * pPoint;
/**
* @brief Line mode structures definition
*/
typedef enum
{
CENTER_MODE = 0x01, /*!< Center mode */
RIGHT_MODE = 0x02, /*!< Right mode */
LEFT_MODE = 0x03, /*!< Left mode */
NO_MODE
} Line_ModeTypdef;
/**
* @brief LCD color
*/
#define LCD_COLOR_BLUE 0x001F
#define LCD_COLOR_GREEN 0x07E0
#define LCD_COLOR_RED 0xF800
#define LCD_COLOR_CYAN 0x07FF
#define LCD_COLOR_MAGENTA 0xF81F
#define LCD_COLOR_YELLOW 0xFFE0
#define LCD_COLOR_LIGHTBLUE 0x841F
#define LCD_COLOR_LIGHTGREEN 0x87F0
#define LCD_COLOR_LIGHTRED 0xFC10
#define LCD_COLOR_LIGHTCYAN 0x87FF
#define LCD_COLOR_LIGHTMAGENTA 0xFC1F
#define LCD_COLOR_LIGHTYELLOW 0xFFF0
#define LCD_COLOR_DARKBLUE 0x0010
#define LCD_COLOR_DARKGREEN 0x0400
#define LCD_COLOR_DARKRED 0x8000
#define LCD_COLOR_DARKCYAN 0x0410
#define LCD_COLOR_DARKMAGENTA 0x8010
#define LCD_COLOR_DARKYELLOW 0x8400
#define LCD_COLOR_WHITE 0xFFFF
#define LCD_COLOR_LIGHTGRAY 0xD69A
#define LCD_COLOR_GRAY 0x8410
#define LCD_COLOR_DARKGRAY 0x4208
#define LCD_COLOR_BLACK 0x0000
#define LCD_COLOR_BROWN 0xA145
#define LCD_COLOR_ORANGE 0xFD20
/* Macro to convert ST COLOR in RGB 24BIT definition to 16BIT RGB (R5bit,G6bit,B5bit) */
#define LCD_R(__R_COLOR__) (((__R_COLOR__>>3)&0x1F)<<11)
#define LCD_G(__G_COLOR__) (((__G_COLOR__>>2)&0x3F)<<5)
#define LCD_B(__B_COLOR__) ((__B_COLOR__>>3)&0x1F)
/* Definition of Official ST COLOR */
#define LCD_COLOR_ST_BLUE_DARK (LCD_R(0x00)|LCD_G(0x20)|LCD_B(0x52))
#define LCD_COLOR_ST_BLUE (LCD_R(0x39)|LCD_G(0xA9)|LCD_B(0xDC))
#define LCD_COLOR_ST_BLUE_LIGHT (LCD_R(0xD1)|LCD_G(0xE4)|LCD_B(0xF3))
#define LCD_COLOR_ST_GREEN_LIGHT (LCD_R(0xBB)|LCD_G(0xCC)|LCD_B(0x01))
#define LCD_COLOR_ST_GREEN_DARK (LCD_R(0x00)|LCD_G(0x3D)|LCD_B(0x14))
#define LCD_COLOR_ST_YELLOW (LCD_R(0xFF)|LCD_G(0xD3)|LCD_B(0x00))
#define LCD_COLOR_ST_BROWN (LCD_R(0x5C)|LCD_G(0x09)|LCD_B(0x15))
#define LCD_COLOR_ST_PINK (LCD_R(0xD4)|LCD_G(0x00)|LCD_B(0x7A))
#define LCD_COLOR_ST_PURPLE (LCD_R(0x59)|LCD_G(0x0D)|LCD_B(0x58))
#define LCD_COLOR_ST_GRAY_DARK (LCD_R(0x4F)|LCD_G(0x52)|LCD_B(0x51))
#define LCD_COLOR_ST_GRAY (LCD_R(0x90)|LCD_G(0x98)|LCD_B(0x9E))
#define LCD_COLOR_ST_GRAY_LIGHT (LCD_R(0xB9)|LCD_G(0xC4)|LCD_B(0xCA))
/**
* @brief LCD default font
*/
#ifndef LCD_DEFAULT_FONT
#define LCD_DEFAULT_FONT Font8
#endif
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_LCD_Exported_Functions Exported Functions
* @{
*/
uint8_t BSP_LCD_Init(void);
uint32_t BSP_LCD_GetXSize(void);
uint32_t BSP_LCD_GetYSize(void);
uint16_t BSP_LCD_GetTextColor(void);
uint16_t BSP_LCD_GetBackColor(void);
void BSP_LCD_SetTextColor(__IO uint16_t Color);
void BSP_LCD_SetBackColor(__IO uint16_t Color);
void BSP_LCD_SetFont(sFONT *pFonts);
sFONT *BSP_LCD_GetFont(void);
void BSP_LCD_Clear(uint16_t Color);
void BSP_LCD_ClearStringLine(uint16_t Line);
void BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *pText);
void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *pText, Line_ModeTypdef Mode);
void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii);
void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint16_t RGBCode);
uint16_t BSP_LCD_ReadPixel(uint16_t Xpos, uint16_t Ypos);
void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length);
void BSP_LCD_DrawVLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length);
void BSP_LCD_DrawLine(uint16_t X1, uint16_t Y1, uint16_t X2, uint16_t Y2);
void BSP_LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
void BSP_LCD_DrawPolygon(pPoint pPoints, uint16_t PointCount);
void BSP_LCD_DrawEllipse(int Xpos, int Ypos, int XRadius, int YRadius);
void BSP_LCD_DrawBitmap(uint16_t Xpos, uint16_t Ypos, uint8_t *pBmp);
void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
void BSP_LCD_FillEllipse(int Xpos, int Ypos, int XRadius, int YRadius);
void BSP_LCD_DisplayOff(void);
void BSP_LCD_DisplayOn(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0C1E_EVAL_LCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0c1e_eval_mux.c
* @author MCD Application Team
* @brief This file provides a set of functions needed to manage the Type-C
* MUX associated to a Type-C receptacle. These functions allow for
* reconfiguring the pins of the Type-C receptacle when the related
* Type-C port operate in DisplayPort alternate mode or
* when it is used as a USB 3.1 to USB Type-C adapter.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include <stdio.h>
#include "stm32g0c1e_eval.h"
#include "stm32g0c1e_eval_mux.h"
#include "stm32g0xx_hal.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM32G0C1E_EVAL
* @{
*/
/** @addtogroup STM32G0C1E_EVAL_MUX
* @{
*/
/** @defgroup STM32G0C1E_EVAL_MUX_Private_Typedef Private Typedef
* @{
*/
typedef enum {
MUX_NOT_INITIALIZED = 0,
MUX_INITIALIZED
} MUX_StateTypedef;
typedef struct {
MUX_StateTypedef State;
TYPECSWITCH_Drv_t * TypeCSwitch_Drv;
uint16_t I2C_Address_TypeCSwitch;
DPREDRIVER_Drv_t * DPRedriver_Drv;
uint16_t I2C_Address_DPRedriver;
} MuxInfoTypeDef;
typedef struct {
#if defined(TUSB546_DEBUG)
TUSB546_RegistersTypeDef TUSB546_Registers;
#endif /* TUSB546_DEBUG */
#if defined(CBTL08GP053_DEBUG)
CBTL08GP053_RegistersTypeDef CBTL08GP053_Registers;
#endif /* CBTL08GP053_DEBUG */
#if defined(SN65DP141_DEBUG)
SN65DP141_RegistersTypeDef SN65DP141_Registers;
#endif /* CBTL08GP053_DEBUG */
MUX_HPDCallbackFuncTypeDef * pfnHPDCallbackFunc;
MUX_HPDStateTypeDef HPDState;
MuxInfoTypeDef MuxInfo[TYPE_C_MUX_NB];
} ContextTypeDef;
typedef enum
{
DET_HPD_SOURCE = 0
} DetectId_TypeDef;
typedef enum
{
SEL_HPDIN = 0
} SelectId_TypeDef;
typedef enum {
DET_STATE_LOW = 0,
DET_STATE_HIGH
} MUX_DETState_TypeDef;
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_MUX_Private_Macros Private Macros
* @{
*/
#define DETx_GPIO_CLK_ENABLE(__DET__) do { if((__DET__) == DET_HPD_SOURCE) DET_HPD_SOURCE_GPIO_CLK_ENABLE();} while(0)
#define SELx_GPIO_CLK_ENABLE(__SEL__) do { if((__SEL__) == SEL_HPDIN) SEL_HPDIN_GPIO_CLK_ENABLE();} while(0)
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_MUX_Private_Variables Private Variables
* @{
*/
static const TYPECSWITCH_Mode_t ModeSelect[2][13] =
{
/* PLUG_ORIENTATION_NORMAL */
{
DFP_D_PIN_ASSIGNMENT_A_NORMAL, /* DFP_PIN_ASSIGNMMENT_A */
DFP_D_PIN_ASSIGNMENT_B_NORMAL, /* DFP_PIN_ASSIGNMMENT_B */
DFP_D_PIN_ASSIGNMENT_C_NORMAL, /* DFP_PIN_ASSIGNMMENT_C */
DFP_D_PIN_ASSIGNMENT_D_NORMAL, /* DFP_PIN_ASSIGNMMENT_D */
DFP_D_PIN_ASSIGNMENT_E_NORMAL, /* DFP_PIN_ASSIGNMMENT_E */
DFP_D_PIN_ASSIGNMENT_F_NORMAL, /* DFP_PIN_ASSIGNMMENT_F */
UFP_D_PIN_ASSIGNMENT_A_NORMAL, /* UFP_PIN_ASSIGNMMENT_A */
UFP_D_PIN_ASSIGNMENT_B_NORMAL, /* UFP_PIN_ASSIGNMMENT_B */
UFP_D_PIN_ASSIGNMENT_C_NORMAL, /* UFP_PIN_ASSIGNMMENT_C */
UFP_D_PIN_ASSIGNMENT_D_NORMAL, /* UFP_PIN_ASSIGNMMENT_D */
UFP_D_PIN_ASSIGNMENT_E_NORMAL, /* UFP_PIN_ASSIGNMMENT_E */
UFP_D_PIN_ASSIGNMENT_F_NORMAL, /* UFP_PIN_ASSIGNMMENT_F */
USB_NORMAL /* USB_ONLY_PIN_ASSIGNMMENT */
},
/* PLUG_ORIENTATION_FLIPPED */
{
DFP_D_PIN_ASSIGNMENT_A_FLIPPED, /* DFP_PIN_ASSIGNMMENT_A */
DFP_D_PIN_ASSIGNMENT_B_FLIPPED, /* DFP_PIN_ASSIGNMMENT_B */
DFP_D_PIN_ASSIGNMENT_C_FLIPPED, /* DFP_PIN_ASSIGNMMENT_C */
DFP_D_PIN_ASSIGNMENT_D_FLIPPED, /* DFP_PIN_ASSIGNMMENT_D */
DFP_D_PIN_ASSIGNMENT_E_FLIPPED, /* DFP_PIN_ASSIGNMMENT_E */
DFP_D_PIN_ASSIGNMENT_F_FLIPPED, /* DFP_PIN_ASSIGNMMENT_F */
UFP_D_PIN_ASSIGNMENT_A_FLIPPED, /* UFP_PIN_ASSIGNMMENT_A */
UFP_D_PIN_ASSIGNMENT_B_FLIPPED, /* UFP_PIN_ASSIGNMMENT_B */
UFP_D_PIN_ASSIGNMENT_C_FLIPPED, /* UFP_PIN_ASSIGNMMENT_C */
UFP_D_PIN_ASSIGNMENT_D_FLIPPED, /* UFP_PIN_ASSIGNMMENT_D */
UFP_D_PIN_ASSIGNMENT_E_FLIPPED, /* UFP_PIN_ASSIGNMMENT_E */
UFP_D_PIN_ASSIGNMENT_F_FLIPPED, /* UFP_PIN_ASSIGNMMENT_F */
USB_FLIPPED /* USB_ONLY_PIN_ASSIGNMMENT */
}
};
/**
* @brief SEL variables
*/
static GPIO_TypeDef* SEL_PORT[SELn] = {
SEL_HPDIN_GPIO_PORT,
};
static uint16_t SEL_PIN[SELn] = {
SEL_HPDIN_PIN,
};
/* BSP PWR contextual data */
static ContextTypeDef Context =
{
.HPDState = HPD_STATE_LOW,
.pfnHPDCallbackFunc = (MUX_HPDCallbackFuncTypeDef *)NULL,
.MuxInfo =
{
/* TYPE_C_MUX_1 */
{
.State = MUX_NOT_INITIALIZED,
.TypeCSwitch_Drv = &tusb546_drv_CrossSwitch,
.I2C_Address_TypeCSwitch = MUX_1_TYPEC_SWITCH_I2C_ADDRESS,
.DPRedriver_Drv = &tusb546_drv_LinearRedriver,
.I2C_Address_DPRedriver = MUX_1_DP_REDRIVER_I2C_ADDRESS
},
/* TYPE_C_MUX_2 */
{
.State = MUX_NOT_INITIALIZED,
.TypeCSwitch_Drv = &cbtl08gp053_drv,
.I2C_Address_TypeCSwitch = MUX_2_TYPEC_SWITCH_I2C_ADDRESS,
.DPRedriver_Drv = &sn65dp141_drv,
.I2C_Address_DPRedriver = MUX_2_DP_REDRIVER_I2C_ADDRESS
}
}
};
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_MUX_Private_Functions Private Functions
* @{
*/
static void MUX_DET_Init(void);
static void MUX_DET_DeInit(void);
static MUX_DETState_TypeDef MUX_DET_GetState(void);
static void MUX_SEL_Init(SelectId_TypeDef Sel);
static void MUX_SEL_DeInit(SelectId_TypeDef Sel);
static void MUX_SEL_On(SelectId_TypeDef Sel);
static void MUX_SEL_Off(SelectId_TypeDef Sel);
static void MUX_DebounceTimerSetConfig(uint32_t DebounceTime);
static void MUX_DebounceTimerResetConfig(void);
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_MUX_Exported_Variables Exported Variables
* @{
*/
TIM_HandleTypeDef htim = {.Instance = DEBOUNCE_TIM_INSTANCE};
/**
* @}
*/
/** @addtogroup STM32G0C1E_EVAL_MUX_Exported_Functions
* @{
*/
/**
* @brief Initialize the hardware resources used by the Type-C MUX
* assigned to a given Type-C MUX.
* @param TypeCMuxId Type-C MUX identifier
* This parameter can be take one of the following values:
* @arg TYPE_C_MUX_1
* @arg TYPE_C_MUX_2
* @retval mux status
*/
MUX_StatusTypeDef BSP_MUX_Init(MUX_TypeCMuxIdTypeDef TypeCMuxId)
{
uint32_t ret = 0;
if (Context.MuxInfo[TypeCMuxId].State == MUX_NOT_INITIALIZED)
{
switch (TypeCMuxId)
{
case TYPE_C_MUX_1:
case TYPE_C_MUX_2:
/* USB Type-C Crossbar Switch initialization */
ret += Context.MuxInfo[TypeCMuxId].TypeCSwitch_Drv->Init(Context.MuxInfo[TypeCMuxId].I2C_Address_TypeCSwitch);
/* DisplayPort Linear Redriver initialization */
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->Init(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver);
if (TypeCMuxId == TYPE_C_MUX_1)
{
MUX_SEL_Init(SEL_HPDIN);
}
else
{
/* DET_HPD_SOURCE */
MUX_DET_Init();
}
/* Initialize the debounce timer (if not done already) */
if ((Context.MuxInfo[TYPE_C_MUX_1].State == MUX_NOT_INITIALIZED) &&
(Context.MuxInfo[TYPE_C_MUX_2].State == MUX_NOT_INITIALIZED))
{
MUX_DebounceTimerSetConfig(DEBOUNCE_TIME);
}
/* Update Context */
Context.MuxInfo[TypeCMuxId].State = MUX_INITIALIZED;
break;
default:
ret++;
break;
}
}
return (ret == 0) ? MUX_OK : MUX_ERROR;
}
/**
* @brief Free the hardware resources used by the Type-C MUX
* assigned to a given Type-C MUX.
* @param TypeCMuxId Type-C MUX identifier
* This parameter can be take one of the following values:
* @arg TYPE_C_MUX_1
* @arg TYPE_C_MUX_2
* @retval mux status
*/
MUX_StatusTypeDef BSP_MUX_DeInit(MUX_TypeCMuxIdTypeDef TypeCMuxId)
{
uint32_t ret = 0;
if (Context.MuxInfo[TypeCMuxId].State == MUX_INITIALIZED)
{
switch (TypeCMuxId)
{
case TYPE_C_MUX_1:
case TYPE_C_MUX_2:
/* USB Type-C Crossbar Switch de-initialization */
Context.MuxInfo[TypeCMuxId].TypeCSwitch_Drv->DeInit(Context.MuxInfo[TypeCMuxId].I2C_Address_TypeCSwitch);
/* DisplayPort Linear Redriver de-initialization */
Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->DeInit(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver);
if (TypeCMuxId == TYPE_C_MUX_1)
{
MUX_DebounceTimerResetConfig();
MUX_SEL_DeInit(SEL_HPDIN);
}
else
{
/* DET_HPD_SOURCE */
MUX_DET_DeInit();
}
/* Update Context */
Context.MuxInfo[TypeCMuxId].State = MUX_NOT_INITIALIZED;
/* De-initialize the debounce timer (if not required anymore)*/
if ((Context.MuxInfo[TYPE_C_MUX_1].State == MUX_NOT_INITIALIZED) &&
(Context.MuxInfo[TYPE_C_MUX_2].State == MUX_NOT_INITIALIZED))
{
MUX_DebounceTimerResetConfig();
}
break;
default:
ret++;
break;
}
}
return (ret == 0) ? MUX_OK : MUX_ERROR;
}
/**
* @brief Power on the Type-C MUX.
* @param TypeCMuxId Type-C MUX identifier
* This parameter can be take one of the following values:
* @arg TYPE_C_MUX_1
* @arg TYPE_C_MUX_2
* @retval mux status
*/
MUX_StatusTypeDef BSP_MUX_Enable(MUX_TypeCMuxIdTypeDef TypeCMuxId)
{
uint32_t ret = 0;
switch (TypeCMuxId)
{
case TYPE_C_MUX_1:
case TYPE_C_MUX_2:
/* Power on USB Type-C Crossbar Switch */
ret += Context.MuxInfo[TypeCMuxId].TypeCSwitch_Drv->PowerOn(Context.MuxInfo[TypeCMuxId].I2C_Address_TypeCSwitch);
/* Power on DisplayPort Linear Redriver */
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->PowerOn(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver);
break;
default:
ret++;
break;
}
return (ret == 0) ? MUX_OK : MUX_ERROR;
}
/**
* @brief Power down the Type-C MUX.
* @param TypeCMuxId Type-C MUX identifier
* This parameter can be take one of the following values:
* @arg TYPE_C_MUX_1
* @arg TYPE_C_MUX_2
* @retval mux status
*/
MUX_StatusTypeDef BSP_MUX_Disable(MUX_TypeCMuxIdTypeDef TypeCMuxId)
{
uint32_t ret = 0;
switch (TypeCMuxId)
{
case TYPE_C_MUX_1:
case TYPE_C_MUX_2:
/* Power off USB Type-C Crossbar Switch */
ret += Context.MuxInfo[TypeCMuxId].TypeCSwitch_Drv->PowerOff(Context.MuxInfo[TypeCMuxId].I2C_Address_TypeCSwitch);
/* Power down DisplayPort Linear Redriver */
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->PowerOff(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver);
break;
default:
ret++;
break;
}
return (ret == 0) ? MUX_OK : MUX_ERROR;
}
/**
* @brief Set the pin assignment of the USB Type-C connector when it operates
* in one of the following mode:
* DFP_D: Downstream Facing Port associated with a DisplayPort Source device
* UFP_D: Upstream Facing Port associated with a DisplayPort Source device
* @param TypeCMuxId Type-C MUX identifier
* This parameter can be take one of the following values:
* @arg TYPE_C_MUX_1
* @arg TYPE_C_MUX_2
* @param TypeCPlugOrientation Type-C plug orientation
* This parameter can be take one of the following values:
* @arg PLUG_ORIENTATION_NORMAL
* @arg PLUG_ORIENTATION_FLIPPED
* @param TypeCConnectorPinAssignment Type-C connector pin assignment
* This parameter can be take one of the following values:
* @arg DFP_PIN_ASSIGNMMENT_A
* @arg DFP_PIN_ASSIGNMMENT_B
* @arg DFP_PIN_ASSIGNMMENT_C
* @arg DFP_PIN_ASSIGNMMENT_D
* @arg DFP_PIN_ASSIGNMMENT_E
* @arg DFP_PIN_ASSIGNMMENT_F
* @arg UFP_PIN_ASSIGNMMENT_A
* @arg UFP_PIN_ASSIGNMMENT_B
* @arg UFP_PIN_ASSIGNMMENT_C
* @arg UFP_PIN_ASSIGNMMENT_D
* @arg UFP_PIN_ASSIGNMMENT_E
* @arg UFP_PIN_ASSIGNMMENT_F
* @arg USB_ONLY_PIN_ASSIGNMMENT
* @retval mux status
*/
MUX_StatusTypeDef BSP_MUX_SetDPPinAssignment(MUX_TypeCMuxIdTypeDef TypeCMuxId,
MUX_TypeCPlugOrientationTypeDef TypeCPlugOrientation,
MUX_TypeCConnectorPinAssignmentTypeDef TypeCConnectorPinAssignment)
{
uint32_t ret = 0;
TYPECSWITCH_Mode_t Mode;
Mode = ModeSelect[TypeCPlugOrientation][TypeCConnectorPinAssignment];
if (Context.MuxInfo[TypeCMuxId].TypeCSwitch_Drv->IsSupportedMode(Mode))
{
/* Set Alt. mode */
ret += Context.MuxInfo[TypeCMuxId].TypeCSwitch_Drv->SetMode(Context.MuxInfo[TypeCMuxId].I2C_Address_TypeCSwitch, Mode);
/* Enable Display Port channels (if required) */
switch(TypeCConnectorPinAssignment)
{
case USB_ONLY_PIN_ASSIGNMMENT:
/* no DP channel enabled */
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->DisableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP0);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->DisableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP1);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->DisableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP2);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->DisableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP3);
break;
case DFP_PIN_ASSIGNMMENT_B:
case DFP_PIN_ASSIGNMMENT_D:
case DFP_PIN_ASSIGNMMENT_F:
case UFP_PIN_ASSIGNMMENT_B:
case UFP_PIN_ASSIGNMMENT_D:
case UFP_PIN_ASSIGNMMENT_F:
/* Enable Display Port ML0 and ML1 */
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->EnableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP0);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->EnableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP1);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->DisableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP2);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->DisableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP3);
break;
case DFP_PIN_ASSIGNMMENT_A:
case DFP_PIN_ASSIGNMMENT_C:
case DFP_PIN_ASSIGNMMENT_E:
case UFP_PIN_ASSIGNMMENT_A:
case UFP_PIN_ASSIGNMMENT_C:
case UFP_PIN_ASSIGNMMENT_E:
/* Enable Display Port ML0, ML1, ML2 and ML3 */
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->EnableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP0);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->EnableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP1);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->EnableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP2);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->EnableChannel(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP3);
break;
}
}
return (ret == 0) ? MUX_OK : MUX_ERROR;
}
/**
* @brief Set the equalizer gain for all the channels
* @param TypeCMuxId Type-C MUX identifier
* This parameter can be take one of the following values:
* @arg TYPE_C_MUX_1
* @arg TYPE_C_MUX_2
* @param EQGain Equalizer gain.
* TYPE_C_MUX_1: This parameter must be a value between 0x00 and @ref MUX_1_EQGAIN_MAX.
* TYPE_C_MUX_2: This parameter must be a value between 0x00 and @ref MUX_2_EQGAIN_MAX.
* @retval mux status
*/
MUX_StatusTypeDef BSP_MUX_SetEQGain(MUX_TypeCMuxIdTypeDef TypeCMuxId,
uint8_t EQGain)
{
uint32_t ret = 1;
if (((TYPE_C_MUX_1 == TypeCMuxId) && (MUX_1_EQGAIN_MAX >= EQGain))
|| ((TYPE_C_MUX_2 == TypeCMuxId) && (MUX_2_EQGAIN_MAX >= EQGain)))
{
ret = 0;
/* Set EQ gain for Port ML0, ML1, ML2 and ML3 */
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->SetEQGain(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP0, EQGain);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->SetEQGain(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP1, EQGain);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->SetEQGain(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP2, EQGain);
ret += Context.MuxInfo[TypeCMuxId].DPRedriver_Drv->SetEQGain(Context.MuxInfo[TypeCMuxId].I2C_Address_DPRedriver, CHANNEL_DP3, EQGain);
}
return (ret == 0) ? MUX_OK : MUX_ERROR;
}
/**
* @brief Set the HPD level seen by the DP source device.
* @note This function is used to enable DisplayPort HPD signaling
* through PD messaging.
* @param TypeCMuxId Type-C MUX identifier
* This parameter can be take one of the following values:
* @arg TYPE_C_MUX_1
* @arg TYPE_C_MUX_2
* @param HPDState Hot Plud Detection (HPD) state
* This parameter can be take one of the following values:
* @arg HPD_STATE_LOW
* @arg HPD_STATE_HIGH
* @retval mux status
*/
MUX_StatusTypeDef BSP_MUX_SetHPDState(MUX_TypeCMuxIdTypeDef TypeCMuxId,
MUX_HPDStateTypeDef HPDState)
{
uint32_t ret = 0;
switch (TypeCMuxId)
{
case TYPE_C_MUX_1:
if(HPD_STATE_LOW == HPDState)
{
MUX_SEL_Off(SEL_HPDIN);
}
else
{
MUX_SEL_On(SEL_HPDIN);
}
break;
default:
ret++;
break;
}
return (ret == 0) ? MUX_OK : MUX_ERROR;
}
/**
* @brief Retrieve actual HPD level of the DP source device.
* @param TypeCMuxId Type-C MUX identifier
* This parameter can be take one of the following values:
* @arg TYPE_C_MUX_1
* @arg TYPE_C_MUX_2
* @param pHPDState pointer to the Hot Plud Detection (HPD) state
* This parameter can be take one of the following values:
* @arg HPD_STATE_LOW
* @arg HPD_STATE_HIGH
* @retval mux status
*/
MUX_StatusTypeDef BSP_MUX_GetHPDState(MUX_TypeCMuxIdTypeDef TypeCMuxId,
MUX_HPDStateTypeDef * pHPDState)
{
uint32_t ret = 0;
/* Initialize returned HPDState */
*pHPDState = HPD_STATE_LOW;
/* Read HPDState */
switch (TypeCMuxId)
{
case TYPE_C_MUX_2:
*pHPDState = (MUX_HPDStateTypeDef)MUX_DET_GetState();
break;
default:
ret++;
break;
}
return (ret == 0) ? MUX_OK : MUX_ERROR;
}
/**
* @brief Generate an HPD_IRQ towards the DP source device.
* @note This function must be called every time an HPD_IRQ is detected by the
* PD communication stack.
* @param TypeCMuxId Type-C MUX identifier
* This parameter can be take one of the following values:
* @arg TYPE_C_MUX_1
* @arg TYPE_C_MUX_2
* @retval mux status
*/
MUX_StatusTypeDef BSP_MUX_HPDIRQ(MUX_TypeCMuxIdTypeDef TypeCMuxId)
{
MUX_StatusTypeDef ret = MUX_ERROR;
return ret;
}
/**
* @brief Display port hot plug detection (HPD)function.
* @note This function must be called when a display bort capable device
* is connected to the Display Port source receptacle of the MB1352
* daughter board.
* @retval none
*/
void BSP_MUX_Detect_HPD(void)
{
if (Context.pfnHPDCallbackFunc != (MUX_HPDCallbackFuncTypeDef *)NULL)
{
HAL_TIM_Base_Start_IT(&htim);
}
}
/**
* @brief HPD callback function registration.
* @note The sink device drives a hot plug detect (HPD) signal to notify the
* source that a sink is present.
* @note Once registered, HPD callback function will be called upon connection
* disconnection of a DP Sink device.
* @param TypeCMuxId Type-C MUX identifier
* This parameter can be take one of the following values:
* @arg TYPE_C_MUX_1
* @arg TYPE_C_MUX_2
* @param pHPDCallbackFunc HPD callback function pointer
* @retval mux status
*/
MUX_StatusTypeDef BSP_MUX_RegisterHPDCallbackFunc(MUX_TypeCMuxIdTypeDef TypeCMuxId,
MUX_HPDCallbackFuncTypeDef * pHPDCallbackFunc)
{
uint8_t ret = 0;
if (TypeCMuxId == TYPE_C_MUX_2)
{
Context.pfnHPDCallbackFunc = pHPDCallbackFunc;
}
else
{
ret++;
}
return (ret == 0) ? MUX_OK : MUX_ERROR;
}
/**
* @brief Initializes the TIM Base MSP.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
/* Enable Debounce Timer clock */
DEBOUNCE_TIM_CLK_ENABLE();
/* NVIC configuration for debounce timer interrupt */
HAL_NVIC_SetPriority(DEBOUNCE_TIM_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(DEBOUNCE_TIM_IRQn);
}
/**
* @brief DeInitialize TIM Base MSP.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Enable Debounce Timer clock */
DEBOUNCE_TIM_CLK_DISABLE();
/* Disable Debounce timer interrupt */
HAL_NVIC_DisableIRQ(DEBOUNCE_TIM_IRQn);
}
#if defined(TUSB546_DEBUG) || defined(CBTL08GP053_DEBUG) || defined(SN65DP141_DEBUG)
/**
* @brief Dump the register content of a device .
* @param Device device(s)
* This parameter can be any combination of the following values:
* DEVICE_CBTL08GP053
* DEVICE_SN65DP141
* DEVICE_TUSB546
* @retval none
*/
void BSP_MUX_DumpDeviceRegisters(uint32_t Device)
{
#if defined(CBTL08GP053_DEBUG)
if ((Device & DEVICE_CBTL08GP053) == DEVICE_CBTL08GP053)
{
printf("\n\tCBTL08GP053 registers dump:\n");
MUX_IO_Read(MUX_2_TYPEC_SWITCH_I2C_ADDRESS, CBTL08GP053_REG_SYS_CTRL, &Context.CBTL08GP053_Registers.SysCtrl.Register);
printf("\t\tSYS_CTRL : 0x%0.2x\n", Context.CBTL08GP053_Registers.SysCtrl.Register);
MUX_IO_Read(MUX_2_TYPEC_SWITCH_I2C_ADDRESS, CBTL08GP053_REG_OP1_CTRL, &Context.CBTL08GP053_Registers.Op1Ctrl.Register);
printf("\t\tOP1_CTRL : 0x%0.2x\n", Context.CBTL08GP053_Registers.Op1Ctrl.Register);
MUX_IO_Read(MUX_2_TYPEC_SWITCH_I2C_ADDRESS, CBTL08GP053_REG_OP2_CTRL, &Context.CBTL08GP053_Registers.Op2Ctrl.Register);
printf("\t\tOP2_CTRL : 0x%0.2x\n", Context.CBTL08GP053_Registers.Op2Ctrl.Register);
MUX_IO_Read(MUX_2_TYPEC_SWITCH_I2C_ADDRESS, CBTL08GP053_REG_OP3_CTRL, &Context.CBTL08GP053_Registers.Op3Ctrl.Register);
printf("\t\tOP3_CTRL : 0x%0.2x\n", Context.CBTL08GP053_Registers.Op3Ctrl.Register);
MUX_IO_Read(MUX_2_TYPEC_SWITCH_I2C_ADDRESS, CBTL08GP053_REG_OP4_CTRL, &Context.CBTL08GP053_Registers.Op4Ctrl.Register);
printf("\t\tOP4_CTRL : 0x%0.2x\n", Context.CBTL08GP053_Registers.Op4Ctrl.Register);
MUX_IO_Read(MUX_2_TYPEC_SWITCH_I2C_ADDRESS, CBTL08GP053_REG_OP5_CTRL, &Context.CBTL08GP053_Registers.Op5Ctrl.Register);
printf("\t\tOP5_CTRL : 0x%0.2x\n", Context.CBTL08GP053_Registers.Op5Ctrl.Register);
MUX_IO_Read(MUX_2_TYPEC_SWITCH_I2C_ADDRESS, CBTL08GP053_REG_CROSS5_CTRL, &Context.CBTL08GP053_Registers.Cross5Ctrl.Register);
printf("\t\tCROSS5_CTRL: 0x%0.2x\n", Context.CBTL08GP053_Registers.Cross5Ctrl.Register);
MUX_IO_Read(MUX_2_TYPEC_SWITCH_I2C_ADDRESS, CBTL08GP053_REG_SW_CTRL, &Context.CBTL08GP053_Registers.SwCtrl.Register);
printf("\t\tSW_CTRL : 0x%0.2x\n", Context.CBTL08GP053_Registers.SwCtrl.Register);
MUX_IO_Read(MUX_2_TYPEC_SWITCH_I2C_ADDRESS, CBTL08GP053_REG_REVISION, &Context.CBTL08GP053_Registers.Revision);
printf("\t\tREVISION : 0x%0.2x\n", Context.CBTL08GP053_Registers.Revision);
}
#endif /* CBTL08GP053_DEBUG */
#if defined(SN65DP141_DEBUG)
if ((Device & DEVICE_SN65DP141) == DEVICE_SN65DP141)
{
printf("\n\tSN65DP141 registers dump:\n");
MUX_IO_Read(MUX_2_DP_REDRIVER_I2C_ADDRESS, SN65DP141_REG_CFG, &Context.SN65DP141_Registers.General.Register);
printf("\t\tGeneral Device Settings : 0x%0.2x\n", Context.SN65DP141_Registers.General.Register);
MUX_IO_Read(MUX_2_DP_REDRIVER_I2C_ADDRESS, SN65DP141_REG_CHEN, &Context.SN65DP141_Registers.ChannelEnable.Register);
printf("\t\tChannel Enable : 0x%0.2x\n", Context.SN65DP141_Registers.ChannelEnable.Register);
MUX_IO_Read(MUX_2_DP_REDRIVER_I2C_ADDRESS, SN65DP141_REG_CH0_CFG, &Context.SN65DP141_Registers.Channel0Ctrl.Register);
printf("\t\tChannel 0 Control Settings: 0x%0.2x\n", Context.SN65DP141_Registers.Channel0Ctrl.Register);
MUX_IO_Read(MUX_2_DP_REDRIVER_I2C_ADDRESS, SN65DP141_REG_CH0_EN, &Context.SN65DP141_Registers.Channel0Enable.Register);
printf("\t\tChannel 0 Enable Settings : 0x%0.2x\n", Context.SN65DP141_Registers.Channel0Enable.Register);
MUX_IO_Read(MUX_2_DP_REDRIVER_I2C_ADDRESS, SN65DP141_REG_CH1_CFG, &Context.SN65DP141_Registers.Channel1Ctrl.Register);
printf("\t\tChannel 1 Control Settings: 0x%0.2x\n", Context.SN65DP141_Registers.Channel1Ctrl.Register);
MUX_IO_Read(MUX_2_DP_REDRIVER_I2C_ADDRESS, SN65DP141_REG_CH1_EN, &Context.SN65DP141_Registers.Channel1Enable.Register);
printf("\t\tChannel 1 Enable Settings : 0x%0.2x\n", Context.SN65DP141_Registers.Channel1Enable.Register);
MUX_IO_Read(MUX_2_DP_REDRIVER_I2C_ADDRESS, SN65DP141_REG_CH2_CFG, &Context.SN65DP141_Registers.Channel2Ctrl.Register);
printf("\t\tChannel 2 Control Settings: 0x%0.2x\n", Context.SN65DP141_Registers.Channel2Ctrl.Register);
MUX_IO_Read(MUX_2_DP_REDRIVER_I2C_ADDRESS, SN65DP141_REG_CH2_EN, &Context.SN65DP141_Registers.Channel2Enable.Register);
printf("\t\tChannel 2 Enable Settings : 0x%0.2x\n", Context.SN65DP141_Registers.Channel2Enable.Register);
MUX_IO_Read(MUX_2_DP_REDRIVER_I2C_ADDRESS, SN65DP141_REG_CH3_CFG, &Context.SN65DP141_Registers.Channel3Ctrl.Register);
printf("\t\tChannel 3 Control Settings: 0x%0.2x\n", Context.SN65DP141_Registers.Channel3Ctrl.Register);
MUX_IO_Read(MUX_2_DP_REDRIVER_I2C_ADDRESS, SN65DP141_REG_CH3_EN, &Context.SN65DP141_Registers.Channel3Enable.Register);
printf("\t\tChannel 3 Enable Settings : 0x%0.2x\n", Context.SN65DP141_Registers.Channel3Enable.Register);
}
#endif /* SN65DP141_DEBUG */
#if defined(TUSB546_DEBUG)
if ((Device & DEVICE_TUSB546) == DEVICE_TUSB546)
{
MUX_IO_Read(MUX_1_TYPEC_SWITCH_I2C_ADDRESS, TUSB546_REG_CTRL, &Context.TUSB546_Registers.General.Register);
MUX_IO_Read(MUX_1_TYPEC_SWITCH_I2C_ADDRESS, TUSB546_REG_DP_CTRL1, &Context.TUSB546_Registers.DPCtrlStatus10.Register);
MUX_IO_Read(MUX_1_TYPEC_SWITCH_I2C_ADDRESS, TUSB546_REG_DP_CTRL2, &Context.TUSB546_Registers.DPCtrlStatus11.Register);
MUX_IO_Read(MUX_1_TYPEC_SWITCH_I2C_ADDRESS, TUSB546_REG_DP_CTRL3, &Context.TUSB546_Registers.DPCtrlStatus12.Register);
MUX_IO_Read(MUX_1_TYPEC_SWITCH_I2C_ADDRESS, TUSB546_REG_DP_CTRL4, &Context.TUSB546_Registers.DPCtrlStatus13.Register);
}
#endif /* TUSB546_DEBUG */
}
#endif /* TUSB546_DEBUG || CBTL08GP053_DEBUG || SN65DP141_DEBUG */
/**
* @}
*/
/** @addtogroup STM32G0C1E_EVAL_MUX_Private_Functions
* @{
*/
/**
* @brief Configures DET GPIO.
* @note This function configures Detection GPIO pin for DET_HPD_SOURCE
* @retval None
*/
static void MUX_DET_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* Enable the GPIO_DET clock */
DET_HPD_SOURCE_GPIO_CLK_ENABLE();
/* Configure the GPIO_MOS pin */
GPIO_InitStruct.Pin = DET_HPD_SOURCE_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(DET_HPD_SOURCE_GPIO_PORT, &GPIO_InitStruct);
/* Enable and set EXTI lines Interrupt to the lowest priority */
HAL_NVIC_SetPriority(DET_EXTI_IRQn, 2, 0);
HAL_NVIC_EnableIRQ(DET_EXTI_IRQn);
}
/**
* @brief Reset DET GPIO configuration.
* @note This function resets configuration of Detection GPIO pin for DET_HPD_SOURCE
* @retval None
*/
static void MUX_DET_DeInit(void)
{
/* Disable EXTI lines Interrupt */
HAL_NVIC_DisableIRQ(DET_EXTI_IRQn);
HAL_GPIO_DeInit(DET_HPD_SOURCE_GPIO_PORT, DET_HPD_SOURCE_PIN);
}
/**
* @brief Returns the selected Detect state.
* @note This function returns GPIO pin state for DET_HPD_SOURCE
* @retval The Detect GPIO pin value
*/
static MUX_DETState_TypeDef MUX_DET_GetState(void)
{
GPIO_PinState PinState;
PinState = HAL_GPIO_ReadPin(DET_HPD_SOURCE_GPIO_PORT, DET_HPD_SOURCE_PIN);
/* Update Context */
Context.HPDState = HPD_STATE_LOW;
if (GPIO_PIN_SET == PinState)
{
Context.HPDState = HPD_STATE_HIGH;
}
return (PinState == GPIO_PIN_RESET) ? DET_STATE_LOW : DET_STATE_HIGH;
}
/**
* @brief Configures SEL GPIO.
* @param Sel Specifies the Select Pin to be configured.
* This parameter can be one of following parameters:
* @arg SEL_HPDIN
* @retval None
*/
static void MUX_SEL_Init(SelectId_TypeDef Sel)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* Enable the GPIO_DET clock */
SELx_GPIO_CLK_ENABLE(Sel);
/* Configure the GPIO_MOS pin */
GPIO_InitStruct.Pin = SEL_PIN[Sel];
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(SEL_PORT[Sel], &GPIO_InitStruct);
HAL_GPIO_WritePin(SEL_PORT[Sel], SEL_PIN[Sel], GPIO_PIN_RESET);
}
/**
* @brief Reset SEL GPIO configuration.
* @param Sel Specifies the Select Pin.
* This parameter can be one of following parameters:
* @arg SEL_HPDIN
* @retval None
*/
static void MUX_SEL_DeInit(SelectId_TypeDef Sel)
{
HAL_GPIO_DeInit(SEL_PORT[Sel], SEL_PIN[Sel]);
}
/**
* @brief Turns selected Sel On.
* @param Sel Specifies the Select Pin to be configured.
* This parameter can be one of following parameters:
* @arg SEL_HPDIN
* @retval None
*/
static void MUX_SEL_On(SelectId_TypeDef Sel)
{
HAL_GPIO_WritePin(SEL_PORT[Sel], SEL_PIN[Sel], GPIO_PIN_SET);
}
/**
* @brief Turns selected Det Off.
* @param Sel Specifies the Select Pin to be configured.
* This parameter can be one of following parameters:
* @arg SEL_HPDIN
* @retval None
*/
static void MUX_SEL_Off(SelectId_TypeDef Sel)
{
HAL_GPIO_WritePin(SEL_PORT[Sel], SEL_PIN[Sel], GPIO_PIN_RESET);
}
/**
* @brief Set debounce timer configuration.
* @param DebounceTime Debounce time (in us)
* @retval None
*/
static void MUX_DebounceTimerSetConfig(uint32_t DebounceTime)
{
__HAL_TIM_RESET_HANDLE_STATE(&htim);
htim.Init.Prescaler = (DEBOUNCE_TIM_COUNTER_CLK_FREQ() / 1000000) -1;
htim.Init.CounterMode = TIM_COUNTERMODE_UP;
htim.Init.Period = DebounceTime - 1;
htim.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim.Init.RepetitionCounter = 0;
htim.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
HAL_TIM_Base_Init(&htim);
}
/**
* @brief Reset debounce timer configuration.
* @retval None
*/
static void MUX_DebounceTimerResetConfig(void)
{
HAL_TIM_Base_DeInit(&htim);
}
/**
* @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
HAL_TIM_Base_Stop_IT(htim);
if ((Context.HPDState == HPD_STATE_LOW) && (DET_STATE_HIGH == MUX_DET_GetState()))
{
/* Invoke registered callback function */
Context.pfnHPDCallbackFunc(TYPE_C_MUX_2, HPD_STATE_HIGH);
}
if ((Context.HPDState == HPD_STATE_HIGH) && (DET_STATE_LOW == MUX_DET_GetState()))
{
/* Invoke registered callback function */
Context.pfnHPDCallbackFunc(TYPE_C_MUX_2, HPD_STATE_LOW);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0c1e_eval_mux.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the
* stm32g0c1e_eval_mux.c firmware driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0C1E_EVAL_MUX_H
#define STM32G0C1E_EVAL_MUX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx.h"
#include "../Components/sn65dp141/sn65dp141.h"
#include "../Components/cbtl08gp053/cbtl08gp053.h"
#include "../Components/tusb546/tusb546.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM32G0C1E_EVAL
* @{
*/
/** @defgroup STM32G0C1E_EVAL_MUX STM32G0C1E_EVAL MUX
* @{
*/
/** @defgroup STM32G0C1E_EVAL_MUX_Exported_Defines Exported Defines
* @{
*/
#define MUX_1_EQGAIN_MAX TUSB546_EQGAIN_15
#define MUX_2_EQGAIN_MAX SN65DP141_EQGAIN_7
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_MUX_Exported_Types Exported Types
* @{
*/
/**
* @brief MUX Status
*/
typedef enum
{
MUX_OK = 0,
MUX_ERROR
} MUX_StatusTypeDef;
/**
* @brief Type-C MUX identifier
*/
typedef enum
{
TYPE_C_MUX_1 = 0,
TYPE_C_MUX_2,
TYPE_C_MUX_NB
} MUX_TypeCMuxIdTypeDef;
/**
* @brief Type-C connector pin assignments
*/
typedef enum
{
DFP_PIN_ASSIGNMMENT_A = 0, /*!< USB Type-C to USB Type-C or Protocol Converter */
DFP_PIN_ASSIGNMMENT_B, /*!< USB Type-C to USB Type-C or Protocol Converter */
DFP_PIN_ASSIGNMMENT_C, /*!< USB Type-C to USB Type-C or Protocol Converter */
DFP_PIN_ASSIGNMMENT_D, /*!< USB Type-C to USB Type-C or Protocol Converter */
DFP_PIN_ASSIGNMMENT_E, /*!< USB Type-C to DisplayPort */
DFP_PIN_ASSIGNMMENT_F, /*!< USB Type-C to DisplayPort */
UFP_PIN_ASSIGNMMENT_A, /*!< USB Type-C to USB Type-C or Protocol Converter */
UFP_PIN_ASSIGNMMENT_B, /*!< USB Type-C to USB Type-C or Protocol Converter */
UFP_PIN_ASSIGNMMENT_C, /*!< USB Type-C to USB Type-C or Protocol Converter */
UFP_PIN_ASSIGNMMENT_D, /*!< USB Type-C to USB Type-C or Protocol Converter */
UFP_PIN_ASSIGNMMENT_E, /*!< USB Type-C to USB Type-C or Protocol Converter */
UFP_PIN_ASSIGNMMENT_F, /*!< USB Type-C to USB Type-C or Protocol Converter */
USB_ONLY_PIN_ASSIGNMMENT /*!< USB 3.1 Only */
} MUX_TypeCConnectorPinAssignmentTypeDef;
/**
* @brief Type-C port plug orientation
*/
typedef enum
{
PLUG_ORIENTATION_NORMAL = 0,
PLUG_ORIENTATION_FLIPPED
} MUX_TypeCPlugOrientationTypeDef;
/**
* @brief HDP (Hot Plug Detection) state
*/
typedef enum
{
HPD_STATE_LOW = 0,
HPD_STATE_HIGH
} MUX_HPDStateTypeDef;
/**
* @brief HPD Callback Function Pointer
*/
typedef void MUX_HPDCallbackFuncTypeDef(MUX_TypeCMuxIdTypeDef TypeCMuxId, MUX_HPDStateTypeDef HPDState);
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_MUX_Exported_Constants Exported Constants
* @{
*/
#define DETn 2
#define DET_HPD_SOURCE_PIN GPIO_PIN_6 /* PC.06 */
#define DET_HPD_SOURCE_GPIO_PORT GPIOC
#define DET_HPD_SOURCE_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define DET_HPD_SOURCE_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
#define DET_EXTI_IRQn EXTI4_15_IRQn
#define DET_EXTI_IRQHandler EXTI4_15_IRQHandler
#define SELn 1
#define SEL_HPDIN_PIN GPIO_PIN_5 /* PB.05 */
#define SEL_HPDIN_GPIO_PORT GPIOB
#define SEL_HPDIN_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define SEL_HPDIN_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
#define DEBOUNCE_TIM_INSTANCE TIM6
#define DEBOUNCE_TIM_CLK_ENABLE() __HAL_RCC_TIM6_CLK_ENABLE()
#define DEBOUNCE_TIM_CLK_DISABLE() __HAL_RCC_TIM6_CLK_DISABLE()
#define DEBOUNCE_TIM_COUNTER_CLK_FREQ() HAL_RCC_GetPCLK1Freq()
#define DEBOUNCE_TIM_IRQn TIM6_DAC_LPTIM1_IRQn
#define DEBOUNCE_TIME 1000u /* 1ms */
#define DEBOUNCE_TIM_IRQHandler TIM6_DAC_LPTIM1_IRQHandler
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_MUX_Exported_Variables Exported Variables
* @{
*/
extern TIM_HandleTypeDef htim;
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_MUX_Exported_Functions Exported Functions
* @{
*/
MUX_StatusTypeDef BSP_MUX_Init(MUX_TypeCMuxIdTypeDef TypeCMuxId);
MUX_StatusTypeDef BSP_MUX_DeInit(MUX_TypeCMuxIdTypeDef TypeCMuxId);
MUX_StatusTypeDef BSP_MUX_Enable(MUX_TypeCMuxIdTypeDef TypeCMuxId);
MUX_StatusTypeDef BSP_MUX_Disable(MUX_TypeCMuxIdTypeDef TypeCMuxId);
MUX_StatusTypeDef BSP_MUX_SetDPPinAssignment(MUX_TypeCMuxIdTypeDef TypeCMuxId,
MUX_TypeCPlugOrientationTypeDef TypeCPlugOrientation,
MUX_TypeCConnectorPinAssignmentTypeDef TypeCConnectorPinAssignment);
MUX_StatusTypeDef BSP_MUX_SetEQGain(MUX_TypeCMuxIdTypeDef TypeCMuxId,
uint8_t EQGain);
MUX_StatusTypeDef BSP_MUX_SetHPDState(MUX_TypeCMuxIdTypeDef TypeCMuxId,
MUX_HPDStateTypeDef HPDState);
MUX_StatusTypeDef BSP_MUX_GetHPDState(MUX_TypeCMuxIdTypeDef TypeCMuxId,
MUX_HPDStateTypeDef * pHPDState);
MUX_StatusTypeDef BSP_MUX_HPDIRQ(MUX_TypeCMuxIdTypeDef TypeCMuxId);
void BSP_MUX_Detect_HPD(void);
MUX_StatusTypeDef BSP_MUX_RegisterHPDCallbackFunc(MUX_TypeCMuxIdTypeDef TypeCMuxId,
MUX_HPDCallbackFuncTypeDef * pHPDCallbackFunc);
#if defined(TUSB546_DEBUG) || defined(CBTL08GP053_DEBUG) || defined(SN65DP141_DEBUG)
#define DEVICE_CBTL08GP053 0x00000001U
#define DEVICE_SN65DP141 0x00000002U
#define DEVICE_TUSB546 0x00000004U
void BSP_MUX_DumpDeviceRegisters(uint32_t Device);
#endif /* TUSB546_DEBUG || CBTL08GP053_DEBUG || SN65DP141_DEBUG */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0C1E_EVAL_MUX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32g0c1e_eval_pwr.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the
* stm32g0c1e_eval_pwr.c firmware driver.
******************************************************************************
*
* <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0C1E_EVAL_POWER
#define STM32G0C1E_EVAL_POWER
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM32G0C1E_EVAL
* @{
*/
/** @defgroup STM32G0C1E_EVAL_POWER STM32G0C1E_EVAL POWER
* @{
*/
/** @defgroup STM32G0C1E_EVAL_POWER_Exported_Types Exported Types based on BSP V1 specification (keep for legacy)
* @{
*/
/**
* @brief POWER Status
*/
typedef enum
{
PWR_OK = 0,
PWR_ERROR
} PWR_StatusTypeDef;
/**
* @brief Power role
*/
#define PWR_PowerRoleTypeDef USBPD_PWR_PowerRoleTypeDef
/**
* @brief Voltage control mode
*/
#define PWR_DCDCCtrlModeTypeDef USBPD_PWR_DCDCCtrlModeTypeDef
/**
* @brief VBUS connection status
*/
#define PWR_VBUSConnectionStatusTypeDef USBPD_PWR_VBUSConnectionStatusTypeDef
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_POWER_Exported_Types2 Exported Types based on BSP V2 secification
*@{
*/
/**
* @brief Power role
*/
typedef enum
{
POWER_ROLE_SOURCE = 0,
POWER_ROLE_SINK,
POWER_ROLE_DUAL
}
USBPD_PWR_PowerRoleTypeDef;
/**
* @brief Voltage control mode
*/
typedef enum
{
DCDC_CTRL_MODE_UNKNOWN = 0,
DCDC_CTRL_MODE_GPIO,
DCDC_CTRL_MODE_PWM,
} USBPD_PWR_DCDCCtrlModeTypeDef;
/**
* @brief VBUS connection status
*/
typedef enum
{
VBUS_CONNECTED = 0,
VBUS_NOT_CONNECTED
} USBPD_PWR_VBUSConnectionStatusTypeDef;
/* Keep for Legacy BSP V1 */
/**
* @brief VBUS Detection Callback
*/
typedef void PWR_VBUSDetectCallbackFunc(uint32_t Instance,
PWR_VBUSConnectionStatusTypeDef VBUSConnectionStatus);
/**
* @brief VBUS Detection Callback
*/
typedef void USBPD_PWR_VBUSDetectCallbackFunc(uint32_t Instance,
USBPD_PWR_VBUSConnectionStatusTypeDef VBUSConnectionStatus);
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_POWER_Exported_Constants Exported Constants based on BSP V1 specification (keep for legacy)
* @{
*/
/**
* @brief Number of TypeC ports
*/
#define PWR_TYPEC_PORT_NB USBPD_PWR_INSTANCES_NBR
/**
* @brief Type-C port identifier
*/
#define TYPE_C_PORT_1 USBPD_PWR_TYPE_C_PORT_1
#define TYPE_C_PORT_2 USBPD_PWR_TYPE_C_PORT_2
/**
* @brief CC pin identifier
*/
#define TYPE_C_CC1 USBPD_PWR_TYPE_C_CC1
#define TYPE_C_CC2 USBPD_PWR_TYPE_C_CC2
/**
* @brief VBUS disconnection threshold values (in mV)
*/
#define BSP_PWR_HIGH_VBUS_THRESHOLD USBPD_PWR_HIGH_VBUS_THRESHOLD
#define BSP_PWR_LOW_VBUS_THRESHOLD USBPD_PWR_LOW_VBUS_THRESHOLD
/**
* @brief VBUS discharge parameters
*/
#define BSP_PWR_DISCHARGE_MARGIN USBPD_PWR_DISCHARGE_MARGIN
#define BSP_PWR_DISCHARGE_TIME USBPD_PWR_DISCHARGE_TIME
/**
* @brief Calibration settings
*/
#define BSP_PWR_DCDC_PRECISION USBPD_PWR_DCDC_PRECISION
#define BSP_PWR_CALIBRATION_ENABLED USBPD_PWR_CALIBRATION_ENABLED
#define BSP_PWR_CALIBRATION_DISABLED USBPD_PWR_CALIBRATION_DISABLED
/**
* @brief power timeout
*/
#define BSP_PWR_TIMEOUT_PDO USBPD_PWR_TIMEOUT_PDO
#define BSP_PWR_TIMEOUT_APDO USBPD_PWR_TIMEOUT_APDO
/**
* @brief Invalid value set during issue with voltage setting
*/
#define BSP_PWR_INVALID_VALUE USBPD_PWR_INVALID_VALUE
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_USBPD_PWR_Exported_Constants2 Exported Constants on BSP V2 specification
@{
*/
/* Defines error for BSP V2 (copy for legacy reasons) */
/* Common Error codes */
#ifndef BSP_ERROR_NONE
#define BSP_ERROR_NONE 0
#endif
#ifndef BSP_ERROR_NO_INIT
#define BSP_ERROR_NO_INIT -1
#endif
#ifndef BSP_ERROR_WRONG_PARAM
#define BSP_ERROR_WRONG_PARAM -2
#endif
#ifndef BSP_ERROR_PERIPH_FAILURE
#define BSP_ERROR_PERIPH_FAILURE -4
#endif
#ifndef BSP_ERROR_FEATURE_NOT_SUPPORTED
#define BSP_ERROR_FEATURE_NOT_SUPPORTED -11
#endif
/**
* @brief Number of TypeC ports
*/
#define USBPD_PWR_INSTANCES_NBR 2u
/**
* @brief Type-C port identifier
*/
#define USBPD_PWR_TYPE_C_PORT_1 0u
#define USBPD_PWR_TYPE_C_PORT_2 1u
/**
* @brief CC pin identifier
*/
#define USBPD_PWR_TYPE_C_CC1 1u
#define USBPD_PWR_TYPE_C_CC2 2u
/**
* @brief VBUS disconnection threshold values (in mV)
*/
#define USBPD_PWR_HIGH_VBUS_THRESHOLD (2800u)
#define USBPD_PWR_LOW_VBUS_THRESHOLD (750U)
#define USBPD_PWR_VBUS_THRESHOLD_5V (3900u)
#define USBPD_PWR_VBUS_THRESHOLD_9V (7000u)
#define USBPD_PWR_VBUS_THRESHOLD_15V (12500u)
#define USBPD_PWR_VBUS_THRESHOLD_20V (17000u)
#define USBPD_PWR_VBUS_THRESHOLD_APDO (2150u)
/**
* @brief VBUS discharge parameters
*/
#define USBPD_PWR_DISCHARGE_MARGIN (500u)
#define USBPD_PWR_DISCHARGE_TIME (6u)
/**
* @brief Calibration settings
*/
#define USBPD_PWR_DCDC_PRECISION (20u) /* DCDC output precision set to 20mV (Noise)*/
#define USBPD_PWR_CALIBRATION_ENABLED (1u)
#define USBPD_PWR_CALIBRATION_DISABLED (0u)
/**
* @brief Standard VBUS voltage levels
*/
#define USBPD_PWR_VBUS_5V 5000u
#define USBPD_PWR_VBUS_9V 9000u
#define USBPD_PWR_VBUS_15V 15000u
/**
* @brief power timeout
*/
#define USBPD_PWR_TIMEOUT_PDO 250u /* Timeout for PDO to PDO or PDO to APDO at 250ms*/
#define USBPD_PWR_TIMEOUT_APDO 25u /* Timeout for APDO to APDO at 25ms*/
/**
* @brief Invalid value set during issue with voltage setting
*/
#define USBPD_PWR_INVALID_VALUE 0xFFFFFFFFu
#define GPIO_SOURCE_EN_PIN GPIO_PIN_3 /* PD.03 */
#define GPIO_SOURCE_EN_PORT GPIOD
#define GPIO_SOURCE_EN_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
#define GPIO_VBUS_DISCHARGE1_PIN GPIO_PIN_13 /* PB.13 */
#define GPIO_VBUS_DISCHARGE1_PORT GPIOB
#define GPIO_VBUS_DISCHARGE1_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define GPIO_VBUS_DISCHARGE2_PIN GPIO_PIN_14 /* PB.14 */
#define GPIO_VBUS_DISCHARGE2_PORT GPIOB
#define GPIO_VBUS_DISCHARGE2_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define GPIO_VCONN_EN1_PIN GPIO_PIN_4 /* PD.04 */
#define GPIO_VCONN_EN1_PORT GPIOD
#define GPIO_VCONN_EN1_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
#define GPIO_VCONN_EN2_PIN GPIO_PIN_9 /* PB.09 */
#define GPIO_VCONN_EN2_PORT GPIOB
#define GPIO_VCONN_EN2_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define GPIO_VCONN_DISCHARGE1_PIN GPIO_PIN_2 /* PA.02 */
#define GPIO_VCONN_DISCHARGE1_PORT GPIOA
#define GPIO_VCONN_DISCHARGE1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define GPIO_VCONN_DISCHARGE2_PIN GPIO_PIN_0 /* PB.00 */
#define GPIO_VCONN_DISCHARGE2_PORT GPIOB
#define GPIO_VCONN_DISCHARGE2_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define GPIO_V_CTL2_PIN GPIO_PIN_1 /* PA.01 */
#define GPIO_V_CTL2_PORT GPIOA
#define GPIO_V_CTL2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define GPIO_V_CTL1_PIN GPIO_PIN_1 /* PC.01 */
#define GPIO_V_CTL1_PORT GPIOC
#define GPIO_V_CTL1_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
/* Definition of ADCx clock resources */
#define ADCx ADC1
#define ADCx_CLK_ENABLE() __HAL_RCC_ADC_CLK_ENABLE()
#define ADCx_CLK_DISABLE() __HAL_RCC_ADC_CLK_DISABLE()
#define ADCx_FORCE_RESET() __HAL_RCC_ADC_FORCE_RESET()
#define ADCx_RELEASE_RESET() __HAL_RCC_ADC_RELEASE_RESET()
/* Definition of ADCx channels */
#define ADCx_CHANNEL_VSENSE_1 ADC_CHANNEL_9
#define ADCx_CHANNEL_ISENSE_1 ADC_CHANNEL_11
#define ADCx_CHANNEL_VSENSE_2 ADC_CHANNEL_3
#define ADCx_CHANNEL_ISENSE_2 ADC_CHANNEL_16
#define ADCx_CHANNEL_VSENSE_DCDC ADC_CHANNEL_15
/* Definition of ADCx channels */
#define ADCxChanneln 5u
#define ADCx_CHANNEL_VSENSE_1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define ADCx_CHANNEL_VSENSE_1_GPIO_PORT GPIOB
#define ADCx_CHANNEL_VSENSE_1_GPIO_PIN GPIO_PIN_1
#define ADCx_CHANNEL_ISENSE_1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define ADCx_CHANNEL_ISENSE_1_GPIO_PORT GPIOB
#define ADCx_CHANNEL_ISENSE_1_GPIO_PIN GPIO_PIN_10
#define ADCx_CHANNEL_VSENSE_2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define ADCx_CHANNEL_VSENSE_2_GPIO_PORT GPIOA
#define ADCx_CHANNEL_VSENSE_2_GPIO_PIN GPIO_PIN_3
#define ADCx_CHANNEL_ISENSE_2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define ADCx_CHANNEL_ISENSE_2_GPIO_PORT GPIOB
#define ADCx_CHANNEL_ISENSE_2_GPIO_PIN GPIO_PIN_12
#define ADCx_CHANNEL_VSENSE_DCDC_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define ADCx_CHANNEL_VSENSE_DCDC_GPIO_PORT GPIOB
#define ADCx_CHANNEL_VSENSE_DCDC_GPIO_PIN GPIO_PIN_11
/* Definition of ADCx DMA resources */
#define ADCx_DMA_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
#define ADCx_DMA DMA1_Channel1
/* Definition of DMA NVIC resources */
#define ADCx_DMA_IRQn DMA1_Channel1_IRQn
#define ADCx_DMA_IRQHandler DMA1_Channel1_IRQHandler
/* Definition of ADCx NVIC resources */
#define ADCx_IRQn ADC1_COMP_IRQn
#define ADCx_IRQHandler ADC1_COMP_IRQHandler
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_POWER_Exported_Functions Exported Functions based on BSP V1 specification (keep for legacy)
* @{
*/
PWR_StatusTypeDef BSP_PWR_Init(uint32_t PortId);
PWR_StatusTypeDef BSP_PWR_VBUSInit(uint32_t PortId);
PWR_StatusTypeDef BSP_PWR_VBUSDeInit(uint32_t PortId);
void BSP_PWR_VBUSIsGPIO(uint32_t *voltage1, uint32_t *voltage2, uint32_t *voltage3);
PWR_StatusTypeDef BSP_PWR_VBUSOn(uint32_t PortId);
PWR_StatusTypeDef BSP_PWR_VBUSOff(uint32_t PortId);
PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_Fixed(uint32_t PortNum,
uint32_t VbusTargetInmv,
uint32_t OperatingCurrent,
uint32_t MaxOperatingCurrent);
PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_Variable(uint32_t PortNum,
uint32_t VbusTargetMaxInmv,
uint32_t VbusTargetMinInmv,
uint32_t OperatingCurrent,
uint32_t MaxOperatingCurrent);
PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_Battery(uint32_t PortId,
uint32_t VbusTargetMin,
uint32_t VbusTargetMax,
uint32_t OperatingPower,
uint32_t MaxOperatingPower);
PWR_StatusTypeDef BSP_PWR_VBUSSetVoltage_APDO(uint32_t PortId,
uint32_t VbusTargetInmv,
uint32_t OperatingCurrent,
int32_t Delta);
uint32_t BSP_PWR_VBUSGetVoltage(uint32_t PortId);
int32_t BSP_PWR_VBUSGetCurrent(uint32_t PortId);
PWR_StatusTypeDef BSP_PWR_VCONNInit(uint32_t PortId,
uint32_t CCPinId);
PWR_StatusTypeDef BSP_PWR_VCONNDeInit(uint32_t PortId,
uint32_t CCPinId);
PWR_StatusTypeDef BSP_PWR_VCONNOn(uint32_t PortId,
uint32_t CCPinId);
PWR_StatusTypeDef BSP_PWR_VCONNOff(uint32_t PortId,
uint32_t CCPinId);
void BSP_PWR_SetVBUSDisconnectionThreshold(uint32_t PortId,
uint32_t VoltageThreshold);
PWR_StatusTypeDef BSP_PWR_RegisterVBUSDetectCallback(uint32_t PortId,
PWR_VBUSDetectCallbackFunc * pfnVBUSDetectCallback);
uint8_t BSP_PWR_VBUSIsOn(uint32_t PortId);
uint8_t BSP_PWR_VCONNIsOn(uint32_t PortId,
uint32_t CCPinId);
uint32_t BSP_PWR_DCDCGetVoltage(uint32_t PortId);
PWR_DCDCCtrlModeTypeDef BSP_PWR_DCDCGetCtrlMode(uint32_t PortId);
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_USBPD_POWER_Exported_Functions2 Exported Functions based on BSP V2 specification
* @{
*/
/* Common functions */
int32_t BSP_USBPD_PWR_Init(uint32_t Instance);
int32_t BSP_USBPD_PWR_Deinit(uint32_t Instance);
int32_t BSP_USBPD_PWR_VBUSInit(uint32_t Instance);
int32_t BSP_USBPD_PWR_VBUSDeInit(uint32_t Instance);
int32_t BSP_USBPD_PWR_VBUSOn(uint32_t Instance);
int32_t BSP_USBPD_PWR_VBUSOff(uint32_t Instance);
int32_t BSP_USBPD_PWR_VBUSSetVoltage_Fixed(uint32_t Instance,
uint32_t VbusTargetInmv,
uint32_t OperatingCurrent,
uint32_t MaxOperatingCurrent);
int32_t BSP_USBPD_PWR_VBUSSetVoltage_Variable(uint32_t Instance,
uint32_t VbusTargetMaxInmv,
uint32_t VbusTargetMinInmv,
uint32_t OperatingCurrent,
uint32_t MaxOperatingCurrent);
int32_t BSP_USBPD_PWR_VBUSSetVoltage_Battery(uint32_t Instance,
uint32_t VbusTargetMin,
uint32_t VbusTargetMax,
uint32_t OperatingPower,
uint32_t MaxOperatingPower);
int32_t BSP_USBPD_PWR_VBUSSetVoltage_APDO(uint32_t Instance,
uint32_t VbusTargetInmv,
uint32_t OperatingCurrent,
int32_t Delta);
int32_t BSP_USBPD_PWR_VBUSGetVoltage(uint32_t Instance, uint32_t *pVoltage);
int32_t BSP_USBPD_PWR_VBUSGetCurrent(uint32_t Instance, int32_t *pCurrent);
int32_t BSP_USBPD_PWR_VCONNInit(uint32_t Instance,
uint32_t CCPinId);
int32_t BSP_USBPD_PWR_VCONNDeInit(uint32_t Instance,
uint32_t CCPinId);
int32_t BSP_USBPD_PWR_VCONNOn(uint32_t Instance,
uint32_t CCPinId);
int32_t BSP_USBPD_PWR_VCONNOff(uint32_t Instance,
uint32_t CCPinId);
int32_t BSP_USBPD_PWR_SetVBUSDisconnectionThreshold(uint32_t Instance,
uint32_t VoltageThreshold);
int32_t BSP_USBPD_PWR_RegisterVBUSDetectCallback(uint32_t Instance,
USBPD_PWR_VBUSDetectCallbackFunc *pfnVBUSDetectCallback);
int32_t BSP_USBPD_PWR_VBUSIsOn(uint32_t Instance, uint8_t *pState);
int32_t BSP_USBPD_PWR_VCONNIsOn(uint32_t Instance,
uint32_t CCPinId, uint8_t *pState);
int32_t BSP_USBPD_PWR_DCDCGetCtrlMode(uint32_t Instance, USBPD_PWR_DCDCCtrlModeTypeDef *pDCDCCtrl);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0C1E_EVAL_POWER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0c1e_eval_sd.h
* @author MCD Application Team
* @brief This file contains the common defines and functions prototypes for
* the STM32G0C1E_EVAL_sd.c driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0C1E_EVAL_SD_H
#define STM32G0C1E_EVAL_SD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0c1e_eval.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM32G0C1E_EVAL
* @{
*/
/** @defgroup STM32G0C1E_EVAL_SD STM32G0C1E_EVAL SD
* @{
*/
/** @defgroup STM32G0C1E_EVAL_SD_Exported_Types Exported Types
* @{
*/
/**
* @brief SD status structure definition
*/
enum {
BSP_SD_OK = 0x00,
MSD_OK = 0x00,
BSP_SD_ERROR = 0x01,
MSD_ERROR = 0x01,
BSP_SD_TIMEOUT
};
/**
* @brief SD transfer state definition
*/
#define SD_TRANSFER_OK ((uint8_t)0x00)
#define SD_TRANSFER_BUSY ((uint8_t)0x01)
#define SD_TRANSFER_ERROR ((uint8_t)0x02)
/**
* @}
*/
/**
* @brief SD status structure definition
*/
typedef struct
{
uint8_t Reserved1:2; /* Reserved */
uint16_t DeviceSize:12; /* Device Size */
uint8_t MaxRdCurrentVDDMin:3; /* Max. read current @ VDD min */
uint8_t MaxRdCurrentVDDMax:3; /* Max. read current @ VDD max */
uint8_t MaxWrCurrentVDDMin:3; /* Max. write current @ VDD min */
uint8_t MaxWrCurrentVDDMax:3; /* Max. write current @ VDD max */
uint8_t DeviceSizeMul:3; /* Device size multiplier */
} struct_v1;
typedef struct
{
uint8_t Reserved1:6; /* Reserved */
uint32_t DeviceSize:22; /* Device Size */
uint8_t Reserved2:1; /* Reserved */
} struct_v2;
/**
* @brief Card Specific Data: CSD Register
*/
typedef struct
{
/* Header part */
uint8_t CSDStruct:2; /* CSD structure */
uint8_t Reserved1:6; /* Reserved */
uint8_t TAAC:8; /* Data read access-time 1 */
uint8_t NSAC:8; /* Data read access-time 2 in CLK cycles */
uint8_t MaxBusClkFrec:8; /* Max. bus clock frequency */
uint16_t CardComdClasses:12; /* Card command classes */
uint8_t RdBlockLen:4; /* Max. read data block length */
uint8_t PartBlockRead:1; /* Partial blocks for read allowed */
uint8_t WrBlockMisalign:1; /* Write block misalignment */
uint8_t RdBlockMisalign:1; /* Read block misalignment */
uint8_t DSRImpl:1; /* DSR implemented */
/* v1 or v2 struct */
union csd_version {
struct_v1 v1;
struct_v2 v2;
} version;
uint8_t EraseSingleBlockEnable:1; /* Erase single block enable */
uint8_t EraseSectorSize:7; /* Erase group size multiplier */
uint8_t WrProtectGrSize:7; /* Write protect group size */
uint8_t WrProtectGrEnable:1; /* Write protect group enable */
uint8_t Reserved2:2; /* Reserved */
uint8_t WrSpeedFact:3; /* Write speed factor */
uint8_t MaxWrBlockLen:4; /* Max. write data block length */
uint8_t WriteBlockPartial:1; /* Partial blocks for write allowed */
uint8_t Reserved3:5; /* Reserved */
uint8_t FileFormatGrouop:1; /* File format group */
uint8_t CopyFlag:1; /* Copy flag (OTP) */
uint8_t PermWrProtect:1; /* Permanent write protection */
uint8_t TempWrProtect:1; /* Temporary write protection */
uint8_t FileFormat:2; /* File Format */
uint8_t Reserved4:2; /* Reserved */
uint8_t crc:7; /* Reserved */
uint8_t Reserved5:1; /* always 1*/
} SD_CSD;
/**
* @brief Card Identification Data: CID Register
*/
typedef struct
{
__IO uint8_t ManufacturerID; /* ManufacturerID */
__IO uint16_t OEM_AppliID; /* OEM/Application ID */
__IO uint32_t ProdName1; /* Product Name part1 */
__IO uint8_t ProdName2; /* Product Name part2*/
__IO uint8_t ProdRev; /* Product Revision */
__IO uint32_t ProdSN; /* Product Serial Number */
__IO uint8_t Reserved1; /* Reserved1 */
__IO uint16_t ManufactDate; /* Manufacturing Date */
__IO uint8_t CID_CRC; /* CID CRC */
__IO uint8_t Reserved2; /* always 1 */
} SD_CID;
/**
* @brief SD Card information
*/
typedef struct
{
SD_CSD Csd;
SD_CID Cid;
uint32_t CardCapacity; /*!< Card Capacity */
uint32_t CardBlockSize; /*!< Card Block Size */
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
} SD_CardInfo;
/** @defgroup STM32G0C1E_EVAL_SPI_SD_Exported_Constants Exported Constants
* @{
*/
/**
* @brief Block Size
*/
#define SD_BLOCK_SIZE 0x200
/**
* @brief SD detection on its memory slot
*/
#define SD_PRESENT ((uint8_t)0x01)
#define SD_NOT_PRESENT ((uint8_t)0x00)
#define SD_DATATIMEOUT ((uint32_t)100000000)
/**
* @brief SD Card information structure
*/
#define BSP_SD_CardInfo SD_CardInfo
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_SD_Exported_Functions Exported Functions
* @{
*/
uint8_t BSP_SD_Init(void);
uint8_t BSP_SD_IsDetected(void);
uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout);
uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout);
uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr);
uint8_t BSP_SD_GetCardState(void);
uint8_t BSP_SD_GetCardInfo(SD_CardInfo *pCardInfo);
/* Link functions for SD Card peripheral */
void SD_IO_Init(void);
void SD_IO_CSState(uint8_t state);
void SD_IO_WriteReadData(const uint8_t *DataIn, uint8_t *DataOut, uint16_t DataLength);
uint8_t SD_IO_WriteByte(uint8_t Data);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0C1E_EVAL_SD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0c1e_eval_tsensor.c
* @author MCD Application Team
* @brief This file provides a set of functions needed to manage the I2C STLM75
* temperature sensor mounted on STM32G0C1E-EV board .
* It implements a high level communication layer for read and write
* from/to this sensor. The needed STM32G0xx hardware resources (I2C and
* GPIO) are defined in stm32g0c1e_eval.h file, and the initialization is
* performed in TSENSOR_IO_Init() function declared in stm32g0c1e_eval.c
* file.
* You can easily tailor this driver to any other development board,
* by just adapting the defines for hardware resources and
* TSENSOR_IO_Init() function.
*
* +-----------------------------------------------------------------+
* | Pin assignment |
* +---------------------------------------+-----------+-------------+
* | STM32G0xx I2C Pins | STLM75 | Pin |
* +---------------------------------------+-----------+-------------+
* | STLM75_I2C_SDA_PIN/ SDA | SDA | 1 |
* | STLM75_I2C_SCL_PIN/ SCL | SCL | 2 |
* | STLM75_I2C_SMBUSALERT_PIN/ SMBUS ALERT| OS/INT | 3 |
* | . | GND | 4 (0V) |
* | . | GND | 5 (0V) |
* | . | GND | 6 (0V) |
* | . | GND | 7 (0V) |
* | . | VDD | 8 (3.3V)|
* +---------------------------------------+-----------+-------------+
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g0c1e_eval_tsensor.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM32G0C1E_EVAL
* @{
*/
/** @addtogroup STM32G0C1E_EVAL_TSENSOR
* @brief This file includes the STLM75 Temperature Sensor driver of
* STM32G0C1E-EV boards.
* @{
*/
/** @defgroup STM32G0C1E_EVAL_TSENSOR_Private_Variables Private Variables
* @{
*/
static TSENSOR_DrvTypeDef *tsensor_drv;
__IO uint16_t TSENSORAddress = 0;
/**
* @}
*/
/** @addtogroup STM32G0C1E_EVAL_TSENSOR_Exported_Functions
* @{
*/
/**
* @brief Initializes peripherals used by the I2C Temperature Sensor driver.
* @retval TSENSOR status
*/
uint32_t BSP_TSENSOR_Init(void)
{
uint8_t ret = TSENSOR_ERROR;
TSENSOR_InitTypeDef STLM75_InitStructure;
/* Temperature Sensor Initialization */
if(Stlm75Drv.IsReady(TSENSOR_I2C_ADDRESS_A01, TSENSOR_MAX_TRIALS) == HAL_OK)
{
/* Initialize the temperature sensor driver structure */
TSENSORAddress = TSENSOR_I2C_ADDRESS_A01;
tsensor_drv = &Stlm75Drv;
ret = TSENSOR_OK;
}
else
{
if(Stlm75Drv.IsReady(TSENSOR_I2C_ADDRESS_A02, TSENSOR_MAX_TRIALS) == HAL_OK)
{
/* Initialize the temperature sensor driver structure */
TSENSORAddress = TSENSOR_I2C_ADDRESS_A02;
tsensor_drv = &Stlm75Drv;
ret = TSENSOR_OK;
}
else
{
ret = TSENSOR_ERROR;
}
}
if (ret == TSENSOR_OK)
{
/* Configure Temperature Sensor : Conversion 9 bits in continuous mode */
/* Alert outside range Limit Temperature 12° <-> 24°c */
STLM75_InitStructure.AlertMode = STLM75_INTERRUPT_MODE;
STLM75_InitStructure.ConversionMode = STLM75_CONTINUOUS_MODE;
STLM75_InitStructure.TemperatureLimitHigh = 24;
STLM75_InitStructure.TemperatureLimitLow = 12;
/* TSENSOR Init */
tsensor_drv->Init(TSENSORAddress, &STLM75_InitStructure);
ret = TSENSOR_OK;
}
return ret;
}
/**
* @brief Returns the Temperature Sensor status.
* @retval The Temperature Sensor status.
*/
uint8_t BSP_TSENSOR_ReadStatus(void)
{
return (tsensor_drv->ReadStatus(TSENSORAddress));
}
/**
* @brief Read Temperature register of STLM75.
* @retval STLM75 measured temperature value.
*/
float BSP_TSENSOR_ReadTemp(void)
{
return tsensor_drv->ReadTemp(TSENSORAddress);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0c1e_eval_tsensor.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the
* stm32g0c1e_eval_tsensor.c firmware driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0C1E_EVAL_TSENSOR_H
#define STM32G0C1E_EVAL_TSENSOR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0c1e_eval.h"
#include "../Components/stlm75/stlm75.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM32G0C1E_EVAL
* @{
*/
/** @defgroup STM32G0C1E_EVAL_TSENSOR STM32G0C1E_EVAL TSENSOR
* @{
*/
/** @defgroup STM32G0C1E_EVAL_TSENSOR_Exported_Types Exported Types
* @{
*/
/**
* @brief TSENSOR Status
*/
typedef enum
{
TSENSOR_OK = 0,
TSENSOR_ERROR
} TSENSOR_Status_TypDef;
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_TSENSOR_Exported_Constants Exported Constants
* @{
*/
/* Temperature Sensor hardware I2C address */
#define TSENSOR_I2C_ADDRESS_A01 0x90
#define TSENSOR_I2C_ADDRESS_A02 0x92
/* Maximum number of trials use for STTS751_IsReady function */
#define TSENSOR_MAX_TRIALS 50
/**
* @}
*/
/** @defgroup STM32G0C1E_EVAL_TSENSOR_Exported_Functions Exported Functions
* @{
*/
uint32_t BSP_TSENSOR_Init(void);
uint8_t BSP_TSENSOR_ReadStatus(void);
float BSP_TSENSOR_ReadTemp(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0C1E_EVAL_TSENSOR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0xx.h
* @author MCD Application Team
* @brief CMSIS STM32G0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32G0xx device used in the target application
* - To use or not the peripherals drivers in application code(i.e.
* code will be based on direct access to peripherals registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/Apache-2.0
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32g0xx
* @{
*/
#ifndef STM32G0xx_H
#define STM32G0xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32G0)
#define STM32G0
#endif /* STM32G0 */
/* Uncomment the line below according to the target STM32G0 device used in your
application
*/
#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \
&& !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \
&& !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \
&& !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx)
/* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */
/* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */
/* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */
/* #define STM32G070xx */ /*!< STM32G070xx Devices */
/* #define STM32G071xx */ /*!< STM32G071xx Devices */
/* #define STM32G081xx */ /*!< STM32G081xx Devices */
/* #define STM32G050xx */ /*!< STM32G050xx Devices */
/* #define STM32G051xx */ /*!< STM32G051xx Devices */
/* #define STM32G061xx */ /*!< STM32G061xx Devices */
/* #define STM32G030xx */ /*!< STM32G030xx Devices */
/* #define STM32G031xx */ /*!< STM32G031xx Devices */
/* #define STM32G041xx */ /*!< STM32G041xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number $VERSION$
*/
#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
#define __STM32G0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
|(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
|(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32G0_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32G0B1xx)
#include "stm32g0b1xx.h"
#elif defined(STM32G0C1xx)
#include "stm32g0c1xx.h"
#elif defined(STM32G0B0xx)
#include "stm32g0b0xx.h"
#elif defined(STM32G071xx)
#include "stm32g071xx.h"
#elif defined(STM32G081xx)
#include "stm32g081xx.h"
#elif defined(STM32G070xx)
#include "stm32g070xx.h"
#elif defined(STM32G031xx)
#include "stm32g031xx.h"
#elif defined(STM32G041xx)
#include "stm32g041xx.h"
#elif defined(STM32G030xx)
#include "stm32g030xx.h"
#elif defined(STM32G051xx)
#include "stm32g051xx.h"
#elif defined(STM32G061xx)
#include "stm32g061xx.h"
#elif defined(STM32G050xx)
#include "stm32g050xx.h"
#else
#error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32g0xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32G0xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32g0xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M0+ Device System Source File for STM32G0xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/Apache-2.0
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32g0xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef SYSTEM_STM32G0XX_H
#define SYSTEM_STM32G0XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32G0xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*SYSTEM_STM32G0XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.3
* @date 24. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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/**
******************************************************************************
* @file stm32_assert.h
* @author MCD Application Team
* @brief STM32 assert template file.
* This file should be copied to the application folder and renamed
* to stm32_assert.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32_ASSERT_H
#define STM32_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for functions parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* STM32_ASSERT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0xx_HAL_H
#define STM32G0xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_conf.h"
/** @addtogroup STM32G0xx_HAL_Driver
* @{
*/
/** @defgroup HAL HAL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
/** @defgroup SYSCFG_BootMode Boot Mode
* @{
*/
#define SYSCFG_BOOT_MAINFLASH 0x00000000U /*!< Main Flash memory mapped at 0x0000 0000 */
#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x0000 0000 */
#define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x0000 0000 */
/**
* @}
*/
/** @defgroup SYSCFG_Break Break
* @{
*/
#define SYSCFG_BREAK_SP SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM Parity error signal with Break Input of TIM1/15/16/17 */
#if defined(SYSCFG_CFGR2_PVDL)
#define SYSCFG_BREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
#endif /* SYSCFG_CFGR2_PVDL */
#define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/15/16/17 */
#define SYSCFG_BREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC of CortexM0+ with Break Input of TIM1/15/16/17 */
/**
* @}
*/
#if defined(SYSCFG_CDEN_SUPPORT)
/** @defgroup SYSCFG_ClampingDiode Clamping Diode
* @{
*/
#define SYSCFG_CDEN_PA1 SYSCFG_CFGR2_PA1_CDEN /*!< Enables Clamping Diode on PA1 */
#define SYSCFG_CDEN_PA3 SYSCFG_CFGR2_PA3_CDEN /*!< Enables Clamping Diode on PA3 */
#define SYSCFG_CDEN_PA5 SYSCFG_CFGR2_PA5_CDEN /*!< Enables Clamping Diode on PA5 */
#define SYSCFG_CDEN_PA6 SYSCFG_CFGR2_PA6_CDEN /*!< Enables Clamping Diode on PA6 */
#define SYSCFG_CDEN_PA13 SYSCFG_CFGR2_PA13_CDEN /*!< Enables Clamping Diode on PA13 */
#define SYSCFG_CDEN_PB0 SYSCFG_CFGR2_PB0_CDEN /*!< Enables Clamping Diode on PB0 */
#define SYSCFG_CDEN_PB1 SYSCFG_CFGR2_PB1_CDEN /*!< Enables Clamping Diode on PB1 */
#define SYSCFG_CDEN_PB2 SYSCFG_CFGR2_PB2_CDEN /*!< Enables Clamping Diode on PB2 */
/**
* @}
*/
#endif /* SYSCFG_CDEN_SUPPORT */
/** @defgroup HAL_Pin_remapping Pin remapping
* @{
*/
/* Only available on cut2.0 */
#define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves digitally as PA9 GPIO pin */
#define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves digitally as PA10 GPIO pin */
/**
* @}
*/
/** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection
* @{
*/
#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IR Modulation envelope source */
#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */
#if defined(USART4)
#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART4 is selected as IR Modulation envelope source */
#else
#define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */
#endif /* USART4 */
/**
* @}
*/
/** @defgroup HAL_IR_POL_SEL IR output polarity selection
* @{
*/
#define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U /*!< 00: IR output polarity not inverted */
#define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL /*!< 01: IR output polarity inverted */
/**
* @}
*/
#if defined(VREFBUF)
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0: VREF_OUT1 around 2.048 V.
This requires VDDA equal to or higher than 2.4 V. */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1: VREF_OUT1 around 2.5 V.
This requires VDDA equal to or higher than 2.8 V. */
/**
* @}
*/
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
* @{
*/
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
/**
* @}
*/
#endif /* VREFBUF */
/** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO
* @{
*/
/** @brief Fast mode Plus driving capability on a specific GPIO
*/
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast mode Plus on PB6 */
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast mode Plus on PB7 */
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast mode Plus on PB8 */
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast mode Plus on PB9 */
#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast mode Plus on PA9 */
#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */
/**
* @}
*/
/** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx
* @{
*/
/** @brief Fast mode Plus driving capability on a specific GPIO
*/
#define SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */
#define SYSCFG_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast mode Plus on I2C2 */
#if defined (I2C3)
#define SYSCFG_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast mode Plus on I2C3 */
#endif /* I2C3 */
/**
* @}
*/
#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
/** @defgroup SYSCFG_UCPDx_STROBE SYSCFG Dead Battery feature configuration
* @{
*/
#define SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD1 Dead battery sw configuration */
#define SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE /*!< UCPD2 Dead battery sw configuration */
/**
* @}
*/
#endif /* SYSCFG_CFGR1_UCPD1_STROBE) || SYSCFG_CFGR1_UCPD2_STROBE */
/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
* @brief ISR Wrapper
* @{
*/
#define HAL_SYSCFG_ITLINE0 0x00000000U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE1 0x00000001U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE2 0x00000002U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE3 0x00000003U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE4 0x00000004U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE8 0x00000008U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE10 0x0000000AU /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE11 0x0000000BU /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE12 0x0000000CU /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE13 0x0000000DU /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE14 0x0000000EU /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE15 0x0000000FU /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE17 0x00000011U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE18 0x00000012U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE20 0x00000014U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE24 0x00000018U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE25 0x00000019U /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE26 0x0000001AU /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE29 0x0000001DU /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE30 0x0000001EU /*!< Internal define for macro handling */
#define HAL_SYSCFG_ITLINE31 0x0000001FU /*!< Internal define for macro handling */
#define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG) /*!< WWDG has expired .... */
#if defined (PWR_PVD_SUPPORT)
#define HAL_ITLINE_PVDOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT) /*!< Power voltage detection Interrupt .... */
#endif /* PWR_PVD_SUPPORT */
#if defined (PWR_PVM_SUPPORT)
#define HAL_ITLINE_PVMOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVMOUT) /*!< Power voltage monitor Interrupt .... */
#endif /* PWR_PVM_SUPPORT */
#define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC -> exti[19] Interrupt */
#define HAL_ITLINE_TAMPER ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER) /*!< TAMPER -> exti[21] interrupt .... */
#define HAL_ITLINE_FLASH_ECC ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC) /*!< Flash ECC Interrupt */
#define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF) /*!< Flash ITF Interrupt */
#define HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL) /*!< CLK Control Interrupt */
#if defined (CRS)
#define HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS) /*!< CRS Interrupt */
#endif /*CRS */
#define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0) /*!< External Interrupt 0 */
#define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1) /*!< External Interrupt 1 */
#define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2) /*!< External Interrupt 2 */
#define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3) /*!< External Interrupt 3 */
#define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4) /*!< EXTI4 Interrupt */
#define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5) /*!< EXTI5 Interrupt */
#define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6) /*!< EXTI6 Interrupt */
#define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7) /*!< EXTI7 Interrupt */
#define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8) /*!< EXTI8 Interrupt */
#define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9) /*!< EXTI9 Interrupt */
#define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10) /*!< EXTI10 Interrupt */
#define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11) /*!< EXTI11 Interrupt */
#define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12) /*!< EXTI12 Interrupt */
#define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */
#define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */
#define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */
#if defined (UCPD1)
#define HAL_ITLINE_UCPD1 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD1) /*!< UCPD1 Interrupt */
#endif /* UCPD1 */
#if defined (UCPD2)
#define HAL_ITLINE_UCPD2 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD2) /*!< UCPD2 Interrupt */
#endif /* UCPD2 */
#if defined (STM32G0C1xx) || defined (STM32G0B1xx) || defined (STM32G0B0xx)
#define HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB) /*!< USB Interrupt */
#endif /* STM32G0C1xx) || STM32G0B1xx) || STM32G0B0xx */
#define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */
#define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2) /*!< DMA1 Channel 2 Interrupt */
#define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3) /*!< DMA1 Channel 3 Interrupt */
#define HAL_ITLINE_DMAMUX1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX1) /*!< DMAMUX1 Interrupt */
#define HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4) /*!< DMA1 Channel 4 Interrupt */
#define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) /*!< DMA1 Channel 5 Interrupt */
#if defined(DMA1_Channel7)
#define HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6) /*!< DMA1 Channel 6 Interrupt */
#define HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7) /*!< DMA1 Channel 7 Interrupt */
#endif /* DMA1_Channel7 */
#if defined (DMA2)
#define HAL_ITLINE_DMA2_CH1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH1) /*!< DMA2 Channel 1 Interrupt */
#define HAL_ITLINE_DMA2_CH2 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH2) /*!< DMA2 Channel 2 Interrupt */
#define HAL_ITLINE_DMA2_CH3 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3) /*!< DMA2 Channel 3 Interrupt */
#define HAL_ITLINE_DMA2_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4) /*!< DMA2 Channel 4 Interrupt */
#define HAL_ITLINE_DMA2_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5) /*!< DMA2 Channel 5 Interrupt */
#endif /* DMA2 */
#define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */
#if defined (COMP1)
#define HAL_ITLINE_COMP1 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1) /*!< COMP1 Interrupt -> exti[17] */
#endif /* COMP1 */
#if defined (COMP2)
#define HAL_ITLINE_COMP2 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2) /*!< COMP2 Interrupt -> exti[18] */
#endif /* COMP2 */
#if defined (COMP3)
#define HAL_ITLINE_COMP3 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP3) /*!< COMP3 Interrupt -> exti[1x] */
#endif /* COMP3 */
#define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */
#define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */
#define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG) /*!< TIM1 TRG Interrupt */
#define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU) /*!< TIM1 CCU Interrupt */
#define HAL_ITLINE_TIM1_CC ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC) /*!< TIM1 CC Interrupt */
#if defined (TIM2)
#define HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB) /*!< TIM2 Interrupt */
#endif /* TIM2 */
#define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */
#if defined (TIM4)
#define HAL_ITLINE_TIM4 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM4_GLB) /*!< TIM4 Interrupt */
#endif /* TIM4 */
#if defined(TIM6)
#define HAL_ITLINE_TIM6 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB) /*!< TIM6 Interrupt */
#endif /* TIM6 */
#if defined(DAC1)
#define HAL_ITLINE_DAC ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC) /*!< DAC Interrupt */
#endif /* DAC1 */
#if defined(LPTIM1)
#define HAL_ITLINE_LPTIM1 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB) /*!< LPTIM1 Interrupt -> exti[29] */
#endif /* LPTIM1 */
#if defined(TIM7)
#define HAL_ITLINE_TIM7 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB) /*!< TIM7 Interrupt */
#endif /* TIM7 */
#if defined(LPTIM2)
#define HAL_ITLINE_LPTIM2 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB) /*!< LPTIM2 Interrupt -> exti[30] */
#endif /* LPTIM2 */
#define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */
#if defined(TIM15)
#define HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB) /*!< TIM15 Interrupt */
#endif /* TIM15 */
#define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB) /*!< TIM16 Interrupt */
#if defined (FDCAN1) || defined (FDCAN2)
#define HAL_ITLINE_FDCAN1_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN1_IT0) /*!< FDCAN1_IT0 Interrupt */
#define HAL_ITLINE_FDCAN2_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN2_IT0) /*!< FDCAN2_IT0 Interrupt */
#endif /* FDCAN1 || FDCAN2 */
#define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB) /*!< TIM17 Interrupt */
#if defined (FDCAN1) || defined (FDCAN2)
#define HAL_ITLINE_FDCAN1_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN1_IT1) /*!< FDCAN1_IT1 Interrupt */
#define HAL_ITLINE_FDCAN2_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN2_IT1) /*!< FDCAN2_IT1 Interrupt */
#endif /* FDCAN1 || FDCAN2 */
#define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt -> exti[23] */
#define HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB) /*!< I2C2 Interrupt -> exti[24] */
#if defined (I2C3)
#define HAL_ITLINE_I2C3 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C3_GLB) /*!< I2C3 Interrupt -> exti[22] */
#endif /* I2C3 */
#define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1) /*!< SPI1 Interrupt */
#define HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2) /*!< SPI2 Interrupt */
#if defined (SPI3)
#define HAL_ITLINE_SPI3 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI3) /*!< SPI3 Interrupt */
#endif /* SPI3 */
#define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt -> exti[25] */
#define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt -> exti[26] */
#if defined (LPUART2)
#define HAL_ITLINE_LPUART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB) /*!< LPUART2 GLB Interrupt -> exti[26] */
#endif /* LPUART2 */
#if defined(USART3)
#define HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB) /*!< USART3 Interrupt .... */
#endif /* USART3 */
#if defined(USART4)
#define HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB) /*!< USART4 Interrupt .... */
#endif /* USART4 */
#if defined (LPUART1)
#define HAL_ITLINE_LPUART1 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB) /*!< LPUART1 Interrupt -> exti[28]*/
#endif /* LPUART1 */
#if defined (USART5)
#define HAL_ITLINE_USART5 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB) /*!< USART5 Interrupt .... */
#endif /* USART5 */
#if defined (USART6)
#define HAL_ITLINE_USART6 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB) /*!< USART6 Interrupt .... */
#endif /* USART6 */
#if defined (CEC)
#define HAL_ITLINE_CEC ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC) /*!< CEC Interrupt -> exti[27] */
#endif /* CEC */
#if defined (RNG)
#define HAL_ITLINE_RNG ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG) /*!< RNG Interrupt */
#endif /* RNG */
#if defined (AES)
#define HAL_ITLINE_AES ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES) /*!< AES Interrupt */
#endif /* AES */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
*/
/** @defgroup DBG_Exported_Macros DBG Exported Macros
* @{
*/
/** @brief Freeze and Unfreeze Peripherals in Debug mode
*/
#if defined(DBG_APB_FZ1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
#endif /* DBG_APB_FZ1_DBG_TIM2_STOP */
#if defined(DBG_APB_FZ1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
#endif /* DBG_APB_FZ1_DBG_TIM3_STOP */
#if defined(DBG_APB_FZ1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
#endif /* DBG_APB_FZ1_DBG_TIM4_STOP */
#if defined(DBG_APB_FZ1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
#endif /* DBG_APB_FZ1_DBG_TIM6_STOP */
#if defined(DBG_APB_FZ1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
#endif /* DBG_APB_FZ1_DBG_TIM7_STOP */
#if defined(DBG_APB_FZ1_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
#endif /* DBG_APB_FZ1_DBG_RTC_STOP */
#if defined(DBG_APB_FZ1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
#endif /* DBG_APB_FZ1_DBG_WWDG_STOP */
#if defined(DBG_APB_FZ1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
#endif /* DBG_APB_FZ1_DBG_IWDG_STOP */
#if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
#endif /* DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP */
#if defined(DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
#endif /* DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP */
#if defined(DBG_APB_FZ1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
#endif /* DBG_APB_FZ1_DBG_LPTIM1_STOP */
#if defined(DBG_APB_FZ1_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
#endif /* DBG_APB_FZ1_DBG_LPTIM2_STOP */
#if defined(DBG_APB_FZ2_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
#endif /* DBG_APB_FZ2_DBG_TIM1_STOP */
#if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
#endif /* DBG_APB_FZ2_DBG_TIM14_STOP */
#if defined(DBG_APB_FZ2_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
#endif /* DBG_APB_FZ2_DBG_TIM15_STOP */
#if defined(DBG_APB_FZ2_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
#endif /* DBG_APB_FZ2_DBG_TIM16_STOP */
#if defined(DBG_APB_FZ2_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
#endif /* DBG_APB_FZ2_DBG_TIM17_STOP */
/**
* @}
*/
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
* @{
*/
/**
* @brief ISR wrapper check
* @note Allow to determine interrupt source per line.
*/
#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
/** @brief Main Flash memory mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
/** @brief System Flash memory mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
/** @brief Embedded SRAM mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() \
MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0))
/**
* @brief Return the boot mode as configured by user.
* @retval The boot mode as configured by user. The returned value can be one
* of the following values @ref SYSCFG_BootMode
*/
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
/** @brief SYSCFG Break ECC lock.
* Enable and lock the connection of Flash ECC error connection to TIM1 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
/** @brief SYSCFG Break Cortex-M0+ Lockup lock.
* Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
#if defined(SYSCFG_CFGR2_PVDL)
/** @brief SYSCFG Break PVD lock.
* Enables and locks the PVD connection with Timer1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register
* @note The selected configuration is locked and can be unlocked only by system reset
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
#endif /* SYSCFG_CFGR2_PVDL */
/** @brief SYSCFG Break SRAM PARITY lock
* Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17
* @note The selected configuration is locked and can only be unlocked by system reset
*/
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL)
/** @brief Parity check on RAM disable macro
* @note Disabling the parity check on RAM locks the configuration bit.
* To re-enable the parity check on RAM perform a system reset.
*/
#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF)
/** @brief Set the PEF bit to clear the SRAM Parity Error Flag.
*/
#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0U)
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0U)
#if defined(SYSCFG_CDEN_SUPPORT)
/** @brief Clamping Diode on specific pins enable/disable macros
* @param __PIN__ This parameter can be a combination of values @ref SYSCFG_ClampingDiode
*/
#define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
SET_BIT(SYSCFG->CFGR2, (__PIN__));\
}while(0U)
#define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\
}while(0U)
#endif /* SYSCFG_CDEN_SUPPORT */
/** @brief ISR wrapper check
* @note Allow to determine interrupt source per line.
*/
#define __HAL_SYSCFG_GET_PENDING_IT(__SOURCE__) \
(SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFFU))
/** @brief selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register
* @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL
*/
#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\
SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\
}while(0U)
#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U)
/** @brief IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register
* @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL
*/
#define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__) do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\
SET_BIT(SYSCFG->CFGR1,(__SEL__));\
}while(0U)
/**
* @brief Return the IROut Polarity mode as configured by user.
* @retval The IROut polarity as configured by user. The returned value can be one
* of @ref HAL_IR_POL_SEL
*/
#define __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL)
/** @brief Break input to TIM1/15/16/17 capability enable/disable macros
* @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break
*/
#define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
SET_BIT(SYSCFG->CFGR2, (__BREAK__));\
}while(0U)
#define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\
}while(0U)
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
* @{
*/
#if defined (PWR_PVD_SUPPORT)
#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \
((__CONFIG__) == SYSCFG_BREAK_PVD) || \
((__CONFIG__) == SYSCFG_BREAK_ECC) || \
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
#else
#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \
((__CONFIG__) == SYSCFG_BREAK_ECC) || \
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
#endif /* PWR_PVD_SUPPORT */
#if defined(SYSCFG_CDEN_SUPPORT)
#define IS_SYSCFG_CLAMPINGDIODE(__PIN__) ((((__PIN__) & SYSCFG_CDEN_PA1) == SYSCFG_CDEN_PA1) || \
(((__PIN__) & SYSCFG_CDEN_PA3) == SYSCFG_CDEN_PA3) || \
(((__PIN__) & SYSCFG_CDEN_PA5) == SYSCFG_CDEN_PA5) || \
(((__PIN__) & SYSCFG_CDEN_PA6) == SYSCFG_CDEN_PA6) || \
(((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \
(((__PIN__) & SYSCFG_CDEN_PB0) == SYSCFG_CDEN_PB0) || \
(((__PIN__) & SYSCFG_CDEN_PB1) == SYSCFG_CDEN_PB1) || \
(((__PIN__) & SYSCFG_CDEN_PB2) == SYSCFG_CDEN_PB2))
#endif /* SYSCFG_CDEN_SUPPORT */
#if defined (USART4)
#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
#else
#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2))
#endif /* USART4 */
#define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \
((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED))
#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
#define IS_SYSCFG_DBATT_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_UCPD1_STROBE) || \
((__CONFIG__) == SYSCFG_UCPD2_STROBE) || \
((__CONFIG__) == (SYSCFG_UCPD1_STROBE | SYSCFG_UCPD2_STROBE)))
#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
#if defined(VREFBUF)
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#endif /* VREFBUF */
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#define IS_HAL_REMAP_PIN(RMP) (((RMP) == SYSCFG_REMAP_PA11) || \
((RMP) == SYSCFG_REMAP_PA12) || \
((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12)))
/**
* @}
*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
* @{
*/
/* Initialization and Configuration functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions
* @{
*/
/* DBGMCU Peripheral Control functions *****************************************/
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/* Exported variables ---------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions
* @{
*/
/* SYSCFG Control functions ****************************************************/
#if defined(VREFBUF)
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
#endif /* VREFBUF */
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
void HAL_SYSCFG_EnableRemap(uint32_t PinRemap);
void HAL_SYSCFG_DisableRemap(uint32_t PinRemap);
#if defined(SYSCFG_CDEN_SUPPORT)
void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig);
void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig);
#endif /* SYSCFG_CDEN_SUPPORT */
#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery);
#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0xx_HAL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0xx_hal_adc_ex.h
* @author MCD Application Team
* @brief Header file of ADC HAL extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0xx_HAL_ADC_EX_H
#define STM32G0xx_HAL_ADC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_def.h"
/** @addtogroup STM32G0xx_HAL_Driver
* @{
*/
/** @addtogroup ADCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
* @{
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
* @{
*/
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
* @{
*/
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
* @{
*/
/* Macro reserved for internal HAL driver usage, not intended to be used in */
/* code of final user. */
/**
* @brief Check whether or not ADC is independent.
* @param __HANDLE__ ADC handle.
* @note When multimode feature is not available, the macro always returns SET.
* @retval SET (ADC is independent) or RESET (ADC is not).
*/
#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
/**
* @brief Calibration factor size verification (7 bits maximum).
* @param __CALIBRATION_FACTOR__ Calibration factor value.
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
*/
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
/**
* @brief Verify the ADC oversampling ratio.
* @param __RATIO__ programmed ADC oversampling ratio.
* @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
*/
#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
/**
* @brief Verify the ADC oversampling shift.
* @param __SHIFT__ programmed ADC oversampling shift.
* @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
*/
#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
/**
* @brief Verify the ADC oversampling triggered mode.
* @param __MODE__ programmed ADC oversampling triggered mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADCEx_Exported_Functions
* @{
*/
/** @addtogroup ADCEx_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
/* ADC calibration */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/** @addtogroup ADCEx_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0xx_HAL_ADC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0xx_hal_cec.h
* @author MCD Application Team
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0xx_HAL_CEC_H
#define STM32G0xx_HAL_CEC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_def.h"
#if defined (CEC)
/** @addtogroup STM32G0xx_HAL_Driver
* @{
*/
/** @addtogroup CEC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CEC_Exported_Types CEC Exported Types
* @{
*/
/**
* @brief CEC Init Structure definition
*/
typedef struct
{
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
It can be one of @ref CEC_Signal_Free_Time
and belongs to the set {0,...,7} where
0x0 is the default configuration
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
or CEC_EXTENDED_TOLERANCE */
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
CEC_RX_STOP_ON_BRE: reception is stopped. */
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
CEC line upon Bit Rising Error detection.
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
CEC line upon Long Bit Period Error detection.
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
upon an error detected on a broadcast message.
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
b) LBPE detection: error-bit generation on the CEC line
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
there is no error-bit generation in case of Short Bit Period Error detection in
a broadcast message while LSTN bit is set. */
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
own address (OAR). Messages addressed to different destination are ignored.
Broadcast messages are always received.
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
address (OAR) with positive acknowledge. Messages addressed to different destination
are received, but without interfering with the CEC bus: no acknowledge sent. */
uint16_t OwnAddress; /*!< Own addresses configuration
This parameter can be a value of @ref CEC_OWN_ADDRESS */
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
} CEC_InitTypeDef;
/**
* @brief HAL CEC State definition
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7 (not used)
* x : Should be set to 0
* b6 Error information
* 0 : No Error
* 1 : Error
* b5 CEC peripheral initialization status
* 0 : Reset (peripheral not initialized)
* 1 : Init done (peripheral initialized. HAL CEC Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 CEC peripheral initialization status
* 0 : Reset (peripheral not initialized)
* 1 : Init done (peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef uint32_t HAL_CEC_StateTypeDef;
/**
* @brief CEC handle Structure definition
*/
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
typedef struct __CEC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
{
CEC_TypeDef *Instance; /*!< CEC registers base address */
CEC_InitTypeDef Init; /*!< CEC communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
HAL_LockTypeDef Lock; /*!< Locking object */
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
in case error is reported */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
*hcec); /*!< CEC Tx Transfer completed callback */
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
} CEC_HandleTypeDef;
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL CEC Callback ID enumeration definition
*/
typedef enum
{
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
} HAL_CEC_CallbackIDTypeDef;
/**
* @brief HAL CEC Callback pointer definition
*/
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
/** @defgroup CEC_State_Definition CEC State Code Definition
* @{
*/
#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */
/**
* @}
*/
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
* @{
*/
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
/**
* @}
*/
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
* @{
*/
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
/**
* @}
*/
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
* @{
*/
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
/**
* @}
*/
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
* @{
*/
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
/**
* @}
*/
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
* @{
*/
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
/**
* @}
*/
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
* @{
*/
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
/**
* @}
*/
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
* @{
*/
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
/**
* @}
*/
/** @defgroup CEC_Listening_Mode CEC Listening mode option
* @{
*/
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
/**
* @}
*/
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
* @{
*/
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
/**
* @}
*/
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
* @{
*/
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
/**
* @}
*/
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
/**
* @}
*/
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
* @{
*/
#define CEC_IT_TXACKE CEC_IER_TXACKEIE
#define CEC_IT_TXERR CEC_IER_TXERRIE
#define CEC_IT_TXUDR CEC_IER_TXUDRIE
#define CEC_IT_TXEND CEC_IER_TXENDIE
#define CEC_IT_TXBR CEC_IER_TXBRIE
#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define CEC_IT_RXACKE CEC_IER_RXACKEIE
#define CEC_IT_LBPE CEC_IER_LBPEIE
#define CEC_IT_SBPE CEC_IER_SBPEIE
#define CEC_IT_BRE CEC_IER_BREIE
#define CEC_IT_RXOVR CEC_IER_RXOVRIE
#define CEC_IT_RXEND CEC_IER_RXENDIE
#define CEC_IT_RXBR CEC_IER_RXBRIE
/**
* @}
*/
/** @defgroup CEC_Flags_Definitions CEC Flags definition
* @{
*/
#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define CEC_FLAG_TXERR CEC_ISR_TXERR
#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define CEC_FLAG_TXEND CEC_ISR_TXEND
#define CEC_FLAG_TXBR CEC_ISR_TXBR
#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define CEC_FLAG_LBPE CEC_ISR_LBPE
#define CEC_FLAG_SBPE CEC_ISR_SBPE
#define CEC_FLAG_BRE CEC_ISR_BRE
#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define CEC_FLAG_RXEND CEC_ISR_RXEND
#define CEC_FLAG_RXBR CEC_ISR_RXBR
/**
* @}
*/
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
* @{
*/
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
* @{
*/
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
/**
* @}
*/
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
* @{
*/
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CEC_Exported_Macros CEC Exported Macros
* @{
*/
/** @brief Reset CEC handle gstate & RxState
* @param __HANDLE__ CEC handle.
* @retval None
*/
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
} while(0)
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__ specifies the flag to check.
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
* @arg CEC_FLAG_ARBLST: Arbitration Lost
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
* @retval ITStatus
*/
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/** @brief Clears the interrupt or status flag when raised (write at 1)
* @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__ specifies the interrupt/status flag to clear.
* This parameter can be one of the following values:
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
* @arg CEC_FLAG_ARBLST: Arbitration Lost
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
* @retval none
*/
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
/** @brief Enables the specified CEC interrupt.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to enable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** @brief Disables the specified CEC interrupt.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to disable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Checks whether or not the specified CEC interrupt is enabled.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to check.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval FlagStatus
*/
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/** @brief Enables the CEC device
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
/** @brief Disables the CEC device
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
/** @brief Set Transmission Start flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
/** @brief Set Transmission End flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
*/
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
/** @brief Get Transmission Start flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
/** @brief Get Transmission End flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
/** @brief Clear OAR register
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
* @param __HANDLE__ specifies the CEC Handle.
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
* @retval none
*/
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CEC_Exported_Functions
* @{
*/
/** @addtogroup CEC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
pCEC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup CEC_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/** @addtogroup CEC_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CEC_Private_Types CEC Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CEC_Private_Variables CEC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CEC_Private_Constants CEC Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CEC_Private_Macros CEC Private Macros
* @{
*/
#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
((__MODE__) == CEC_FULL_LISTENING_MODE))
/** @brief Check CEC message size.
* The message size is the payload size: without counting the header,
* it varies from 0 byte (ping operation, one header only, no payload) to
* 15 bytes (1 opcode and up to 14 operands following the header).
* @param __SIZE__ CEC message size.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.
* @param __ADDRESS__ CEC own address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
/** @brief Check CEC initiator or destination logical address setting.
* Initiator and destination addresses are coded over 4 bits.
* @param __ADDRESS__ CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CEC_Private_Functions CEC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* CEC */
#ifdef __cplusplus
}
#endif
#endif /* STM32G0xxHAL_CEC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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USB-PD_Provider_1port/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h Normal file
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@ -0,0 +1,884 @@
/**
******************************************************************************
* @file stm32g0xx_hal_comp.h
* @author MCD Application Team
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0xx_HAL_COMP_H
#define STM32G0xx_HAL_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_ll_exti.h"
/** @addtogroup STM32G0xx_HAL_Driver
* @{
*/
#if defined (COMP1) || defined (COMP2)
/** @addtogroup COMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Types COMP Exported Types
* @{
*/
/**
* @brief COMP Init structure definition
*/
typedef struct
{
uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances
(2 consecutive instances odd and even COMP<x> and COMP<x+1>).
Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode, except for window mode with COMP2 and COMP3 (for devices featuring COMP3): it must be set from COMP3 instance.
This parameter can be a value of @ref COMP_WindowMode */
uint32_t WindowOutput; /*!< Set window mode output.
This parameter can be a value of @ref COMP_WindowOutput */
uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed.
Note: For the characteristics of comparator power modes
(propagation delay and power consumption), refer to device datasheet.
This parameter can be a value of @ref COMP_PowerMode */
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
This parameter can be a value of @ref COMP_InputPlus */
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
This parameter can be a value of @ref COMP_InputMinus */
uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus.
This parameter can be a value of @ref COMP_Hysteresis */
uint32_t OutputPol; /*!< Set comparator output polarity.
This parameter can be a value of @ref COMP_OutputPolarity */
uint32_t BlankingSrce; /*!< Set comparator blanking source.
This parameter can be a value of @ref COMP_BlankingSrce */
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
This parameter can be a value of @ref COMP_EXTI_TriggerMode */
} COMP_InitTypeDef;
/**
* @brief HAL COMP state machine: HAL COMP states definition
*/
#define COMP_STATE_BITFIELD_LOCK (0x10U)
typedef enum
{
HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */
HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
} HAL_COMP_StateTypeDef;
/**
* @brief COMP Handle Structure definition
*/
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
typedef struct __COMP_HandleTypeDef
#else
typedef struct
#endif
{
COMP_TypeDef *Instance; /*!< Register base address */
COMP_InitTypeDef Init; /*!< COMP required parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
__IO uint32_t ErrorCode; /*!< COMP error code */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
} COMP_HandleTypeDef;
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/**
* @brief HAL COMP Callback ID enumeration definition
*/
typedef enum
{
HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
} HAL_COMP_CallbackIDTypeDef;
/**
* @brief HAL COMP Callback pointer definition
*/
typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_Exported_Constants COMP Exported Constants
* @{
*/
/** @defgroup COMP_Error_Code COMP Error Code
* @{
*/
#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL) /*!< Invalid Callback error */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup COMP_WindowMode COMP Window Mode
* @{
*/
#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
#define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | COMP_WINDOWMODE_COMP2) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible). If used from COMP3 instance (when available), comparators instances pair COMP2 and COMP3 have their input plus connected together, the common input is COMP2 input plus (COMP3 input plus is no more accessible). */
/**
* @}
*/
/** @defgroup COMP_WindowOutput COMP Window output
* @{
*/
#define COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. */
#define COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT) /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
#if defined(COMP3)
#define COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT) /*!< Window output synthetized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
#endif
#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */
/**
* @}
*/
/** @defgroup COMP_PowerMode COMP power mode
* @{
*/
/* Note: For the characteristics of comparator power modes */
/* (propagation delay and power consumption), */
/* refer to device datasheet. */
#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */
#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */
/**
* @}
*/
/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
* @{
*/
#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2, pin PB0 for COMP3 (for devices featuring COMP3 instance)) */
#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2, pin PC1 for COMP3 (for devices featuring COMP3 instance)) */
#define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2, pin PE7 for COMP3 (for devices featuring COMP3 instance)) */
/**
* @}
*/
/** @defgroup COMP_InputMinus COMP input minus (inverting input)
* @{
*/
#define COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL) /*!< Comparator input minus connected to 1/4 VrefInt */
#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */
#define COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
#define COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
#define COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2, pin PB2 for COMP3 (for devices featuring COMP3 instance)) */
#define COMP_INPUT_MINUS_IO2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2, pin PC0 for COMP3 (for devices featuring COMP3 instance)) */
#define COMP_INPUT_MINUS_IO3 (COMP_CSR_INMSEL_3 ) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2, pin PE8 for COMP3 (for devices featuring COMP3 instance)) */
/**
* @}
*/
/** @defgroup COMP_Hysteresis COMP hysteresis
* @{
*/
#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */
#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */
#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
/**
* @}
*/
/** @defgroup COMP_OutputPolarity COMP output Polarity
* @{
*/
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
/**
* @}
*/
/** @defgroup COMP_BlankingSrce COMP blanking source
* @{
*/
#define COMP_BLANKINGSRC_NONE (0x00000000UL) /*!<Comparator output without blanking */
/* Note: Output blanking source common to all COMP instances */
#define COMP_BLANKINGSRC_TIM1_OC4 (COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC4 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_1) /*!< Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_2) /*!< Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKING_3) /*!< Comparator output blanking source TIM3 OC3 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
#define COMP_BLANKINGSRC_TIM15_OC2 (COMP_CSR_BLANKING_4) /*!< Comparator output blanking source TIM15 OC2 (common to all COMP instances: COMP1, COMP2, COMP3 (when available)) */
/**
* @}
*/
/** @defgroup COMP_OutputLevel COMP Output Level
* @{
*/
/* Note: Comparator output level values are fixed to "0" and "1", */
/* corresponding COMP register bit is managed by HAL function to match */
/* with these values (independently of bit position in register). */
/* When output polarity is not inverted, comparator output is low when
the input plus is at a lower voltage than the input minus */
#define COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
/* When output polarity is not inverted, comparator output is high when
the input plus is at a higher voltage than the input minus */
#define COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
/**
* @}
*/
/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
* @{
*/
#define COMP_TRIGGERMODE_NONE (0x00000000UL) /*!< Comparator output triggering no External Interrupt Line */
#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Macros COMP Exported Macros
* @{
*/
/** @defgroup COMP_Handle_Management COMP Handle Management
* @{
*/
/** @brief Reset COMP handle state.
* @param __HANDLE__ COMP handle
* @retval None
*/
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
#endif
/**
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
* @param __HANDLE__ COMP handle
* @retval None
*/
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
/**
* @brief Enable the specified comparator.
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
/**
* @brief Disable the specified comparator.
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
/**
* @brief Lock the specified comparator configuration.
* @note Using this macro induce HAL COMP handle state machine being no
* more in line with COMP instance state.
* To keep HAL COMP handle state machine updated, it is recommended
* to use function "HAL_COMP_Lock')".
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
/**
* @brief Check whether the specified comparator is locked.
* @param __HANDLE__ COMP handle
* @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
*/
#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
/**
* @}
*/
/** @defgroup COMP_Exti_Management COMP external interrupt line management
* @{
*/
/**
* @brief Enable the COMP1 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
} while(0)
/**
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
} while(0)
/**
* @brief Enable the COMP1 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Generate a software interrupt on the COMP1 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Check whether the COMP1 EXTI line rising flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP1_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Clear the COMP1 EXTI rising flag.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Check whether the COMP1 EXTI line falling flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Clear the COMP1 EXTI falling flag.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP2 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
} while(0)
/**
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
} while(0)
/**
* @brief Enable the COMP2 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Generate a software interrupt on the COMP2 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Check whether the COMP2 EXTI line rising flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Clear the COMP2 EXTI rising flag.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Check whether the COMP2 EXTI line falling flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP2_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Clear the COMP2 EXTI falling flag.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP3 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Disable the COMP3 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Enable the COMP3 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Disable the COMP3 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Enable the COMP3 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
} while(0)
/**
* @brief Disable the COMP3 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
} while(0)
/**
* @brief Enable the COMP3 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Disable the COMP3 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Generate a software interrupt on the COMP3 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Enable the COMP3 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Disable the COMP3 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Check whether the COMP3 EXTI line rising flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP3_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Clear the COMP3 EXTI rising flag.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Check whether the COMP3 EXTI line falling flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP3_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Clear the COMP3 EXTI falling flag.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP3)
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup COMP_Private_Constants COMP Private Constants
* @{
*/
/** @defgroup COMP_WindowMode_Instance_Differentiator COMP window mode instance differentiator
* @{
*/
#define COMP_WINDOWMODE_COMP2 0x00001000U /*!< COMP window mode using common input of COMP instance: COMP2 */
/**
* @}
*/
/** @defgroup COMP_ExtiLine COMP EXTI Lines
* @{
*/
#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM17) /*!< EXTI line 17 connected to COMP1 output */
#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM18) /*!< EXTI line 18 connected to COMP2 output */
#if defined(COMP3)
#define COMP_EXTI_LINE_COMP3 (EXTI_IMR1_IM20) /*!< EXTI line 20 connected to COMP3 output */
#endif
/**
* @}
*/
/** @defgroup COMP_ExtiLine COMP EXTI Lines
* @{
*/
#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */
#define COMP_EXTI_EVENT (0x00000002UL) /*!< EXTI line event only (without interruption) */
#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */
#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup COMP_Private_Macros COMP Private Macros
* @{
*/
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
* @{
*/
/**
* @brief Get the specified EXTI line for a comparator instance.
* @param __INSTANCE__ specifies the COMP instance.
* @retval value of @ref COMP_ExtiLine
*/
#if defined(COMP3)
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
:((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
: COMP_EXTI_LINE_COMP3)
#else
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
: COMP_EXTI_LINE_COMP2)
#endif
/**
* @}
*/
/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
* @{
*/
#if defined(COMP3)
#define IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__) \
(((__INSTANCE__) == COMP3) \
? \
(((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) \
:\
(((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) \
)
#else
#define IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__) \
(((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) )
#endif
#define IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__) (((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_EACH_COMP) || \
((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP1) || \
((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP2) || \
((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH) )
#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \
((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) )
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3))
#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
((__POL__) == COMP_OUTPUTPOL_INVERTED))
#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \
( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC4) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2) \
)
/* Note: Output blanking source common to all COMP instances */
/* Macro kept for compatibility with other STM32 series */
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
(IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \
((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup COMP_Exported_Functions
* @{
*/
/** @addtogroup COMP_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
pCOMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @}
*/
/* IO operation functions *****************************************************/
/** @addtogroup COMP_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup COMP_Exported_Functions_Group3
* @{
*/
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
/* Callback in interrupt mode */
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* Peripheral State functions **************************************************/
/** @addtogroup COMP_Exported_Functions_Group4
* @{
*/
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* COMP1 || COMP2 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0xx_HAL_COMP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0xx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32g0xx_hal_conf.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0xx_HAL_CONF_H
#define STM32G0xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CEC_MODULE_ENABLED
#define HAL_COMP_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_FDCAN_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LPTIM_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_SMBUS_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
/* ########################## Register Callbacks selection ############################## */
/**
* @brief This is the list of modules where register callback can be used
*/
#define USE_HAL_ADC_REGISTER_CALLBACKS 0u
#define USE_HAL_CEC_REGISTER_CALLBACKS 0u
#define USE_HAL_COMP_REGISTER_CALLBACKS 0u
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u
#define USE_HAL_DAC_REGISTER_CALLBACKS 0u
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0u
#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
#define USE_HAL_I2S_REGISTER_CALLBACKS 0u
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u
#define USE_HAL_HCD_REGISTER_CALLBACKS 0u
#define USE_HAL_PCD_REGISTER_CALLBACKS 0u
#define USE_HAL_RNG_REGISTER_CALLBACKS 0u
#define USE_HAL_RTC_REGISTER_CALLBACKS 0u
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u
#define USE_HAL_SPI_REGISTER_CALLBACKS 0u
#define USE_HAL_TIM_REGISTER_CALLBACKS 0u
#define USE_HAL_UART_REGISTER_CALLBACKS 0u
#define USE_HAL_USART_REGISTER_CALLBACKS 0u
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
/**
* @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
* This internal oscillator is mainly dedicated to provide a high precision clock to
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
* which is subject to manufacturing process variations.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/
#endif /* HSI48_VALUE */
#endif
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S1 peripheral
* This value is used by the RCC HAL module to compute the I2S1 clock source
* frequency.
*/
#if !defined (EXTERNAL_I2S1_CLOCK_VALUE)
#define EXTERNAL_I2S1_CLOCK_VALUE (48000UL) /*!< Value of the I2S1 External clock source in Hz*/
#endif /* EXTERNAL_I2S1_CLOCK_VALUE */
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
/**
* @brief External clock source for I2S2 peripheral
* This value is used by the RCC HAL module to compute the I2S2 clock source
* frequency.
*/
#if !defined (EXTERNAL_I2S2_CLOCK_VALUE)
#define EXTERNAL_I2S2_CLOCK_VALUE 48000U /*!< Value of the I2S2 External clock source in Hz*/
#endif /* EXTERNAL_I2S2_CLOCK_VALUE */
#endif
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define INSTRUCTION_CACHE_ENABLE 1U
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 1U
/* ################## CRYP peripheral configuration ########################## */
#define USE_HAL_CRYP_SUSPEND_RESUME 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include modules header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32g0xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32g0xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32g0xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32g0xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32g0xx_hal_adc.h"
#include "stm32g0xx_hal_adc_ex.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32g0xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32g0xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32g0xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32g0xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32g0xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32g0xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_FDCAN_MODULE_ENABLED
#include "stm32g0xx_hal_fdcan.h"
#endif /* HAL_FDCAN_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32g0xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32g0xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32g0xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32g0xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32g0xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32g0xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32g0xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32g0xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32g0xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32g0xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32g0xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32g0xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32g0xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32g0xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32g0xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32g0xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32g0xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32g0xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for functions parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* STM32G0xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0xx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0xx_HAL_CORTEX_H
#define STM32G0xx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_def.h"
/** @addtogroup STM32G0xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
* @{
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect.
*/
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
} MPU_Region_InitTypeDef;
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/**
* @}
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and Configuration functions *****************************/
void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
* @{
*/
/* Peripheral Control functions *************************************************/
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1U)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if (__MPU_PRESENT == 1)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0xx_HAL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0xx_hal_crc.h
* @author MCD Application Team
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0xx_HAL_CRC_H
#define STM32G0xx_HAL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_def.h"
/** @addtogroup STM32G0xx_HAL_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types
* @{
*/
/**
* @brief CRC HAL State Structure definition
*/
typedef enum
{
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
} HAL_CRC_StateTypeDef;
/**
* @brief CRC Init Structure definition
*/
typedef struct
{
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
is set to DEFAULT_INIT_VALUE_ENABLE. */
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
Can be either one of the following values
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
} CRC_InitTypeDef;
/**
* @brief CRC Handle Structure definition
*/
typedef struct
{
CRC_TypeDef *Instance; /*!< Register base address */
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
HAL_LockTypeDef Lock; /*!< CRC Locking object */
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
must occur if InputBufferFormat is not one of the three values listed above */
} CRC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
*/
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
* @{
*/
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
* @{
*/
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
/**
* @}
*/
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
* @{
*/
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
* the CRC APIs to provide a correct result */
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
/**
* @}
*/
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
/** @brief Reset CRC handle state.
* @param __HANDLE__ CRC handle.
* @retval None
*/
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
* @brief Reset CRC Data Register.
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
* @brief Set CRC INIT non-default value
* @param __HANDLE__ CRC handle
* @param __INIT__ 32-bit initial value
* @retval None
*/
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/**
* @brief Store data in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @param __VALUE__ Value to be stored in the ID register
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
* @brief Return the data stored in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval Value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
((LENGTH) == CRC_POLYLENGTH_16B) || \
((LENGTH) == CRC_POLYLENGTH_8B) || \
((LENGTH) == CRC_POLYLENGTH_7B))
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
/**
* @}
*/
/* Include CRC HAL Extended module */
#include "stm32g0xx_hal_crc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/* Peripheral Control functions ***********************************************/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/* Peripheral State and Error functions ***************************************/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0xx_HAL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32g0xx_hal_crc_ex.h
* @author MCD Application Team
* @brief Header file of CRC HAL extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0xx_HAL_CRC_EX_H
#define STM32G0xx_HAL_CRC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_def.h"
/** @addtogroup STM32G0xx_HAL_Driver
* @{
*/
/** @addtogroup CRCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
* @{
*/
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
* @{
*/
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
/**
* @}
*/
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
* @{
*/
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
* @{
*/
/**
* @brief Set CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/**
* @brief Unset CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
/**
* @brief Set CRC non-default polynomial
* @param __HANDLE__ CRC handle
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
* @retval None
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
* @{
*/
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRCEx_Exported_Functions
* @{
*/
/** @addtogroup CRCEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G0xx_HAL_CRC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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