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Jochen Friedrich
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<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
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<head>
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<meta charset="utf-8" />
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<meta name="generator" content="pandoc" />
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<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
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<title>Release Notes for SN65DP141 Component Drivers</title>
|
||||
<style type="text/css">
|
||||
code{white-space: pre-wrap;}
|
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span.smallcaps{font-variant: small-caps;}
|
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|
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div.column{display: inline-block; vertical-align: top; width: 50%;}
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<body>
|
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<div class="row">
|
||||
<div class="col-sm-12 col-lg-4">
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||||
<div class="card fluid">
|
||||
<div class="sectione dark">
|
||||
<center>
|
||||
<h1 id="release-notes-for-sn65dp141-component-drivers"><small>Release Notes for</small> <mark>SN65DP141 Component Drivers</mark></h1>
|
||||
<p>Copyright © 2017 STMicroelectronics<br />
|
||||
</p>
|
||||
<a href="https://www.st.com" class="logo"><img src="../../../../_htmresc/st_logo.png" alt="ST logo" /></a>
|
||||
</center>
|
||||
</div>
|
||||
</div>
|
||||
<h1 id="license">License</h1>
|
||||
<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
|
||||
<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
|
||||
<h1 id="purpose">Purpose</h1>
|
||||
<p>This directory contains the SN65DP141 component drivers.</p>
|
||||
</div>
|
||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history">Update History</h1>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section13" checked aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.0.2 / 23-July-2020</label>
|
||||
<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Update release notes format</li>
|
||||
<li>Correct misspelled words</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.0.1 / 10-October-2018</label>
|
||||
<div>
|
||||
<h2 id="main-changes-1">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Fix compilation warnings detected by IAR V8.30.1</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.0.0 / 16-November-2017</label>
|
||||
<div>
|
||||
<h2 id="main-changes-2">Main Changes</h2>
|
||||
<ul>
|
||||
<li>First official release of SN65DP141 Component driver</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<footer class="sticky">
|
||||
For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a>
|
||||
</footer>
|
||||
</body>
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</html>
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@ -0,0 +1,346 @@
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/**
|
||||
******************************************************************************
|
||||
* @file sn65dp141.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides a set of functions needed to manage the SN65DP141
|
||||
* DisplayPort Linear Redriver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "sn65dp141.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141
|
||||
* @brief This file provides a set of functions needed to drive the
|
||||
* SN65DP141 DisplayPort Linear Redriver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DisplayPort Linear Redriver Driver structure initialization */
|
||||
DPREDRIVER_Drv_t sn65dp141_drv =
|
||||
{
|
||||
sn65dp141_Init,
|
||||
sn65dp141_DeInit,
|
||||
sn65dp141_PowerOn,
|
||||
sn65dp141_PowerOff,
|
||||
sn65dp141_SetEQGain,
|
||||
sn65dp141_EnableChannel,
|
||||
sn65dp141_DisableChannel
|
||||
};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the SN65DP141 and configure the needed hardware resources.
|
||||
* @param Address Device address on communication Bus.
|
||||
* @retval None
|
||||
*/
|
||||
uint32_t sn65dp141_Init(uint16_t Address)
|
||||
{
|
||||
uint32_t err_count = 0;
|
||||
|
||||
/* Low level init */
|
||||
err_count += MUX_IO_Init();
|
||||
|
||||
/* Restore SN65DP141 registers reset values */
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CFG, 0x00);
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CHEN, 0x00);
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH0_CFG, 0x00);
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH0_EN, 0x00);
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH1_CFG, 0x00);
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH1_EN, 0x00);
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH2_CFG, 0x00);
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH2_EN, 0x00);
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH3_CFG, 0x00);
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CH3_EN, 0x00);
|
||||
|
||||
return err_count;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Release the hardware resources required to use the SN65DP141
|
||||
* @param Address SN65DP141 address on communication Bus.
|
||||
* @retval none
|
||||
*/
|
||||
void sn65dp141_DeInit(uint16_t Address)
|
||||
{
|
||||
/* Restore SN65DP141 registers reset values */
|
||||
MUX_IO_Write(Address, SN65DP141_REG_CFG, 0x00);
|
||||
MUX_IO_Write(Address, SN65DP141_REG_CHEN, 0x00);
|
||||
MUX_IO_Write(Address, SN65DP141_REG_CH0_CFG, 0x00);
|
||||
MUX_IO_Write(Address, SN65DP141_REG_CH0_EN, 0x00);
|
||||
MUX_IO_Write(Address, SN65DP141_REG_CH1_CFG, 0x00);
|
||||
MUX_IO_Write(Address, SN65DP141_REG_CH1_EN, 0x00);
|
||||
MUX_IO_Write(Address, SN65DP141_REG_CH2_CFG, 0x00);
|
||||
MUX_IO_Write(Address, SN65DP141_REG_CH2_EN, 0x00);
|
||||
MUX_IO_Write(Address, SN65DP141_REG_CH3_CFG, 0x00);
|
||||
MUX_IO_Write(Address, SN65DP141_REG_CH3_EN, 0x00);
|
||||
|
||||
/* Low level de-init */
|
||||
MUX_IO_DeInit();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Power on the SN65DP141.
|
||||
* @param Address SN65DP141 address on communication Bus.
|
||||
* @retval 0: successful, else failed
|
||||
*/
|
||||
uint32_t sn65dp141_PowerOn(uint16_t Address)
|
||||
{
|
||||
uint32_t err_count = 0;
|
||||
uint8_t cfg;
|
||||
|
||||
/* Read General Device Settings register*/
|
||||
err_count += MUX_IO_Read(Address, SN65DP141_REG_CFG, &cfg);
|
||||
|
||||
/* Clear PWRDOWN bit of General Device Settings register */
|
||||
cfg &= ~SN65DP141_REG_CFG_PWRDOWN;
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CFG, cfg);
|
||||
|
||||
return err_count;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Power down the SN65DP141.
|
||||
* @param Address SN65DP141 address on communication Bus.
|
||||
* @retval 0: successful, else failed
|
||||
*/
|
||||
uint32_t sn65dp141_PowerOff(uint16_t Address)
|
||||
{
|
||||
uint32_t err_count = 0;
|
||||
uint8_t cfg;
|
||||
|
||||
/* Read General Device Settings register*/
|
||||
err_count += MUX_IO_Read(Address, SN65DP141_REG_CFG, &cfg);
|
||||
|
||||
/* Set PWRDOWN bit of General Device Settings register */
|
||||
cfg |= SN65DP141_REG_CFG_PWRDOWN;
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CFG, cfg);
|
||||
|
||||
return err_count;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the equalizer gain for a given channel.
|
||||
* @param Address SN65DP141 address on communication Bus.
|
||||
* @param ChannelId Channel identifier.
|
||||
* This parameter can be take one of the following values:
|
||||
* CHANNEL_DP0
|
||||
* CHANNEL_DP1
|
||||
* CHANNEL_DP2
|
||||
* CHANNEL_DP3
|
||||
* @param EQGain Equalizer gain.
|
||||
* This parameter must be a value between 0x00 and 0x07.
|
||||
* @retval 0: successful, else failed
|
||||
*/
|
||||
uint32_t sn65dp141_SetEQGain(uint16_t Address,
|
||||
DPREDRIVER_ChannelId_t ChannelId,
|
||||
uint8_t EQGain)
|
||||
{
|
||||
uint32_t err_count = 0;
|
||||
uint8_t chctrl;
|
||||
uint8_t cfg;
|
||||
|
||||
switch(ChannelId)
|
||||
{
|
||||
case CHANNEL_DP0:
|
||||
cfg = SN65DP141_REG_CH0_CFG;
|
||||
break;
|
||||
case CHANNEL_DP1:
|
||||
cfg = SN65DP141_REG_CH1_CFG;
|
||||
break;
|
||||
case CHANNEL_DP2:
|
||||
cfg = SN65DP141_REG_CH2_CFG;
|
||||
break;
|
||||
case CHANNEL_DP3:
|
||||
cfg = SN65DP141_REG_CH3_CFG;
|
||||
break;
|
||||
default:
|
||||
cfg = SN65DP141_REG_CH0_CFG;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Read Channel x Control Settings register */
|
||||
err_count += MUX_IO_Read(Address, cfg, &chctrl);
|
||||
|
||||
/* Set the equalizer gain bit field (EQ setting) for concerned channel */
|
||||
chctrl = (chctrl & (~(uint8_t)SN65DP141_REG_CHxCFG_EQ_SETTING_Msk)) | (EQGain << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos);
|
||||
|
||||
/* Enable Max gain for TX & RX */
|
||||
chctrl |= SN65DP141_REG_CHxCFG_RX_GAIN_1 | SN65DP141_REG_CHxCFG_EQ_DC_GAIN | SN65DP141_REG_CHxCFG_TX_GAIN;
|
||||
|
||||
/* Update Channel x Control Settings register */
|
||||
err_count += MUX_IO_Write(Address, cfg, chctrl);
|
||||
|
||||
return err_count;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable a DP channel.
|
||||
* @param Address SN65DP141 address on communication Bus.
|
||||
* @param ChannelId Channel identifier.
|
||||
* This parameter can be take one of the following values:
|
||||
* CHANNEL_DP0
|
||||
* CHANNEL_DP1
|
||||
* CHANNEL_DP2
|
||||
* CHANNEL_DP3
|
||||
* @retval 0: successful, else failed
|
||||
*/
|
||||
uint32_t sn65dp141_EnableChannel(uint16_t Address,
|
||||
DPREDRIVER_ChannelId_t ChannelId)
|
||||
{
|
||||
uint32_t err_count = 0;
|
||||
uint8_t chen;
|
||||
|
||||
/* Read Channel Enable register */
|
||||
err_count += MUX_IO_Read(Address, SN65DP141_REG_CHEN, &chen);
|
||||
|
||||
/* Clear LN_EN_CHx bit of Channel Enable register */
|
||||
switch(ChannelId)
|
||||
{
|
||||
case CHANNEL_DP0:
|
||||
chen &= ~SN65DP141_REG_CHEN_LN_EN_CH0;
|
||||
break;
|
||||
case CHANNEL_DP1:
|
||||
chen &= ~SN65DP141_REG_CHEN_LN_EN_CH1;
|
||||
break;
|
||||
case CHANNEL_DP2:
|
||||
chen &= ~SN65DP141_REG_CHEN_LN_EN_CH2;
|
||||
break;
|
||||
case CHANNEL_DP3:
|
||||
chen &= ~SN65DP141_REG_CHEN_LN_EN_CH3;
|
||||
break;
|
||||
default:
|
||||
/* Nothing to do */
|
||||
break;
|
||||
}
|
||||
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CHEN, chen);
|
||||
|
||||
return err_count;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a DP channel.
|
||||
* @param Address SN65DP141 address on communication Bus.
|
||||
* @param ChannelId Channel identifier.
|
||||
* This parameter can be take one of the following values:
|
||||
* CHANNEL_DP0
|
||||
* CHANNEL_DP1
|
||||
* CHANNEL_DP2
|
||||
* CHANNEL_DP3
|
||||
* @retval 0: successful, else failed
|
||||
*/
|
||||
uint32_t sn65dp141_DisableChannel(uint16_t Address,
|
||||
DPREDRIVER_ChannelId_t ChannelId)
|
||||
{
|
||||
uint32_t err_count = 0;
|
||||
uint8_t chen;
|
||||
|
||||
/* Read Channel Enable register */
|
||||
err_count += MUX_IO_Read(Address, SN65DP141_REG_CHEN, &chen);
|
||||
|
||||
/* Set LN_EN_CHx bit of Channel Enable register */
|
||||
switch(ChannelId)
|
||||
{
|
||||
case CHANNEL_DP0:
|
||||
chen |= SN65DP141_REG_CHEN_LN_EN_CH0;
|
||||
break;
|
||||
case CHANNEL_DP1:
|
||||
chen |= SN65DP141_REG_CHEN_LN_EN_CH1;
|
||||
break;
|
||||
case CHANNEL_DP2:
|
||||
chen |= SN65DP141_REG_CHEN_LN_EN_CH2;
|
||||
break;
|
||||
case CHANNEL_DP3:
|
||||
chen |= SN65DP141_REG_CHEN_LN_EN_CH3;
|
||||
break;
|
||||
default:
|
||||
/* Nothing to do */
|
||||
break;
|
||||
}
|
||||
|
||||
err_count += MUX_IO_Write(Address, SN65DP141_REG_CHEN, chen);
|
||||
|
||||
return err_count;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,395 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file sn65dp141.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header for sn65dp141.h module
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef SN65DP141_H
|
||||
#define SN65DP141_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
#include "../Common/dpredriver.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SN65DP141
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
/******************************* Register Map ********************************/
|
||||
#define SN65DP141_REG_CFG 0x00 /*!< General Device Settings register */
|
||||
#define SN65DP141_REG_CHEN 0x01 /*!< Channel Enable register */
|
||||
#define SN65DP141_REG_CH0_CFG 0x02 /*!< Channel 0 Control Settings register */
|
||||
#define SN65DP141_REG_CH0_EN 0x03 /*!< Channel 0 Enable Settings register */
|
||||
#define SN65DP141_REG_CH1_CFG 0x05 /*!< Channel 1 Control Settings register */
|
||||
#define SN65DP141_REG_CH1_EN 0x06 /*!< Channel 1 Enable Settings register */
|
||||
#define SN65DP141_REG_CH2_CFG 0x08 /*!< Channel 2 Control Settings register */
|
||||
#define SN65DP141_REG_CH2_EN 0x09 /*!< Channel 2 Enable Settings register */
|
||||
#define SN65DP141_REG_CH3_CFG 0x0B /*!< Channel 3 Control Settings register */
|
||||
#define SN65DP141_REG_CH3_EN 0x0C /*!< Channel 3 Enable Settings register */
|
||||
|
||||
/*********** Bit definition for General Device Settings register *************/
|
||||
#define SN65DP141_REG_CFG_EQ_MODE_Pos (1U)
|
||||
#define SN65DP141_REG_CFG_EQ_MODE_Msk (0x1U << SN65DP141_REG_CFG_EQ_MODE_Pos) /*!< 0x04*/
|
||||
#define SN65DP141_REG_CFG_EQ_MODE SN65DP141_REG_CFG_EQ_MODE_Msk /*!< EQ mode (Cable mode v.s. Trace mode) */
|
||||
#define SN65DP141_REG_CFG_SYNC_ALL_Pos (3U)
|
||||
#define SN65DP141_REG_CFG_SYNC_ALL_Msk (0x1U << SN65DP141_REG_CFG_SYNC_ALL_Pos) /*!< 0x08*/
|
||||
#define SN65DP141_REG_CFG_SYNC_ALL SN65DP141_REG_CFG_SYNC_ALL_Msk /*!< All settings from channel 1 will be used on all channels */
|
||||
#define SN65DP141_REG_CFG_SYNC_23_Pos (4U)
|
||||
#define SN65DP141_REG_CFG_SYNC_23_Msk (0x1U << SN65DP141_REG_CFG_SYNC23_Pos) /*!< 0x10*/
|
||||
#define SN65DP141_REG_CFG_SYNC_23 SN65DP141_REG_CFG_SYNC_23_Msk /*!< All settings from channel 2 will be used for channel 2 and 3 */
|
||||
#define SN65DP141_REG_CFG_SYNC_01_Pos (5U)
|
||||
#define SN65DP141_REG_CFG_SYNC_01_Msk (0x1U << SN65DP141_REG_CFG_SYNC01_Pos) /*!< 0x20*/
|
||||
#define SN65DP141_REG_CFG_SYNC_01 SN65DP141_REG_CFG_SYNC_01_Msk /*!< All settings from channel 1 will be used for channel 0 and 1 */
|
||||
#define SN65DP141_REG_CFG_PWRDOWN_Pos (6U)
|
||||
#define SN65DP141_REG_CFG_PWRDOWN_Msk (0x1U << SN65DP141_REG_CFG_PWRDOWN_Pos) /*!< 0x40*/
|
||||
#define SN65DP141_REG_CFG_PWRDOWN SN65DP141_REG_CFG_PWRDOWN_Msk /*!< Power down the device */
|
||||
#define SN65DP141_REG_CFG_SW_GPIO_Pos (7U)
|
||||
#define SN65DP141_REG_CFG_SW_GPIO_Msk (0x1U << SN65DP141_REG_CFG_SW_GPIO_Pos) /*!< 0x80*/
|
||||
#define SN65DP141_REG_CFG_SW_GPIO SN65DP141_REG_CFG_SW_GPIO_Msk /*!< Switching logic is controlled by GPIO or I2C */
|
||||
|
||||
/*********** Bit definition for Channel Enable register *************/
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH0_Pos (0U)
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH0_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH0_Pos) /*!< 0x01 */
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH0 SN65DP141_REG_CHEN_LN_EN_CH0_Msk /*!< Channel 0 enable */
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH1_Pos (1U)
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH1_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH1_Pos) /*!< 0x02 */
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH1 SN65DP141_REG_CHEN_LN_EN_CH1_Msk /*!< Channel 1 enable */
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH2_Pos (2U)
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH2_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH2_Pos) /*!< 0x04 */
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH2 SN65DP141_REG_CHEN_LN_EN_CH2_Msk /*!< Channel 2 enable */
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH3_Pos (3U)
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH3_Msk (0x1U << SN65DP141_REG_CHEN_LN_EN_CH3_Pos) /*!< 0x08 */
|
||||
#define SN65DP141_REG_CHEN_LN_EN_CH3 SN65DP141_REG_CHEN_LN_EN_CH3_Msk /*!< Channel 3 enable */
|
||||
|
||||
/*********** Bit definition for Channel x Control Settings register *************/
|
||||
#define SN65DP141_REG_CHxCFG_RX_GAIN_Pos (0U)
|
||||
#define SN65DP141_REG_CHxCFG_RX_GAIN_Msk (0x3U << SN65DP141_REG_CHxCFG_RX_GAIN_Pos) /*!< 0x03 */
|
||||
#define SN65DP141_REG_CHxCFG_RX_GAIN SN65DP141_REG_CHxCFG_RX_GAIN_Msk /*!< Channel[x] RX_GAIN control */
|
||||
#define SN65DP141_REG_CHxCFG_RX_GAIN_0 (0x1U << SN65DP141_REG_CHxCFG_RX_GAIN_Pos) /*!< 0x01 */
|
||||
#define SN65DP141_REG_CHxCFG_RX_GAIN_1 (0x2U << SN65DP141_REG_CHxCFG_RX_GAIN_Pos) /*!< 0x02 */
|
||||
#define SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Pos (2U)
|
||||
#define SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Msk (0x1U << SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Pos) /*!< 0x04 */
|
||||
#define SN65DP141_REG_CHxCFG_EQ_DC_GAIN SN65DP141_REG_CHxCFG_EQ_DC_GAIN_Msk /*!< Channel[x] EQ DC gain */
|
||||
#define SN65DP141_REG_CHxCFG_TX_GAIN_Pos (3U)
|
||||
#define SN65DP141_REG_CHxCFG_TX_GAIN_Msk (0x1U << SN65DP141_REG_CHxCFG_TX_GAIN_Pos) /*!< 0x08 */
|
||||
#define SN65DP141_REG_CHxCFG_TX_GAIN SN65DP141_REG_CHxCFG_TX_GAIN_Msk /*!< Channel[x] TX_DC_GAIN control */
|
||||
#define SN65DP141_REG_CHxCFG_EQ_SETTING_Pos (4U)
|
||||
#define SN65DP141_REG_CHxCFG_EQ_SETTING_Msk (0x7U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x70 */
|
||||
#define SN65DP141_REG_CHxCFG_EQ_SETTING SN65DP141_REG_CHxCFG_EQ_SETTING_Msk /*!< Channel[x] TX_DC_GAIN control */
|
||||
#define SN65DP141_REG_CHxCFG_EQ_SETTING_0 (0x1U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x10 */
|
||||
#define SN65DP141_REG_CHxCFG_EQ_SETTING_1 (0x2U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x20 */
|
||||
#define SN65DP141_REG_CHxCFG_EQ_SETTING_2 (0x4U << SN65DP141_REG_CHxCFG_EQ_SETTING_Pos) /*!< 0x40 */
|
||||
|
||||
/*********** Bit definition for Channel x Enable Settings register *************/
|
||||
#define SN65DP141_REG_CHxCTL_DRV_EN_Pos (0U)
|
||||
#define SN65DP141_REG_CHxCTL_DRV_EN_Msk (0x1U << SN65DP141_REG_CHxCTL_DRV_EN_Pos) /*!< 0x01 */
|
||||
#define SN65DP141_REG_CHxCTL_DRV_EN SN65DP141_REG_CHxCTL_DRV_EN_Msk /*!< Channel[0] driver stage enable */
|
||||
#define SN65DP141_REG_CHxCTL_EQ_EN_Pos (1U)
|
||||
#define SN65DP141_REG_CHxCTL_EQ_EN_Msk (0x1U << SN65DP141_REG_CHxCTL_EQ_EN_Pos) /*!< 0x02 */
|
||||
#define SN65DP141_REG_CHxCTL_EQ_EN SN65DP141_REG_CHxCTL_EQ_EN_Msk /*!< Channel[0] EQ stage enable */
|
||||
#define SN65DP141_REG_CHxCTL_DRV_PEAK_Pos (2U)
|
||||
#define SN65DP141_REG_CHxCTL_DRV_PEAK_Msk (0x1U << SN65DP141_REG_CHxCTL_DRV_PEAK_Pos) /*!< 0x04 */
|
||||
#define SN65DP141_REG_CHxCTL_DRV_PEAK SN65DP141_REG_CHxCTL_DRV_PEAK_Msk /*!< Channel[0] driver peaking */
|
||||
|
||||
/** @defgroup SN65DP141_Channel_Identifier
|
||||
* @{
|
||||
*/
|
||||
#define SN65DP141_CHANNEL_1 0x00U
|
||||
#define SN65DP141_CHANNEL_2 0x01U
|
||||
#define SN65DP141_CHANNEL_3 0x04U
|
||||
#define SN65DP141_CHANNEL_4 0x08U
|
||||
#define SN65DP141_CHANNEL_ALL 0x0FU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_EQ_Mode
|
||||
* @{
|
||||
*/
|
||||
#define SN65DP141_EQ_MODE_CABLE 0x00U
|
||||
#define SN65DP141_EQ_MODE_TRACE SN65DP141_REG_CFG_EQ_MODE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Channel_Tracking
|
||||
* @{
|
||||
*/
|
||||
#define SN65DP141_CHANNEL_TRACKING_NONE 0x00U
|
||||
#define SN65DP141_CHANNEL_TRACKING_01 SN65DP141_REG_CFG_SYNC_01
|
||||
#define SN65DP141_CHANNEL_TRACKING_23 SN65DP141_REG_CFG_SYNC_23
|
||||
#define SN65DP141_CHANNEL_TRACKING_ALL SN65DP141_REG_CFG_SYNC_ALL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_EQGAIN SN65DP141 Equalizer Gain
|
||||
* @{
|
||||
*/
|
||||
#define SN65DP141_EQGAIN_0 0x0U
|
||||
#define SN65DP141_EQGAIN_1 0x1U
|
||||
#define SN65DP141_EQGAIN_2 0x2U
|
||||
#define SN65DP141_EQGAIN_3 0x3U
|
||||
#define SN65DP141_EQGAIN_4 0x4U
|
||||
#define SN65DP141_EQGAIN_5 0x5U
|
||||
#define SN65DP141_EQGAIN_6 0x6U
|
||||
#define SN65DP141_EQGAIN_7 0x7U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Channel_RXGAIN
|
||||
* @{
|
||||
*/
|
||||
#define SN65DP141_CHANNEL_RXGAIN_LOW 0x00U
|
||||
#define SN65DP141_CHANNEL_RXGAIN_HIZ SN65DP141_REG_CHxCFG_RX_GAIN_0
|
||||
#define SN65DP141_CHANNEL_RXGAIN_HIGH SN65DP141_REG_CHxCFG_RX_GAIN_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Channel_EQDCGAIN
|
||||
* @{
|
||||
*/
|
||||
#define SN65DP141_CHANNEL_EQDCGAIN_MINUS6DB 0x00U
|
||||
#define SN65DP141_CHANNEL_EQDCGAIN_0DB SN65DP141_REG_CHxCFG_EQ_DC_GAIN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Channel_TXGAIN
|
||||
* @{
|
||||
*/
|
||||
#define SN65DP141_CHANNEL_RXGAIN_0DB 0x00U
|
||||
#define SN65DP141_CHANNEL_RXGAIN_6DB SN65DP141_REG_CHxCFG_TX_GAIN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SN65DP141_DEBUG)
|
||||
/** @defgroup SN65DP141_Exported_Structure SN65DP141 Exported Structure
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RESERVED :2;
|
||||
uint8_t EQ_MODE :1;
|
||||
uint8_t SYNC_ALL :1;
|
||||
uint8_t SYNC_23 :1;
|
||||
uint8_t SYNC_01 :1;
|
||||
uint8_t PWRDOWN :1;
|
||||
uint8_t SW_GPIO :1;
|
||||
};
|
||||
} SN65DP141_GeneralTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t LN_EN_CH0 :1;
|
||||
uint8_t LN_EN_CH1 :1;
|
||||
uint8_t LN_EN_CH2 :1;
|
||||
uint8_t LN_EN_CH3 :1;
|
||||
uint8_t RESERVED :4;
|
||||
};
|
||||
} SN65DP141_ChannelEnableTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RX_GAIN_0 :1;
|
||||
uint8_t RX_GAIN_1 :1;
|
||||
uint8_t EQ_DC_GAIN :1;
|
||||
uint8_t TX_GAIN :1;
|
||||
uint8_t EQ_Setting_0 :1;
|
||||
uint8_t EQ_Setting_1 :1;
|
||||
uint8_t EQ_Setting_2 :1;
|
||||
uint8_t RESERVED :1;
|
||||
};
|
||||
} SN65DP141_Channel0CtrlTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RSVDRV_EN :1;
|
||||
uint8_t EQ_EN :1;
|
||||
uint8_t DRV_PEAK :1;
|
||||
uint8_t RESERVED :5;
|
||||
};
|
||||
} SN65DP141_Channel0EnableTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RX_GAIN_0 :1;
|
||||
uint8_t RX_GAIN_1 :1;
|
||||
uint8_t EQ_DC_GAIN :1;
|
||||
uint8_t TX_GAIN :1;
|
||||
uint8_t EQ_Setting_0 :1;
|
||||
uint8_t EQ_Setting_1 :1;
|
||||
uint8_t EQ_Setting_2 :1;
|
||||
uint8_t RESERVED :1;
|
||||
};
|
||||
} SN65DP141_Channel1CtrlTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RSVDRV_EN :1;
|
||||
uint8_t EQ_EN :1;
|
||||
uint8_t DRV_PEAK :1;
|
||||
uint8_t RESERVED :5;
|
||||
};
|
||||
} SN65DP141_Channel1EnableTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RX_GAIN_0 :1;
|
||||
uint8_t RX_GAIN_1 :1;
|
||||
uint8_t EQ_DC_GAIN :1;
|
||||
uint8_t TX_GAIN :1;
|
||||
uint8_t EQ_Setting_0 :1;
|
||||
uint8_t EQ_Setting_1 :1;
|
||||
uint8_t EQ_Setting_2 :1;
|
||||
uint8_t RESERVED :1;
|
||||
};
|
||||
} SN65DP141_Channel2CtrlTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RSVDRV_EN :1;
|
||||
uint8_t EQ_EN :1;
|
||||
uint8_t DRV_PEAK :1;
|
||||
uint8_t RESERVED :5;
|
||||
};
|
||||
} SN65DP141_Channel2EnableTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RX_GAIN_0 :1;
|
||||
uint8_t RX_GAIN_1 :1;
|
||||
uint8_t EQ_DC_GAIN :1;
|
||||
uint8_t TX_GAIN :1;
|
||||
uint8_t EQ_Setting_0 :1;
|
||||
uint8_t EQ_Setting_1 :1;
|
||||
uint8_t EQ_Setting_2 :1;
|
||||
uint8_t RESERVED :1;
|
||||
};
|
||||
} SN65DP141_Channel3CtrlTypeDef;
|
||||
|
||||
typedef union {
|
||||
uint8_t Register;
|
||||
struct {
|
||||
uint8_t RSVDRV_EN :1;
|
||||
uint8_t EQ_EN :1;
|
||||
uint8_t DRV_PEAK :1;
|
||||
uint8_t RESERVED :5;
|
||||
};
|
||||
} SN65DP141_Channel3EnableTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
SN65DP141_GeneralTypeDef General; /*!< 0x00 (General Device Settings) */
|
||||
SN65DP141_ChannelEnableTypeDef ChannelEnable; /*!< 0x01 (Channel Enable) */
|
||||
SN65DP141_Channel0CtrlTypeDef Channel0Ctrl; /*!< 0x02 (Channel 0 Control Settings) */
|
||||
SN65DP141_Channel0EnableTypeDef Channel0Enable; /*!< 0x03 (Channel 0 Enable Settings) */
|
||||
SN65DP141_Channel1CtrlTypeDef Channel1Ctrl; /*!< 0x05 (Channel 1 Control Settings) */
|
||||
SN65DP141_Channel1EnableTypeDef Channel1Enable; /*!< 0x06 (Channel 1 Enable Settings) */
|
||||
SN65DP141_Channel2CtrlTypeDef Channel2Ctrl; /*!< 0x08 (Channel 2 Control Settings) */
|
||||
SN65DP141_Channel2EnableTypeDef Channel2Enable; /*!< 0x09 (Channel 2 Enable Settings) */
|
||||
SN65DP141_Channel3CtrlTypeDef Channel3Ctrl; /*!< 0x0B (Channel 3 Control Settings) */
|
||||
SN65DP141_Channel3EnableTypeDef Channel3Enable; /*!< 0x0C (Channel 3 Enable Settings) */
|
||||
} SN65DP141_RegistersTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SN65DP141_DEBUG */
|
||||
|
||||
/** @defgroup SN65DP141_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t sn65dp141_Init(uint16_t Address);
|
||||
void sn65dp141_DeInit(uint16_t Address);
|
||||
uint32_t sn65dp141_PowerOn(uint16_t Address);
|
||||
uint32_t sn65dp141_PowerOff(uint16_t Address);
|
||||
uint32_t sn65dp141_SetEQGain(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId, uint8_t EQGain);
|
||||
uint32_t sn65dp141_EnableChannel(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId);
|
||||
uint32_t sn65dp141_DisableChannel(uint16_t Address, DPREDRIVER_ChannelId_t ChannelId);
|
||||
|
||||
/* MUX IO functions */
|
||||
uint8_t MUX_IO_Init(void);
|
||||
void MUX_IO_DeInit(void);
|
||||
uint8_t MUX_IO_Write(uint16_t Addr, uint16_t Reg, uint8_t Data);
|
||||
uint8_t MUX_IO_Read(uint16_t Addr, uint16_t Reg, uint8_t *pData);
|
||||
uint32_t MUX_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SN65DP141_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/* DisplayPort Linear Redriver Driver structure */
|
||||
extern DPREDRIVER_Drv_t sn65dp141_drv;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SN65DP141_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
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Reference in a new issue